diff options
| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2017-01-15 22:36:27 -0600 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-02-02 18:22:41 +1100 |
| commit | 8fd997ad5136b86016139c26db9e605bcdb89d26 (patch) | |
| tree | a686a29aa5825e2fe8d70c42950bb3697f0e033f /include/xive.h | |
| parent | 590212dc7e427b8b228de05c7747a7fe0cc44773 (diff) | |
| download | blackbird-skiboot-8fd997ad5136b86016139c26db9e605bcdb89d26.tar.gz blackbird-skiboot-8fd997ad5136b86016139c26db9e605bcdb89d26.zip | |
xive: Set the FORCE_TM_LOCAL bit in CQ_PBI_CTL
This bits saves the day if the special EX BARs happens to
be misconfigured. There is no drawback to having it always
set so let's do so.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include/xive.h')
| -rw-r--r-- | include/xive.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/include/xive.h b/include/xive.h index ab5ab80a..e9a01c34 100644 --- a/include/xive.h +++ b/include/xive.h @@ -64,6 +64,7 @@ #define CQ_PBI_PC_64K PPC_BIT(5) #define CQ_PBI_VC_64K PPC_BIT(6) #define CQ_PBI_LNX_TRIG PPC_BIT(7) +#define CQ_PBI_FORCE_TM_LOCAL PPC_BIT(22) #define CQ_PBO_CTL 0x108 #define CQ_AIB_CTL 0x110 #define X_CQ_RST_CTL 0x23 @@ -296,6 +297,10 @@ * * Then we have all these "special" CI ops at these offset that trigger * all sorts of side effects: + * + * We can OR'in these a cache line index from 0...3 (ie, 0, 0x80, 0x100, 0x180) + * to select a specific snooper. 0 is pretty busy so 0x80 or 0x100 is recommended + * XXX TODO. add that and find way to tell KVM about it. */ #define TM_SPC_ACK_EBB 0x800 /* Load8 ack EBB to reg*/ #define TM_SPC_ACK_OS_REG 0x810 /* Load16 ack OS irq to reg */ |
