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| author | Gavin Shan <gwshan@linux.vnet.ibm.com> | 2016-10-20 14:17:17 +1100 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2016-10-24 12:14:58 +1100 |
| commit | 18d590eee08be63b5971a4e2a80d571c86b3a305 (patch) | |
| tree | 10d07db8d12e5fd4faa4146682851300391c6358 /include/phb3.h | |
| parent | da11e003fa1a77199a6fd67b2215d0a51e4f731d (diff) | |
| download | blackbird-skiboot-18d590eee08be63b5971a4e2a80d571c86b3a305.tar.gz blackbird-skiboot-18d590eee08be63b5971a4e2a80d571c86b3a305.zip | |
pci: make PCI slot state as incremental to base number
Various backends define their own PCI slot states for flexibility
with numbers [A]. PCI core also defines its PCI slot states [B].
For one specific PCI slot state, the major number of [A] and [B]
should be same so that the corresponding operation can be found.
It means [A] and [B] are relevant to some extent, but the code
where defines the PCI slots in backends doesn't reflect it.
This makes the major PCI slot state defined in backend same to
the corresponding one defined in PCI core. The minor PCI slot
states are made to be incremental to their base number (major
PCI slot state). No functional changes introduced.
Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Acked-by: Russell Currey <ruscur@russell.cc>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include/phb3.h')
| -rw-r--r-- | include/phb3.h | 40 |
1 files changed, 20 insertions, 20 deletions
diff --git a/include/phb3.h b/include/phb3.h index cf4b910d..dbf3c386 100644 --- a/include/phb3.h +++ b/include/phb3.h @@ -211,26 +211,26 @@ enum phb3_state { * changes here, please make sure the base state isn't * conflicting with those defined in pci-slot.h */ -#define PHB3_SLOT_NORMAL 0x00000000 -#define PHB3_SLOT_LINK 0x00000100 -#define PHB3_SLOT_LINK_START 0x00000101 -#define PHB3_SLOT_LINK_WAIT_ELECTRICAL 0x00000102 -#define PHB3_SLOT_LINK_WAIT 0x00000103 -#define PHB3_SLOT_HRESET 0x00000200 -#define PHB3_SLOT_HRESET_START 0x00000201 -#define PHB3_SLOT_HRESET_DELAY 0x00000202 -#define PHB3_SLOT_HRESET_DELAY2 0x00000203 -#define PHB3_SLOT_FRESET 0x00000300 -#define PHB3_SLOT_FRESET_START 0x00000301 -#define PHB3_SLOT_PFRESET 0x00000400 -#define PHB3_SLOT_PFRESET_START 0x00000401 -#define PHB3_SLOT_PFRESET_ASSERT_DELAY 0x00000402 -#define PHB3_SLOT_PFRESET_DEASSERT_DELAY 0x00000403 -#define PHB3_SLOT_CRESET 0x00000500 -#define PHB3_SLOT_CRESET_START 0x00000501 -#define PHB3_SLOT_CRESET_WAIT_CQ 0x00000502 -#define PHB3_SLOT_CRESET_REINIT 0x00000503 -#define PHB3_SLOT_CRESET_FRESET 0x00000504 +#define PHB3_SLOT_NORMAL PCI_SLOT_STATE_NORMAL +#define PHB3_SLOT_LINK PCI_SLOT_STATE_LINK +#define PHB3_SLOT_LINK_START (PHB3_SLOT_LINK + 1) +#define PHB3_SLOT_LINK_WAIT_ELECTRICAL (PHB3_SLOT_LINK + 2) +#define PHB3_SLOT_LINK_WAIT (PHB3_SLOT_LINK + 3) +#define PHB3_SLOT_HRESET PCI_SLOT_STATE_HRESET +#define PHB3_SLOT_HRESET_START (PHB3_SLOT_HRESET + 1) +#define PHB3_SLOT_HRESET_DELAY (PHB3_SLOT_HRESET + 2) +#define PHB3_SLOT_HRESET_DELAY2 (PHB3_SLOT_HRESET + 3) +#define PHB3_SLOT_FRESET PCI_SLOT_STATE_FRESET +#define PHB3_SLOT_FRESET_START (PHB3_SLOT_FRESET + 1) +#define PHB3_SLOT_PFRESET PCI_SLOT_STATE_PFRESET +#define PHB3_SLOT_PFRESET_START (PHB3_SLOT_PFRESET + 1) +#define PHB3_SLOT_PFRESET_ASSERT_DELAY (PHB3_SLOT_PFRESET + 2) +#define PHB3_SLOT_PFRESET_DEASSERT_DELAY (PHB3_SLOT_PFRESET + 3) +#define PHB3_SLOT_CRESET PCI_SLOT_STATE_CRESET +#define PHB3_SLOT_CRESET_START (PHB3_SLOT_CRESET + 1) +#define PHB3_SLOT_CRESET_WAIT_CQ (PHB3_SLOT_CRESET + 2) +#define PHB3_SLOT_CRESET_REINIT (PHB3_SLOT_CRESET + 3) +#define PHB3_SLOT_CRESET_FRESET (PHB3_SLOT_CRESET + 4) /* * PHB3 error descriptor. Errors from all components (PBCQ, PHB) |
