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| author | Mike Qiu <qiudayu@linux.vnet.ibm.com> | 2014-07-02 04:02:07 -0400 |
|---|---|---|
| committer | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2014-07-21 14:48:45 +1000 |
| commit | 9cd97494117f86b84e8b946d025226035acff70e (patch) | |
| tree | 1d9de3f712b77a096b25da24486915544b618b74 /include/p7ioc-regs.h | |
| parent | 5377c73b25c6b19c3b3d238a5bcc7d5f1348ea45 (diff) | |
| download | blackbird-skiboot-9cd97494117f86b84e8b946d025226035acff70e.tar.gz blackbird-skiboot-9cd97494117f86b84e8b946d025226035acff70e.zip | |
P7IOC: Support error injection
The patch implements P7IOC backend to support error injection. There are
3 registers (control, address and mask) for each P7IOC PHB to do error
injection. The way to do error injection is straight-forward. For IO,
MMIO and PCI-CFG error injection, we check the address is valid or not.
The address will be used for error injection if that's valid. Otherwise,
we have to figure one out from IODT, M32DT or PELTM.
As DMA address is natually invisible to users, we just figure it out from
TVT and use that for error injection.
64-bits error injection will be supported later.
Signed-off-by: Mike Qiu <qiudayu@linux.vnet.ibm.com>
Reviewed-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'include/p7ioc-regs.h')
| -rw-r--r-- | include/p7ioc-regs.h | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/include/p7ioc-regs.h b/include/p7ioc-regs.h index daac1eb6..2cd5b75a 100644 --- a/include/p7ioc-regs.h +++ b/include/p7ioc-regs.h @@ -164,9 +164,24 @@ #define PHB_PHB2_TCE_CAP 0x258 #define PHB_PHB2_IRQ_CAP 0x260 #define PHB_PHB2_EEH_CAP 0x268 -#define PHB_PAPR_ERR_INJ_CONTROL 0x2b0 +#define PHB_PAPR_ERR_INJ_CTL 0x2b0 +#define PHB_PAPR_ERR_INJ_CTL_INB PPC_BIT(0) +#define PHB_PAPR_ERR_INJ_CTL_OUTB PPC_BIT(1) +#define PHB_PAPR_ERR_INJ_CTL_STICKY PPC_BIT(2) +#define PHB_PAPR_ERR_INJ_CTL_CFG PPC_BIT(3) +#define PHB_PAPR_ERR_INJ_CTL_RD PPC_BIT(4) +#define PHB_PAPR_ERR_INJ_CTL_WR PPC_BIT(5) +#define PHB_PAPR_ERR_INJ_CTL_FREEZE PPC_BIT(6) #define PHB_PAPR_ERR_INJ_ADDR 0x2b8 #define PHB_PAPR_ERR_INJ_MASK 0x2c0 +#define PHB_PAPR_ERR_INJ_MASK_CFG_MASK PPC_BITMASK(4,11) +#define PHB_PAPR_ERR_INJ_MASK_CFG_LSH PPC_BITLSHIFT(11) +#define PHB_PAPR_ERR_INJ_MASK_MMIO_MASK PPC_BITMASK(16,39) /* 16M aligned */ +#define PHB_PAPR_ERR_INJ_MASK_MMIO_LSH PPC_BITLSHIFT(39) +#define PHB_PAPR_ERR_INJ_MASK_IO_MASK PPC_BITMASK(16,47) /* 64K aligned */ +#define PHB_PAPR_ERR_INJ_MASK_IO_LSH PPC_BITLSHIFT(47) +#define PHB_PAPR_ERR_INJ_MASK_DMA_MASK PPC_BITMASK(60,63) /* 16 window */ +#define PHB_PAPR_ERR_INJ_MASK_DMA_LSH PPC_BITLSHIFT(63) #define PHB_ETU_ERR_SUMMARY 0x2c8 /* UTL registers */ |
