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authorAlistair Popple <alistair@popple.id.au>2017-03-24 12:22:26 +1100
committerStewart Smith <stewart@linux.vnet.ibm.com>2017-03-30 19:37:48 +1100
commitd95ffaa6fac5b0094cb473ad6bbc8923ce4107d7 (patch)
treefb9459fb492c9a9b909376c57b9ca573712a4ab8 /include/npu2.h
parent5180d6555b098f67013d28c388285199b47c911b (diff)
downloadblackbird-skiboot-d95ffaa6fac5b0094cb473ad6bbc8923ce4107d7.tar.gz
blackbird-skiboot-d95ffaa6fac5b0094cb473ad6bbc8923ce4107d7.zip
npu2: Add hardware link training procedures
Unlike other system buses the NVLink2 links need to be trained at runtime as training requires interaction from the GPU device drivers. This patch implements the required training procedures for NVLink2, which are different than the NVLink1 equivalents. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include/npu2.h')
-rw-r--r--include/npu2.h9
1 files changed, 8 insertions, 1 deletions
diff --git a/include/npu2.h b/include/npu2.h
index d535e656..64d6dc09 100644
--- a/include/npu2.h
+++ b/include/npu2.h
@@ -25,6 +25,10 @@
#define NPU2ERR(p, fmt, a...) prlog(PR_ERR, "NPU%d: " fmt, \
(p)->phb.opal_id, ##a)
+#define NPU2DEVDBG(p, fmt, a...) NPU2DBG((p)->npu, fmt, ##a)
+#define NPU2DEVINF(p, fmt, a...) NPU2INF((p)->npu, fmt, ##a)
+#define NPU2DEVERR(p, fmt, a...) NPU2ERR((p)->npu, fmt, ##a)
+
/* Number of PEs supported */
#define NPU2_MAX_PE_NUM 16
#define NPU2_RESERVED_PE_NUM 15
@@ -78,6 +82,7 @@ struct npu2_dev {
uint32_t index;
uint32_t flags;
uint64_t xscom;
+ uint64_t pl_xscom_base;
void *regs;
struct dt_node *dt_node;
struct npu2_pcie_bar bars[2];
@@ -94,11 +99,13 @@ struct npu2_dev {
struct phb *phb;
struct pci_device *pd;
+ int ntl_reset_done;
+
/* Vendor specific capability */
uint32_t vendor_cap;
/* Which PHY lanes this device is associated with */
- uint16_t lane_mask;
+ uint32_t lane_mask;
/* Track currently running procedure and step number */
uint16_t procedure_number;
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