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| author | Michael Neuling <mikey@neuling.org> | 2017-11-14 22:23:03 +1100 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-11-15 01:03:53 -0600 |
| commit | 3c0408ded5a14e110c8a418be305ac20714cb32d (patch) | |
| tree | fffea6eddefcd516b1d62021d361aef86767a388 /include/npu2-regs.h | |
| parent | 4f4bf83128c1d944782f02b238e632ed8d2451af (diff) | |
| download | blackbird-skiboot-3c0408ded5a14e110c8a418be305ac20714cb32d.tar.gz blackbird-skiboot-3c0408ded5a14e110c8a418be305ac20714cb32d.zip | |
npu2: Refactor BAR setting code
This refactors the BAR setting code to make it clearer and handle a
larger range of BAR addresses. This is needed as we are about to move
the GPU to a physical address that is currently not supported by this
code.
This change derives group and chip sections of the BAR from the base
address rather than the chip_id now. mem sel is also derived from the
base address, rather than assuming 0.
No functional change.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Reviewed-by: Balbir Singh <bsingharora@gmail.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include/npu2-regs.h')
| -rw-r--r-- | include/npu2-regs.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/include/npu2-regs.h b/include/npu2-regs.h index ab046aca..ae556612 100644 --- a/include/npu2-regs.h +++ b/include/npu2-regs.h @@ -105,7 +105,8 @@ void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask); #define NPU2_TIMER_CFG 0x018 #define NPU2_GPU0_MEM_BAR 0x020 #define NPU2_GPU1_MEM_BAR 0x028 -#define NPU2_MEM_BAR_SEL_MEM PPC_BITMASK(0,2) +#define NPU2_MEM_BAR_EN PPC_BIT(0) +#define NPU2_MEM_BAR_SEL_MEM PPC_BITMASK(1,2) #define NPU2_MEM_BAR_GROUP PPC_BITMASK(3,6) #define NPU2_MEM_BAR_CHIP PPC_BITMASK(7,9) #define NPU2_MEM_BAR_NODE_ADDR PPC_BITMASK(10,21) |
