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| author | Milton Miller <miltonm@us.ibm.com> | 2016-09-02 14:39:57 +1000 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2016-09-02 15:27:39 +1000 |
| commit | 8f67ee3b7fa573885c2bda34c7934418e12287db (patch) | |
| tree | 9292fd01b830d325702381e73db8bce11fda98dd /include/npu-regs.h | |
| parent | 863ac3c5d2f8a5ea5d471167f3da5cb07aab72fc (diff) | |
| download | blackbird-skiboot-8f67ee3b7fa573885c2bda34c7934418e12287db.tar.gz blackbird-skiboot-8f67ee3b7fa573885c2bda34c7934418e12287db.zip | |
hw/npu: program NPU BUID reg properly
The NPU BUID register was incorrectly programmed resulting in npu
interrupt level 0 causing a PB_CENT_CRESP_ADDR_ERROR checkstop,
and irqs from npus in odd chips being aliased to and processed
as the interrupts from the corresponding npu on the even chips.
The documentation for the BUID register is confusing, describing
required values of some bits and bits of differing meaning within
contained within one field.
This patch seperates the per-irq-level irq enable mask from the
documented buid base field, leaving the buid base as the part that
is directly compared. It documents the buid as the boundary of a
block of 16 sources (in the form of a 4 bit shift), and documents
that some bits are sourced from another register and are always
compared to that register, so they are not required to be set in
the base and mask fields.
Fixes: cc61799 Nvlink: Add NPU PHB functions
Signed-off-by: Milton Miller <miltonm@us.ibm.com>
Signed-off-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include/npu-regs.h')
| -rw-r--r-- | include/npu-regs.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/include/npu-regs.h b/include/npu-regs.h index f663a987..4f1a19c2 100644 --- a/include/npu-regs.h +++ b/include/npu-regs.h @@ -52,7 +52,9 @@ #define NX_AS_CMD_CFG 0x12 #define NX_NP_BUID 0x13 #define NP_BUID_ENABLE PPC_BIT(0) -#define NP_BUID_BASE PPC_BITMASK(1,23) +#define NP_BUID_BASE PPC_BITMASK(1,15) +#define NP_IRQ_LEVELS PPC_BITMASK(16,23) +#define NP_BUID_MASK PPC_BITMASK(24,32) #define NX_TL_CMD_CR 0x20 #define NX_TL_CMD_D_CR 0x21 #define NX_TL_RSP_CR 0x22 |
