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| author | Cyril Bur <cyril.bur@au1.ibm.com> | 2017-05-24 16:37:17 +1000 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-05-26 15:55:23 +1000 |
| commit | 0322cd881ab3fda2b8136d6beb3991fd9d2dc5e7 (patch) | |
| tree | 6f2625adc7db89fb61a06ec814ea4699915d3787 /include/lpc-mbox.h | |
| parent | cc40ffb3a20f02ae968cebc9a0f0af8e8825bfb3 (diff) | |
| download | blackbird-skiboot-0322cd881ab3fda2b8136d6beb3991fd9d2dc5e7.tar.gz blackbird-skiboot-0322cd881ab3fda2b8136d6beb3991fd9d2dc5e7.zip | |
hw/lpc-mbox: Use message registers for interrupts
Currently the BMC raises the interrupt using the BMC control register.
It does so on all accesses to the 16 'data' registers meaning that when
the BMC only wants to set the ATTN (on which we have interrupts enabled)
bit we will also get a control register based interrupt.
The solution here is to mask that interrupt permanantly and enable
interrupts on the protocol defined 'response' data byte.
Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com>
Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Acked-by: Cyril Bur <cyril.bur@au1.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include/lpc-mbox.h')
| -rw-r--r-- | include/lpc-mbox.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/include/lpc-mbox.h b/include/lpc-mbox.h index c67efee9..14e38cf8 100644 --- a/include/lpc-mbox.h +++ b/include/lpc-mbox.h @@ -20,9 +20,9 @@ #include <opal.h> #include <ccan/endian/endian.h> -/* Not 16 because the last two are interrupt based status regs */ -#define BMC_MBOX_DATA_REGS 14 #define BMC_MBOX_ARGS_REGS 11 +#define BMC_MBOX_READ_REGS 16 +#define BMC_MBOX_WRITE_REGS 13 #define MBOX_C_RESET_STATE 0x01 #define MBOX_C_GET_MBOX_INFO 0x02 |
