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authorShreyas B. Prabhu <shreyas@linux.vnet.ibm.com>2014-08-01 10:42:11 +0530
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2014-08-01 16:02:27 +1000
commit025184d5cb8626cd50ac28982d001f92f66a38e2 (patch)
treeb4f7297bc5424f0f2f15587887cbe68a250adc24 /hw
parentdbac1e776bd8cfd928ab0394924a6aca7c681c37 (diff)
downloadblackbird-skiboot-025184d5cb8626cd50ac28982d001f92f66a38e2.tar.gz
blackbird-skiboot-025184d5cb8626cd50ac28982d001f92f66a38e2.zip
slw: Extend opal_slw_set_reg to all supported sprs
Commit 95932150: "slw: patch hsprg0 for wakeup from winkle" added OPAL call for HSPRG0 to be patched via slw. Extend it to all the sprs supported in libpore. Signed-off-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'hw')
-rw-r--r--hw/slw.c43
1 files changed, 26 insertions, 17 deletions
diff --git a/hw/slw.c b/hw/slw.c
index d8d664b9..0af2b436 100644
--- a/hw/slw.c
+++ b/hw/slw.c
@@ -1029,6 +1029,8 @@ static int64_t opal_config_cpu_idle_state(uint64_t state, uint64_t enter)
}
opal_call(OPAL_CONFIG_CPU_IDLE_STATE, opal_config_cpu_idle_state, 2);
+
+#ifdef __HAVE_LIBPORE__
static int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val)
{
@@ -1036,25 +1038,31 @@ static int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val)
struct proc_chip *chip = get_chip(c->chip_id);
void *image = (void *) chip->slw_base;
int rc;
-
- /* Adding HSPRG0, can be extended for other SPRs */
- switch (sprn) {
- case SPR_HSPRG0:
- rc = p8_pore_gen_cpureg_fixed(image, P8_SLW_MODEBUILD_SRAM,
- P8_SPR_HSPRG0, val,
- cpu_get_core_index(c),
- cpu_get_thread_index(c));
-
- if (rc) {
- log_simple_error(&e_info(OPAL_RC_SLW_REG),
- "SLW: Failed to set HSPRG0 for CPU %x\n",
- c->pir);
- return OPAL_INTERNAL_ERROR;
- }
+ int i;
+ int spr_is_supported = 0;
+ /* Check of the SPR is supported by libpore */
+ for ( i=0; i < SLW_SPR_REGS_SIZE ; i++) {
+ if (sprn == SLW_SPR_REGS[i].value) {
+ spr_is_supported = 1;
break;
+ }
+ }
+ if (!spr_is_supported) {
+ log_simple_error(&e_info(OPAL_RC_SLW_REG),
+ "SLW: Trying to set unsupported spr for CPU %x\n",
+ c->pir);
+ return OPAL_UNSUPPORTED;
+ }
+
+ rc = p8_pore_gen_cpureg_fixed(image, P8_SLW_MODEBUILD_SRAM, sprn,
+ val, cpu_get_core_index(c),
+ cpu_get_thread_index(c));
- default:
- return OPAL_UNSUPPORTED;
+ if (rc) {
+ log_simple_error(&e_info(OPAL_RC_SLW_REG),
+ "SLW: Failed to set spr for CPU %x\n",
+ c->pir);
+ return OPAL_INTERNAL_ERROR;
}
return OPAL_SUCCESS;
@@ -1062,3 +1070,4 @@ static int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val)
}
opal_call(OPAL_SLW_SET_REG, opal_slw_set_reg, 3);
+#endif /* __HAVE_LIBPORE__ */
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