summaryrefslogtreecommitdiffstats
path: root/hw
diff options
context:
space:
mode:
authorGavin Shan <gwshan@linux.vnet.ibm.com>2016-04-26 11:56:52 +1000
committerStewart Smith <stewart@linux.vnet.ibm.com>2016-05-03 17:48:46 +1000
commit00f3d2ca92b325db1c7832e4560b564359977202 (patch)
tree86103015f09d73aedfcbf376ece2b0c25884f6d1 /hw
parent98b80af1001027cc59dce040831c1f54d41e4f88 (diff)
downloadblackbird-skiboot-00f3d2ca92b325db1c7832e4560b564359977202.tar.gz
blackbird-skiboot-00f3d2ca92b325db1c7832e4560b564359977202.zip
PCI: Move PHB lock to generic layer
All kinds of PHBs are maintaining a spinlock. At mean while, the spinlock is acquired or released by backends for phb_ops->lock() or phb_ops->unlock(). There're no difference of the logic on all kinds of PHBs. So it's reasonable to maintain the lock in the generic layer (struct phb). This moves lock from specific PHB to generic one. The spinlock is initialized when the generic PHB is registered in pci_register_phb(). Also, two inline functions phb_{lock, unlock}() are introduced to acquire/release it. No logical changes introduced. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'hw')
-rw-r--r--hw/npu-hw-procedures.c1
-rw-r--r--hw/npu.c17
-rw-r--r--hw/p7ioc-phb.c28
-rw-r--r--hw/phb3.c20
4 files changed, 4 insertions, 62 deletions
diff --git a/hw/npu-hw-procedures.c b/hw/npu-hw-procedures.c
index ba87d432..4dbb4baf 100644
--- a/hw/npu-hw-procedures.c
+++ b/hw/npu-hw-procedures.c
@@ -18,7 +18,6 @@
#include <timebase.h>
#include <pci.h>
#include <interrupts.h>
-#include <lock.h>
#include <npu-regs.h>
#include <npu.h>
#include <xscom.h>
diff --git a/hw/npu.c b/hw/npu.c
index a61dd202..1129151c 100644
--- a/hw/npu.c
+++ b/hw/npu.c
@@ -28,7 +28,6 @@
#include <affinity.h>
#include <npu-regs.h>
#include <npu.h>
-#include <lock.h>
#include <xscom.h>
/*
@@ -197,20 +196,6 @@ static uint64_t get_bar_size(uint64_t bar)
return (1 << GETFIELD(NX_MMIO_BAR_SIZE, bar)) * 0x10000;
}
-static void npu_lock(struct phb *phb)
-{
- struct npu *p = phb_to_npu(phb);
-
- lock(&p->lock);
-}
-
-static void npu_unlock(struct phb *phb)
-{
- struct npu *p = phb_to_npu(phb);
-
- unlock(&p->lock);
-}
-
/* Update the changes of the device BAR to link BARs */
static void npu_dev_bar_update(uint32_t gcid, struct npu_dev_bar *bar,
bool enable)
@@ -1102,8 +1087,6 @@ static int64_t npu_err_inject(struct phb *phb, uint32_t pe_num,
}
static const struct phb_ops npu_ops = {
- .lock = npu_lock,
- .unlock = npu_unlock,
.cfg_read8 = npu_dev_cfg_read8,
.cfg_read16 = npu_dev_cfg_read16,
.cfg_read32 = npu_dev_cfg_read32,
diff --git a/hw/p7ioc-phb.c b/hw/p7ioc-phb.c
index 97e4885c..bad7d0a6 100644
--- a/hw/p7ioc-phb.c
+++ b/hw/p7ioc-phb.c
@@ -54,24 +54,6 @@ static inline uint64_t p7ioc_set_sm_timeout(struct p7ioc_phb *p, uint64_t dur)
return dur;
}
-/*
- * Lock callbacks. Allows the OPAL API handlers to lock the
- * PHB around calls such as config space, EEH, etc...
- */
-static void p7ioc_phb_lock(struct phb *phb)
-{
- struct p7ioc_phb *p = phb_to_p7ioc_phb(phb);
-
- lock(&p->lock);
-}
-
-static void p7ioc_phb_unlock(struct phb *phb)
-{
- struct p7ioc_phb *p = phb_to_p7ioc_phb(phb);
-
- unlock(&p->lock);
-}
-
static bool p7ioc_phb_fenced(struct p7ioc_phb *p)
{
struct p7ioc *ioc = p->ioc;
@@ -2569,8 +2551,6 @@ static int64_t p7ioc_papr_errinjct_reset(struct phb *phb)
}
static const struct phb_ops p7ioc_phb_ops = {
- .lock = p7ioc_phb_lock,
- .unlock = p7ioc_phb_unlock,
.cfg_read8 = p7ioc_pcicfg_read8,
.cfg_read16 = p7ioc_pcicfg_read16,
.cfg_read32 = p7ioc_pcicfg_read32,
@@ -2750,11 +2730,11 @@ static void p7ioc_phb_err_interrupt(void *data, uint32_t isn)
* Check if there's an error pending and update PHB fence
* state and return, the ER error is drowned at this point
*/
- lock(&p->lock);
+ phb_lock(&p->phb);
if (p7ioc_phb_fenced(p)) {
p->state = P7IOC_PHB_STATE_FENCED;
PHBERR(p, "ER error ignored, PHB fenced\n");
- unlock(&p->lock);
+ phb_unlock(&p->phb);
return;
}
@@ -2764,7 +2744,7 @@ static void p7ioc_phb_err_interrupt(void *data, uint32_t isn)
* overwriting the errors from IOC.
*/
if (!p7ioc_phb_err_pending(p)) {
- unlock(&p->lock);
+ phb_unlock(&p->phb);
return;
}
@@ -2781,7 +2761,7 @@ static void p7ioc_phb_err_interrupt(void *data, uint32_t isn)
p->err.err_bit = 0;
p7ioc_phb_set_err_pending(p, true);
}
- unlock(&p->lock);
+ phb_unlock(&p->phb);
}
/* MSIs (OS owned) */
diff --git a/hw/phb3.c b/hw/phb3.c
index dbc109b8..ab9d1176 100644
--- a/hw/phb3.c
+++ b/hw/phb3.c
@@ -60,24 +60,6 @@ static void phb3_init_hw(struct phb3 *p, bool first_init);
#define PHBERR(p, fmt, a...) prlog(PR_ERR, "PHB#%04x: " fmt, \
(p)->phb.opal_id, ## a)
-/*
- * Lock callbacks. Allows the OPAL API handlers to lock the
- * PHB around calls such as config space, EEH, etc...
- */
-static void phb3_lock(struct phb *phb)
-{
- struct phb3 *p = phb_to_phb3(phb);
-
- lock(&p->lock);
-}
-
-static void phb3_unlock(struct phb *phb)
-{
- struct phb3 *p = phb_to_phb3(phb);
-
- unlock(&p->lock);
-}
-
/* Helper to select an IODA table entry */
static inline void phb3_ioda_sel(struct phb3 *p, uint32_t table,
uint32_t addr, bool autoinc)
@@ -3591,8 +3573,6 @@ static int64_t phb3_set_capp_recovery(struct phb *phb)
}
static const struct phb_ops phb3_ops = {
- .lock = phb3_lock,
- .unlock = phb3_unlock,
.cfg_read8 = phb3_pcicfg_read8,
.cfg_read16 = phb3_pcicfg_read16,
.cfg_read32 = phb3_pcicfg_read32,
OpenPOWER on IntegriCloud