diff options
| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2017-05-02 11:21:12 +0200 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-05-03 15:50:33 +1000 |
| commit | fa70adcb9d139bd9709681ea138bb2b10a08ff2a (patch) | |
| tree | 9836f8ed4713065bc3643b14527a4056dbb3e254 /hw/xive.c | |
| parent | 4f930a016f791db2d46c37c2946eac8d2966aee0 (diff) | |
| download | blackbird-skiboot-fa70adcb9d139bd9709681ea138bb2b10a08ff2a.tar.gz blackbird-skiboot-fa70adcb9d139bd9709681ea138bb2b10a08ff2a.zip | |
xive: Workaround a problem with indirect TM access
A HW issue can cause accesses to the content of the indirect data
area to pass the actual selection of the target thread. The
workaround is to read the PC_TCTXT_INDIR0 register back before
accessing the data area.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'hw/xive.c')
| -rw-r--r-- | hw/xive.c | 10 |
1 files changed, 10 insertions, 0 deletions
@@ -3935,6 +3935,11 @@ static void xive_cleanup_cpu_tma(struct cpu_thread *c) PC_TCTXT_INDIR_VALID | SETFIELD(PC_TCTXT_INDIR_THRDID, 0ull, c->pir & 0xff)); + /* Workaround for HW issue: Need to read the above register + * back before doing the subsequent accesses + */ + xive_regr(x, PC_TCTXT_INDIR0); + /* Pull user context, OS context and Pool context if any */ in_be32(ind_tm_base + TM_SPC_PULL_USR_CTX); in_be32(ind_tm_base + TM_SPC_PULL_OS_CTX); @@ -4393,6 +4398,11 @@ static int64_t opal_xive_dump_tm(uint32_t offset, const char *n, uint32_t pir) PC_TCTXT_INDIR_VALID | SETFIELD(PC_TCTXT_INDIR_THRDID, 0ull, pir & 0xff)); + /* Workaround for HW issue: Need to read the above register + * back before doing the subsequent accesses + */ + xive_regr(x, PC_TCTXT_INDIR0); + v0 = in_be64(ind_tm_base + offset); v1 = in_be64(ind_tm_base + offset + 8); prlog(PR_INFO, "CPU[%04x]: TM state for QW %s\n", pir, n); |
