NX: Add P9 NX support for 842 compression engine

This patch adds changes needed for 842 compression engine on power 9.
Virtual Accelerator Switch (VAS) is used to access NX 842 engine on P9
and the channel setup will be done with receive FIFO. So RxFIFO
address, logical partition ID (lpid), process ID (pid) and thread ID
(tid) are used for this setup. p9 NX supports high and normal priority
FIFOs. skiboot is not involved to process data with 842 engine, but
configures User Mode Access Control (UMAC) noitify match register with
these values and export them to kernel with device-tree entries.

Also configure registers to setup and enable / disable the engine with
the appropriate registers. Creates the following device-tree entries to
provide RxFIFO address, RxFIFO size, Fifo priority, lpid, pid and tid
values so that kernel can drive P9 NX 842 engine.

The following nodes are located under an xscom node:
/xscom@<xscom_addr>/nx@<nx_addr>

   /ibm,842-high-fifo	: High priority 842 RxFIFO
   /ibm,842-normal-fifo	: Normal priority 842 RxFIFO

Each RxFIFO node contains:
   compatible		: ibm,p9-nx-842
   priority		: High or Normal
   rx-fifo-address	: RxFIFO address
   rx-fifo-size		: RXFIFO size
   lpid			: 0xfff (1's for 12 bits set in UMAC notify
					match register)
   pid			: 842 coprocessor type
   tid			: Counter for 842

Signed-off-by: Haren Myneni <haren@us.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>

1 files changed, 58 insertions, 5 deletions

diff --git a/hw/nx-842.c b/hw/nx-842.c
index 031de038..21bc2fd2 100644
--- a/hw/nx-842.c
+++ b/hw/nx-842.c
@@ -20,6 +20,7 @@
 #include <io.h>
 #include <cpu.h>
 #include <nx.h>
+#include <vas.h>
 
 /* Configuration settings */
 #define CFG_842_FC_ENABLE	(0x1f) /* enable all 842 functions */
@@ -85,6 +86,32 @@ static int nx_cfg_842(u32 gcid, u64 xcfg)
 	return rc;
 }
 
+static int nx_cfg_842_umac(struct dt_node *node, u32 gcid, u32 pb_base)
+{
+	int rc;
+	u64 umac_bar, umac_notify;
+	struct dt_node *nx_node;
+	static u32 nx842_tid = 1; /* tid counter within coprocessor type */
+
+	nx_node = dt_new(node, "ibm,842-high-fifo");
+	umac_bar = pb_base + NX_P9_842_HIGH_PRI_RX_FIFO_BAR;
+	umac_notify = pb_base + NX_P9_842_HIGH_PRI_RX_FIFO_NOTIFY_MATCH;
+	rc = nx_cfg_rx_fifo(nx_node, "ibm,p9-nx-842", "High", gcid,
+				NX_CT_842, nx842_tid++, umac_bar,
+				umac_notify);
+	if (rc)
+		return rc;
+
+	nx_node = dt_new(node, "ibm,842-normal-fifo");
+	umac_bar = pb_base + NX_P9_842_NORMAL_PRI_RX_FIFO_BAR;
+	umac_notify = pb_base + NX_P9_842_NORMAL_PRI_RX_FIFO_NOTIFY_MATCH;
+	rc = nx_cfg_rx_fifo(nx_node, "ibm,p9-nx-842", "Normal", gcid,
+				NX_CT_842, nx842_tid++, umac_bar,
+				umac_notify);
+
+	return rc;
+}
+
 static int nx_cfg_842_dma(u32 gcid, u64 xcfg)
 {
 	u64 cfg;
@@ -94,7 +121,7 @@ static int nx_cfg_842_dma(u32 gcid, u64 xcfg)
 	if (rc)
 		return rc;
 
-	if (proc_gen == proc_gen_p8) {
+	if (proc_gen >= proc_gen_p8) {
 		cfg = SETFIELD(NX_DMA_CFG_842_COMPRESS_PREFETCH, cfg,
 			       DMA_COMPRESS_PREFETCH);
 		cfg = SETFIELD(NX_DMA_CFG_842_DECOMPRESS_PREFETCH, cfg,
@@ -107,14 +134,16 @@ static int nx_cfg_842_dma(u32 gcid, u64 xcfg)
 		       DMA_DECOMPRESS_MAX_RR);
 	cfg = SETFIELD(NX_DMA_CFG_842_SPBC, cfg,
 		       DMA_SPBC);
-	cfg = SETFIELD(NX_DMA_CFG_842_CSB_WR, cfg,
+	if (proc_gen < proc_gen_p9) {
+		cfg = SETFIELD(NX_DMA_CFG_842_CSB_WR, cfg,
 		       DMA_CSB_WR);
-	cfg = SETFIELD(NX_DMA_CFG_842_COMPLETION_MODE, cfg,
+		cfg = SETFIELD(NX_DMA_CFG_842_COMPLETION_MODE, cfg,
 		       DMA_COMPLETION_MODE);
-	cfg = SETFIELD(NX_DMA_CFG_842_CPB_WR, cfg,
+		cfg = SETFIELD(NX_DMA_CFG_842_CPB_WR, cfg,
 		       DMA_CPB_WR);
-	cfg = SETFIELD(NX_DMA_CFG_842_OUTPUT_DATA_WR, cfg,
+		cfg = SETFIELD(NX_DMA_CFG_842_OUTPUT_DATA_WR, cfg,
 		       DMA_OUTPUT_DATA_WR);
+	}
 
 	rc = xscom_write(gcid, xcfg, cfg);
 	if (rc)
@@ -183,3 +212,27 @@ void nx_enable_842(struct dt_node *node, u32 gcid, u32 pb_base)
 	dt_add_property_cells(node, "ibm,842-coprocessor-type", NX_CT_842);
 	dt_add_property_cells(node, "ibm,842-coprocessor-instance", gcid + 1);
 }
+
+void p9_nx_enable_842(struct dt_node *node, u32 gcid, u32 pb_base)
+{
+	u64 cfg_dma, cfg_ee;
+	int rc;
+
+	cfg_dma = pb_base + NX_P9_DMA_CFG;
+	cfg_ee = pb_base + NX_P9_EE_CFG;
+
+	rc = nx_cfg_842_dma(gcid, cfg_dma);
+	if (rc)
+		return;
+
+	rc = nx_cfg_842_umac(node, gcid, pb_base);
+	if (rc)
+		return;
+
+	rc = nx_cfg_842_ee(gcid, cfg_ee);
+	if (rc)
+		return;
+
+	prlog(PR_INFO, "NX%d: 842 Coprocessor Enabled\n", gcid);
+
+}