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| author | Oliver O'Halloran <oohall@gmail.com> | 2019-03-20 19:56:56 +1100 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.ibm.com> | 2019-03-28 15:24:13 +1100 |
| commit | 722cf1c2ed56907fd9cc64c3f406f998d7e44992 (patch) | |
| tree | 2e4e9ab3951130512927d32eb5b05aa4fa09c65a | |
| parent | b8b4c79d44191c09d75ffe6204ab9ce1191491d4 (diff) | |
| download | blackbird-skiboot-722cf1c2ed56907fd9cc64c3f406f998d7e44992.tar.gz blackbird-skiboot-722cf1c2ed56907fd9cc64c3f406f998d7e44992.zip | |
hw/phb4: Drop FRESET_DEASSERT_DELAY state
The delay between the ASSERT_DELAY and DEASSERT_DELAY states is set to
one timebase tick. This state seems to have been a hold over from PHB3
where it was used to add a 1s delay between de-asserting PERST and
polling the link for the CAPI FPGA. There's no requirement for that here
since the link polling on PHB4 is a bit smarter so we should be fine.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
| -rw-r--r-- | hw/phb4.c | 5 | ||||
| -rw-r--r-- | include/phb4.h | 1 |
2 files changed, 0 insertions, 6 deletions
@@ -2999,11 +2999,6 @@ static int64_t phb4_freset(struct pci_slot *slot) PHBDBG(p, "FRESET: Deassert\n"); phb4_assert_perst(slot, false); - pci_slot_set_state(slot, PHB4_SLOT_FRESET_DEASSERT_DELAY); - return pci_slot_set_sm_timeout(slot, msecs_to_tb(1)); - - case PHB4_SLOT_FRESET_DEASSERT_DELAY: - PHBDBG(p, "FRESET: Starting training\n"); phb4_training_trace(p); diff --git a/include/phb4.h b/include/phb4.h index 605effec..c52a840d 100644 --- a/include/phb4.h +++ b/include/phb4.h @@ -125,7 +125,6 @@ #define PHB4_SLOT_FRESET PCI_SLOT_STATE_FRESET #define PHB4_SLOT_FRESET_START (PHB4_SLOT_FRESET + 1) #define PHB4_SLOT_FRESET_ASSERT_DELAY (PHB4_SLOT_FRESET + 2) -#define PHB4_SLOT_FRESET_DEASSERT_DELAY (PHB4_SLOT_FRESET + 3) #define PHB4_SLOT_CRESET PCI_SLOT_STATE_CRESET #define PHB4_SLOT_CRESET_START (PHB4_SLOT_CRESET + 1) #define PHB4_SLOT_CRESET_WAIT_CQ (PHB4_SLOT_CRESET + 2) |
