blob: 0ad5ef930b5d64d54db112bafdd80d39a49faa46 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
|
/*
* Copyright (c) 2014, The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _DT_BINDINGS_RESET_IPQ_806X_H
#define _DT_BINDINGS_RESET_IPQ_806X_H
#define QDSS_STM_RESET 0
#define AFAB_SMPSS_S_RESET 1
#define AFAB_SMPSS_M1_RESET 2
#define AFAB_SMPSS_M0_RESET 3
#define AFAB_EBI1_CH0_RESET 4
#define AFAB_EBI1_CH1_RESET 5
#define SFAB_ADM0_M0_RESET 6
#define SFAB_ADM0_M1_RESET 7
#define SFAB_ADM0_M2_RESET 8
#define ADM0_C2_RESET 9
#define ADM0_C1_RESET 10
#define ADM0_C0_RESET 11
#define ADM0_PBUS_RESET 12
#define ADM0_RESET 13
#define QDSS_CLKS_SW_RESET 14
#define QDSS_POR_RESET 15
#define QDSS_TSCTR_RESET 16
#define QDSS_HRESET_RESET 17
#define QDSS_AXI_RESET 18
#define QDSS_DBG_RESET 19
#define SFAB_PCIE_M_RESET 20
#define SFAB_PCIE_S_RESET 21
#define PCIE_EXT_RESET 22
#define PCIE_PHY_RESET 23
#define PCIE_PCI_RESET 24
#define PCIE_POR_RESET 25
#define PCIE_HCLK_RESET 26
#define PCIE_ACLK_RESET 27
#define SFAB_LPASS_RESET 28
#define SFAB_AFAB_M_RESET 29
#define AFAB_SFAB_M0_RESET 30
#define AFAB_SFAB_M1_RESET 31
#define SFAB_SATA_S_RESET 32
#define SFAB_DFAB_M_RESET 33
#define DFAB_SFAB_M_RESET 34
#define DFAB_SWAY0_RESET 35
#define DFAB_SWAY1_RESET 36
#define DFAB_ARB0_RESET 37
#define DFAB_ARB1_RESET 38
#define PPSS_PROC_RESET 39
#define PPSS_RESET 40
#define DMA_BAM_RESET 41
#define SPS_TIC_H_RESET 42
#define SFAB_CFPB_M_RESET 43
#define SFAB_CFPB_S_RESET 44
#define TSIF_H_RESET 45
#define CE1_H_RESET 46
#define CE1_CORE_RESET 47
#define CE1_SLEEP_RESET 48
#define CE2_H_RESET 49
#define CE2_CORE_RESET 50
#define SFAB_SFPB_M_RESET 51
#define SFAB_SFPB_S_RESET 52
#define RPM_PROC_RESET 53
#define PMIC_SSBI2_RESET 54
#define SDC1_RESET 55
#define SDC2_RESET 56
#define SDC3_RESET 57
#define SDC4_RESET 58
#define USB_HS1_RESET 59
#define USB_HSIC_RESET 60
#define USB_FS1_XCVR_RESET 61
#define USB_FS1_RESET 62
#define GSBI1_RESET 63
#define GSBI2_RESET 64
#define GSBI3_RESET 65
#define GSBI4_RESET 66
#define GSBI5_RESET 67
#define GSBI6_RESET 68
#define GSBI7_RESET 69
#define SPDM_RESET 70
#define SEC_CTRL_RESET 71
#define TLMM_H_RESET 72
#define SFAB_SATA_M_RESET 73
#define SATA_RESET 74
#define TSSC_RESET 75
#define PDM_RESET 76
#define MPM_H_RESET 77
#define MPM_RESET 78
#define SFAB_SMPSS_S_RESET 79
#define PRNG_RESET 80
#define SFAB_CE3_M_RESET 81
#define SFAB_CE3_S_RESET 82
#define CE3_SLEEP_RESET 83
#define PCIE_1_M_RESET 84
#define PCIE_1_S_RESET 85
#define PCIE_1_EXT_RESET 86
#define PCIE_1_PHY_RESET 87
#define PCIE_1_PCI_RESET 88
#define PCIE_1_POR_RESET 89
#define PCIE_1_HCLK_RESET 90
#define PCIE_1_ACLK_RESET 91
#define PCIE_2_M_RESET 92
#define PCIE_2_S_RESET 93
#define PCIE_2_EXT_RESET 94
#define PCIE_2_PHY_RESET 95
#define PCIE_2_PCI_RESET 96
#define PCIE_2_POR_RESET 97
#define PCIE_2_HCLK_RESET 98
#define PCIE_2_ACLK_RESET 99
#define SFAB_USB30_S_RESET 100
#define SFAB_USB30_M_RESET 101
#define USB30_0_PORT2_HS_PHY_RESET 102
#define USB30_0_MASTER_RESET 103
#define USB30_0_SLEEP_RESET 104
#define USB30_0_UTMI_PHY_RESET 105
#define USB30_0_POWERON_RESET 106
#define USB30_0_PHY_RESET 107
#define USB30_1_MASTER_RESET 108
#define USB30_1_SLEEP_RESET 109
#define USB30_1_UTMI_PHY_RESET 110
#define USB30_1_POWERON_RESET 111
#define USB30_1_PHY_RESET 112
#define NSSFB0_RESET 113
#define NSSFB1_RESET 114
#endif
|
