summaryrefslogtreecommitdiffstats
path: root/drivers/clocksource/timer-nps.c
blob: 8da5e93b681041f6e1a26585f614b7c6b3b71a5c (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
/*
 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#include <linux/interrupt.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/cpu.h>
#include <soc/nps/common.h>

#define NPS_MSU_TICK_LOW	0xC8
#define NPS_CLUSTER_OFFSET	8
#define NPS_CLUSTER_NUM		16

/* This array is per cluster of CPUs (Each NPS400 cluster got 256 CPUs) */
static void *nps_msu_reg_low_addr[NPS_CLUSTER_NUM] __read_mostly;

static int __init nps_get_timer_clk(struct device_node *node,
			     unsigned long *timer_freq,
			     struct clk **clk)
{
	int ret;

	*clk = of_clk_get(node, 0);
	ret = PTR_ERR_OR_ZERO(*clk);
	if (ret) {
		pr_err("timer missing clk");
		return ret;
	}

	ret = clk_prepare_enable(*clk);
	if (ret) {
		pr_err("Couldn't enable parent clk\n");
		clk_put(*clk);
		return ret;
	}

	*timer_freq = clk_get_rate(*clk);
	if (!(*timer_freq)) {
		pr_err("Couldn't get clk rate\n");
		clk_disable_unprepare(*clk);
		clk_put(*clk);
		return -EINVAL;
	}

	return 0;
}

static cycle_t nps_clksrc_read(struct clocksource *clksrc)
{
	int cluster = raw_smp_processor_id() >> NPS_CLUSTER_OFFSET;

	return (cycle_t)ioread32be(nps_msu_reg_low_addr[cluster]);
}

static int __init nps_setup_clocksource(struct device_node *node)
{
	int ret, cluster;
	struct clk *clk;
	unsigned long nps_timer1_freq;


	for (cluster = 0; cluster < NPS_CLUSTER_NUM; cluster++)
		nps_msu_reg_low_addr[cluster] =
			nps_host_reg((cluster << NPS_CLUSTER_OFFSET),
				     NPS_MSU_BLKID, NPS_MSU_TICK_LOW);

	ret = nps_get_timer_clk(node, &nps_timer1_freq, &clk);
	if (ret)
		return ret;

	ret = clocksource_mmio_init(nps_msu_reg_low_addr, "nps-tick",
				    nps_timer1_freq, 300, 32, nps_clksrc_read);
	if (ret) {
		pr_err("Couldn't register clock source.\n");
		clk_disable_unprepare(clk);
	}

	return ret;
}

CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clksrc, "ezchip,nps400-timer",
		       nps_setup_clocksource);
CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clk_src, "ezchip,nps400-timer1",
		       nps_setup_clocksource);

#ifdef CONFIG_EZNPS_MTM_EXT
#include <soc/nps/mtm.h>

/* Timer related Aux registers */
#define NPS_REG_TIMER0_TSI	0xFFFFF850
#define NPS_REG_TIMER0_LIMIT	0x23
#define NPS_REG_TIMER0_CTRL	0x22
#define NPS_REG_TIMER0_CNT	0x21

/*
 * Interrupt Enabled (IE) - re-arm the timer
 * Not Halted (NH) - is cleared when working with JTAG (for debug)
 */
#define TIMER0_CTRL_IE		BIT(0)
#define TIMER0_CTRL_NH		BIT(1)

static unsigned long nps_timer0_freq;
static unsigned long nps_timer0_irq;

static void nps_clkevent_rm_thread(void)
{
	int thread;
	unsigned int cflags, enabled_threads;

	hw_schd_save(&cflags);

	enabled_threads = read_aux_reg(NPS_REG_TIMER0_TSI);

	/* remove thread from TSI1 */
	thread = read_aux_reg(CTOP_AUX_THREAD_ID);
	enabled_threads &= ~(1 << thread);
	write_aux_reg(NPS_REG_TIMER0_TSI, enabled_threads);

	/* Acknowledge and if needed re-arm the timer */
	if (!enabled_threads)
		write_aux_reg(NPS_REG_TIMER0_CTRL, TIMER0_CTRL_NH);
	else
		write_aux_reg(NPS_REG_TIMER0_CTRL,
			      TIMER0_CTRL_IE | TIMER0_CTRL_NH);

	hw_schd_restore(cflags);
}

static void nps_clkevent_add_thread(unsigned long delta)
{
	int thread;
	unsigned int cflags, enabled_threads;

	hw_schd_save(&cflags);

	/* add thread to TSI1 */
	thread = read_aux_reg(CTOP_AUX_THREAD_ID);
	enabled_threads = read_aux_reg(NPS_REG_TIMER0_TSI);
	enabled_threads |= (1 << thread);
	write_aux_reg(NPS_REG_TIMER0_TSI, enabled_threads);

	/* set next timer event */
	write_aux_reg(NPS_REG_TIMER0_LIMIT, delta);
	write_aux_reg(NPS_REG_TIMER0_CNT, 0);
	write_aux_reg(NPS_REG_TIMER0_CTRL,
		      TIMER0_CTRL_IE | TIMER0_CTRL_NH);

	hw_schd_restore(cflags);
}

/*
 * Whenever anyone tries to change modes, we just mask interrupts
 * and wait for the next event to get set.
 */
static int nps_clkevent_set_state(struct clock_event_device *dev)
{
	nps_clkevent_rm_thread();
	disable_percpu_irq(nps_timer0_irq);

	return 0;
}

static int nps_clkevent_set_next_event(unsigned long delta,
				       struct clock_event_device *dev)
{
	nps_clkevent_add_thread(delta);
	enable_percpu_irq(nps_timer0_irq, IRQ_TYPE_NONE);

	return 0;
}

static DEFINE_PER_CPU(struct clock_event_device, nps_clockevent_device) = {
	.name				=	"NPS Timer0",
	.features			=	CLOCK_EVT_FEAT_ONESHOT,
	.rating				=	300,
	.set_next_event			=	nps_clkevent_set_next_event,
	.set_state_oneshot		=	nps_clkevent_set_state,
	.set_state_oneshot_stopped	=	nps_clkevent_set_state,
	.set_state_shutdown		=	nps_clkevent_set_state,
	.tick_resume			=	nps_clkevent_set_state,
};

static irqreturn_t timer_irq_handler(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	nps_clkevent_rm_thread();
	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static int nps_timer_starting_cpu(unsigned int cpu)
{
	struct clock_event_device *evt = this_cpu_ptr(&nps_clockevent_device);

	evt->cpumask = cpumask_of(smp_processor_id());

	clockevents_config_and_register(evt, nps_timer0_freq, 0, ULONG_MAX);
	enable_percpu_irq(nps_timer0_irq, IRQ_TYPE_NONE);

	return 0;
}

static int nps_timer_dying_cpu(unsigned int cpu)
{
	disable_percpu_irq(nps_timer0_irq);
	return 0;
}

static int __init nps_setup_clockevent(struct device_node *node)
{
	struct clk *clk;
	int ret;

	nps_timer0_irq = irq_of_parse_and_map(node, 0);
	if (nps_timer0_irq <= 0) {
		pr_err("clockevent: missing irq");
		return -EINVAL;
	}

	ret = nps_get_timer_clk(node, &nps_timer0_freq, &clk);
	if (ret)
		return ret;

	/* Needs apriori irq_set_percpu_devid() done in intc map function */
	ret = request_percpu_irq(nps_timer0_irq, timer_irq_handler,
				 "Timer0 (per-cpu-tick)",
				 &nps_clockevent_device);
	if (ret) {
		pr_err("Couldn't request irq\n");
		clk_disable_unprepare(clk);
		return ret;
	}

	ret = cpuhp_setup_state(CPUHP_AP_ARC_TIMER_STARTING,
				"clockevents/nps:starting",
				nps_timer_starting_cpu,
				nps_timer_dying_cpu);
	if (ret) {
		pr_err("Failed to setup hotplug state");
		clk_disable_unprepare(clk);
		free_percpu_irq(nps_timer0_irq, &nps_clockevent_device);
		return ret;
	}

	return 0;
}

CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clk_evt, "ezchip,nps400-timer0",
		       nps_setup_clockevent);
#endif /* CONFIG_EZNPS_MTM_EXT */
OpenPOWER on IntegriCloud