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/*
* Spreadtrum Whale2 platform peripherals
*
* Copyright (C) 2016, Spreadtrum Communications Inc.
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
#include <dt-bindings/clock/sprd,sc9860-clk.h>
/ {
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
soc: soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
ap_ahb_regs: syscon@20210000 {
compatible = "syscon";
reg = <0 0x20210000 0 0x10000>;
};
pmu_regs: syscon@402b0000 {
compatible = "syscon";
reg = <0 0x402b0000 0 0x10000>;
};
aon_regs: syscon@402e0000 {
compatible = "syscon";
reg = <0 0x402e0000 0 0x10000>;
};
ana_regs: syscon@40400000 {
compatible = "syscon";
reg = <0 0x40400000 0 0x10000>;
};
agcp_regs: syscon@415e0000 {
compatible = "syscon";
reg = <0 0x415e0000 0 0x1000000>;
};
vsp_regs: syscon@61100000 {
compatible = "syscon";
reg = <0 0x61100000 0 0x10000>;
};
cam_regs: syscon@62100000 {
compatible = "syscon";
reg = <0 0x62100000 0 0x10000>;
};
disp_regs: syscon@63100000 {
compatible = "syscon";
reg = <0 0x63100000 0 0x10000>;
};
ap_apb_regs: syscon@70b00000 {
compatible = "syscon";
reg = <0 0x70b00000 0 0x40000>;
};
ap-apb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0x70000000 0x10000000>;
uart0: serial@0 {
compatible = "sprd,sc9860-uart",
"sprd,sc9836-uart";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ext_26m>;
status = "disabled";
};
uart1: serial@100000 {
compatible = "sprd,sc9860-uart",
"sprd,sc9836-uart";
reg = <0x100000 0x100>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ext_26m>;
status = "disabled";
};
uart2: serial@200000 {
compatible = "sprd,sc9860-uart",
"sprd,sc9836-uart";
reg = <0x200000 0x100>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ext_26m>;
status = "disabled";
};
uart3: serial@300000 {
compatible = "sprd,sc9860-uart",
"sprd,sc9836-uart";
reg = <0x300000 0x100>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ext_26m>;
status = "disabled";
};
};
ap-ahb {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
ap_dma: dma-controller@20100000 {
compatible = "sprd,sc9860-dma";
reg = <0 0x20100000 0 0x4000>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
#dma-channels = <32>;
clock-names = "enable";
clocks = <&apahb_gate CLK_DMA_EB>;
};
};
aon {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
adi_bus: spi@40030000 {
compatible = "sprd,sc9860-adi";
reg = <0 0x40030000 0 0x10000>;
hwlocks = <&hwlock 0>;
hwlock-names = "adi";
#address-cells = <1>;
#size-cells = <0>;
};
timer@40050000 {
compatible = "sprd,sc9860-timer";
reg = <0 0x40050000 0 0x20>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ext_32k>;
};
hwlock: hwspinlock@40500000 {
compatible = "sprd,hwspinlock-r3p0";
reg = <0 0x40500000 0 0x1000>;
#hwlock-cells = <1>;
clock-names = "enable";
clocks = <&aon_gate CLK_SPLK_EB>;
};
pin_controller: pinctrl@402a0000 {
compatible = "sprd,sc9860-pinctrl";
reg = <0 0x402a0000 0 0x10000>;
};
watchdog@40310000 {
compatible = "sprd,sp9860-wdt";
reg = <0 0x40310000 0 0x1000>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
timeout-sec = <12>;
clock-names = "enable";
clocks = <&aon_gate CLK_APCPU_WDG_EB>;
};
};
agcp {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
agcp_dma: dma-controller@41580000 {
compatible = "sprd,sc9860-dma";
reg = <0 0x41580000 0 0x4000>;
#dma-cells = <1>;
#dma-channels = <32>;
clock-names = "enable", "ashb_eb";
clocks = <&agcp_gate CLK_AGCP_DMAAP_EB>,
<&agcp_gate CLK_AGCP_AP_ASHB_EB>;
};
};
};
ext_32k: ext_32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "ext-32k";
};
ext_26m: ext_26m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
clock-output-names = "ext-26m";
};
ext_rco_100m: ext_rco_100m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "ext-rco-100m";
};
};
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