blob: 7ed88ee629fb78b559d5bbb312f586490f35d31f (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "sigma,tango4-smp";
cpu0: cpu@0 {
compatible = "arm,cortex-a9";
next-level-cache = <&l2cc>;
device_type = "cpu";
reg = <0>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a9";
next-level-cache = <&l2cc>;
device_type = "cpu";
reg = <1>;
};
};
pmu {
compatible = "arm,cortex-a9-pmu";
interrupt-affinity = <&cpu0>, <&cpu1>;
interrupts =
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
};
};
|
