1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
|
// SPDX-License-Identifier: GPL-2.0
/*
* Device tree for Energy Micro EFM32 Giant Gecko SoC.
*
* Documentation available from
* http://www.silabs.com/Support%20Documents/TechnicalDocs/EFM32GG-RM.pdf
*/
#include "armv7-m.dtsi"
#include "dt-bindings/clock/efm32-cmu.h"
/ {
#address-cells = <1>;
#size-cells = <1>;
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
spi0 = &spi0;
spi1 = &spi1;
spi2 = &spi2;
};
soc {
adc: adc@40002000 {
compatible = "energymicro,efm32-adc";
reg = <0x40002000 0x400>;
interrupts = <7>;
clocks = <&cmu clk_HFPERCLKADC0>;
status = "disabled";
};
gpio: gpio@40006000 {
compatible = "energymicro,efm32-gpio";
reg = <0x40006000 0x1000>;
interrupts = <1 11>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
clocks = <&cmu clk_HFPERCLKGPIO>;
status = "ok";
};
i2c0: i2c@4000a000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "energymicro,efm32-i2c";
reg = <0x4000a000 0x400>;
interrupts = <9>;
clocks = <&cmu clk_HFPERCLKI2C0>;
clock-frequency = <100000>;
status = "disabled";
};
i2c1: i2c@4000a400 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "energymicro,efm32-i2c";
reg = <0x4000a400 0x400>;
interrupts = <10>;
clocks = <&cmu clk_HFPERCLKI2C1>;
clock-frequency = <100000>;
status = "disabled";
};
spi0: spi@4000c000 { /* USART0 */
#address-cells = <1>;
#size-cells = <0>;
compatible = "energymicro,efm32-spi";
reg = <0x4000c000 0x400>;
interrupts = <3 4>;
clocks = <&cmu clk_HFPERCLKUSART0>;
status = "disabled";
};
spi1: spi@4000c400 { /* USART1 */
#address-cells = <1>;
#size-cells = <0>;
compatible = "energymicro,efm32-spi";
reg = <0x4000c400 0x400>;
interrupts = <15 16>;
clocks = <&cmu clk_HFPERCLKUSART1>;
status = "disabled";
};
spi2: spi@4000c800 { /* USART2 */
#address-cells = <1>;
#size-cells = <0>;
compatible = "energymicro,efm32-spi";
reg = <0x4000c800 0x400>;
interrupts = <18 19>;
clocks = <&cmu clk_HFPERCLKUSART2>;
status = "disabled";
};
uart0: uart@4000c000 { /* USART0 */
compatible = "energymicro,efm32-uart";
reg = <0x4000c000 0x400>;
interrupts = <3 4>;
clocks = <&cmu clk_HFPERCLKUSART0>;
status = "disabled";
};
uart1: uart@4000c400 { /* USART1 */
compatible = "energymicro,efm32-uart";
reg = <0x4000c400 0x400>;
interrupts = <15 16>;
clocks = <&cmu clk_HFPERCLKUSART1>;
status = "disabled";
};
uart2: uart@4000c800 { /* USART2 */
compatible = "energymicro,efm32-uart";
reg = <0x4000c800 0x400>;
interrupts = <18 19>;
clocks = <&cmu clk_HFPERCLKUSART2>;
status = "disabled";
};
uart3: uart@4000e000 { /* UART0 */
compatible = "energymicro,efm32-uart";
reg = <0x4000e000 0x400>;
interrupts = <20 21>;
clocks = <&cmu clk_HFPERCLKUART0>;
status = "disabled";
};
uart4: uart@4000e400 { /* UART1 */
compatible = "energymicro,efm32-uart";
reg = <0x4000e400 0x400>;
interrupts = <22 23>;
clocks = <&cmu clk_HFPERCLKUART1>;
status = "disabled";
};
timer0: timer@40010000 {
compatible = "energymicro,efm32-timer";
reg = <0x40010000 0x400>;
interrupts = <2>;
clocks = <&cmu clk_HFPERCLKTIMER0>;
};
timer1: timer@40010400 {
compatible = "energymicro,efm32-timer";
reg = <0x40010400 0x400>;
interrupts = <12>;
clocks = <&cmu clk_HFPERCLKTIMER1>;
};
timer2: timer@40010800 {
compatible = "energymicro,efm32-timer";
reg = <0x40010800 0x400>;
interrupts = <13>;
clocks = <&cmu clk_HFPERCLKTIMER2>;
};
timer3: timer@40010c00 {
compatible = "energymicro,efm32-timer";
reg = <0x40010c00 0x400>;
interrupts = <14>;
clocks = <&cmu clk_HFPERCLKTIMER3>;
};
cmu: cmu@400c8000 {
compatible = "efm32gg,cmu";
reg = <0x400c8000 0x400>;
interrupts = <32>;
#clock-cells = <1>;
};
};
};
|
