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/*
* Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/ {
compatible = "snps,arc";
clock-frequency = <80000000>; /* 80 MHZ */
#address-cells = <1>;
#size-cells = <1>;
chosen { };
aliases { };
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "snps,archs38xN";
reg = <0>;
};
};
/* TIMER0 with interrupt for clockevent */
timer0 {
compatible = "snps,arc-timer";
interrupts = <16>;
interrupt-parent = <&core_intc>;
clocks = <&core_clk>;
};
/* 64-bit Global Free Running Counter */
gfrc {
compatible = "snps,archs-timer-gfrc";
clocks = <&core_clk>;
};
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256M */
};
};
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