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path: root/include/uapi/drm/amdgpu_drm.h
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* drm/amdgpu: Add DMCUB to firmware query interfaceNicholas Kazlauskas2019-11-131-0/+3
| | | | | | | | | | The DMCUB firmware version can be read using the AMDGPU_INFO ioctl or the amdgpu_firmware_info debugfs entry. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: return tcc_disabled_mask to userspaceMarek Olšák2019-10-031-0/+2
| | | | | | | | UMDs need this for correct programming of harvested chips. Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Extends amdgpu vm definitions (v2)Oak Zeng2019-09-131-0/+2
| | | | | | | | | | | | | | Add RW mtype introduced for arcturus. v2: * Don't add probe-invalidation bit from UAPI * Don't add unused AMDGPU_MTYPE_ definitions Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Add flag to wipe VRAM on releaseFelix Kuehling2019-08-021-0/+4
| | | | | | | | | This memory allocation flag will be used to indicate BOs containing sensitive data that should not be leaked to other processes. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: extend AMDGPU_CTX_PRIORITY_NORMAL commentEmil Velikov2019-07-161-1/+6
| | | | | | | | | | | | | | | Currently the AMDGPU_CTX_PRIORITY_* defines are used in both drm_amdgpu_ctx_in::priority and drm_amdgpu_sched_in::priority. Extend the comment to mention the CAP_SYS_NICE or DRM_MASTER requirement is only applicable with the former. Cc: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add pa_sc_tile_steering_override to drm_amdgpu_info_deviceHawking Zhang2019-06-211-0/+2
| | | | | | | | | the initial/default value of pa_sc_tile_steering_override need to be exposed to user mode driver Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add GDDR6 vram typeHuang Rui2019-06-201-0/+1
| | | | | | | | | New vram type. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add NV series gpu family idHuang Rui2019-06-201-0/+1
| | | | | | | Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add timeline support in amdgpu CS v3Chunming Zhou2019-04-121-0/+8
| | | | | | | | | | | | | | | syncobj wait/signal operation is appending in command submission. v2: separate to two kinds in/out_deps functions v3: fix checking for timeline syncobj Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Cc: Tobias Hector <Tobias.Hector@amd.com> Cc: Jason Ekstrand <jason@jlekstrand.net> Cc: Dave Airlie <airlied@redhat.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add ioctl query for enabled ras features (v2)xinhui pan2019-03-191-0/+31
| | | | | | | | | | | Add a query for userspace to check which RAS features are enabled. v2: squash in warning fix Signed-off-by: xinhui pan <xinhui.pan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Add a new flag to AMDGPU_CTX_OP_QUERY_STATE2xinhui pan2019-03-191-0/+3
| | | | | | | | | Add AMDGPU_CTX_QUERY2_FLAGS_RAS_CE/UE which indicate if any error happened between previous query and this query. Signed-off-by: xinhui pan <xinhui.pan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: export ta fw infoxinhui pan2019-03-191-0/+1
| | | | | | | | Output the ta fw, aka xgmi/ras, via debugfs. Signed-off-by: xinhui pan <xinhui.pan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Add command to override the context priority.Bas Nieuwenhuizen2019-02-151-1/+2
| | | | | | | | | | | | | | | | | | Given a master fd we can then override the priority of the context in another fd. Using these overrides was recommended by Christian instead of trying to submit from a master fd, and I am adding a way to override a single context instead of the entire process so we can only upgrade a single Vulkan queue and not effectively the entire process. Reused the flags field as it was checked to be 0 anyways, so nothing used it. This is source-incompatible (due to the name change), but ABI compatible. Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add a workaround for GDS ordered append hangs with compute queuesMarek Olšák2019-02-051-0/+5
| | | | | | | | | | | I'm not increasing the DRM version because GDS isn't totally without bugs yet. v2: update emit_ib_size Signed-off-by: Marek Olšák <marek.olsak@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIESAndrey Grodzovsky2019-02-051-0/+1
| | | | | | | | | | | | | | | New chunk for dependency on start of job's execution instead on the end. This is used for GPU deadlock prevention when userspace uses mid-IB fences to wait for mid-IB work on other rings. v2: Fix typo in AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES v3: Bump KMS version v4: put old fence AFTER acquiring the scheduled fence. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Suggested-by: Christian Koenig <Christian.Koenig@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Add DCC flags for GFX9 amdgpu_boNicholas Kazlauskas2018-11-051-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | [Why] Hardware support for Delta Color Compression (DCC) decompression is available in DC for GFX9 but there's no way for userspace to enable the feature. Enabling the feature can provide improved GFX performance and power savings in many situations. [How] Extend the GFX9 tiling flags to include DCC parameters. These are logically grouped together with tiling flags even if they are technically distinct. This trivially maintains backwards compatibility with existing users of amdgpu_gem_metadata. No new IOCTls or data structures are needed to support DCC. This patch helps expose DCC attributes to both libdrm and amdgpu_dm. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Add DMCU to firmware query interfaceDavid Francis2018-09-141-0/+2
| | | | | | | | | DMCU firmware version can be read using the AMDGPU_INFO ioctl or the amdgpu_firmware_info debugfs entry Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Allow to create BO lists in CS ioctl v3Andrey Grodzovsky2018-07-161-0/+1
| | | | | | | | | | | | | | | | | | | | | | | This change is to support MESA performace optimization. Modify CS IOCTL to allow its input as command buffer and an array of buffer handles to create a temporay bo list and then destroy it when IOCTL completes. This saves on calling for BO_LIST create and destry IOCTLs in MESA and by this improves performance. v2: Avoid inserting the temp list into idr struct. v3: Remove idr alloation from amdgpu_bo_list_create. Remove useless argument from amdgpu_cs_parser_fini Minor cosmetic stuff. v4: Revert amdgpu_bo_list_destroy back to static Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* uapi/drm: add AMDGPU_HW_IP_VCN_JPEG for jpeg CSBoyuan Zhang2018-06-151-1/+2
| | | | | | | | Add AMDGPU_HW_IP_VCN_JPEG define for jpeg CS Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add kernel doc for memory domains.Samuel Li2018-06-151-0/+23
| | | | | | | | | Document the GEM domains exposed to userspace. Suggested-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Samuel Li <Samuel.Li@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Add support to change mtype for 2nd part of gart BOs on GFX9Yong Zhao2018-05-151-0/+4
| | | | | | | | | | | This change prepares for a workaround in amdkfd for a GFX9 HW bug. It requires the control stack memory of compute queues, which is allocated from the second page of MQD gart BOs, to have mtype NC, rather than the default UC. Signed-off-by: Yong Zhao <yong.zhao@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add save restore list cntl gpm and srm firmware supportHuang Rui2018-05-151-0/+6
| | | | | | | | | | RLC save/restore list cntl/gpm_mem/srm_mem ucodes are used for CGPG and gfxoff function. Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: optionally do a writeback but don't invalidate TC for IB fencesMarek Olšák2018-05-151-0/+4
| | | | | | | | | | | | | There is a new IB flag that enables this new behavior. Full invalidation is unnecessary for RELEASE_MEM and doesn't make sense when draw calls from two adjacent gfx IBs run in parallel. This will be the new default for Mesa. v2: bump the version Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: handle domain mask checking v2Chunming Zhou2018-05-151-0/+6
| | | | | | | | | | if domain is illegal, we should return error. v2: remove duplicated domain checking. Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: revert "add new bo flag that indicates BOs don't need fallback (v2)"Christian König2018-05-151-2/+0
| | | | | | | | | | | This reverts commit 6f51d28bfe8e1a676de5cd877639245bed3cc818. Makes fallback handling to complicated. This is just a feature for the GEM interface and shouldn't leak into the core BO create function. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add new bo flag that indicates BOs don't need fallback (v2)Chunming Zhou2018-04-111-0/+2
| | | | | | | | | | | | | | | | | user cases: 1. KFD wraps amdgpu_bo_create, they have no fallback case which is different with amdgpu_gem_object_create. since upstream branch has no amdgpu_amdkfd_gpuvm.c, which need KFD guys add this flag to __alloc_memory_of_gpu: + flags |= AMDGPU_GEM_CREATE_NO_FALLBACK; 2. UMD can specify this flag for their allocation as well if they like. v2: squash in merge conflict fix (Chunming) Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Cc: felix.kuehling@amd.com Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add VCN to firmware query interfaceAlex Deucher2018-03-201-0/+2
| | | | | | | | | Need to be able to query the VCN firmware version from userspace to determine supported features, etc. Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: query vram type from atombiosHawking Zhang2018-03-141-0/+1
| | | | | | | | | The vram type for dGPU is stored in umc_info while sys mem type for APU is stored in integratedsysteminfo Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Expose more GPU sensor queriesRex Zhu2018-02-191-0/+4
| | | | | | | | Add sub-queries for stable pstate shader/memory clock. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: expose the VA above the hole to userspaceChristian König2017-12-061-0/+4
| | | | | | | | | Let userspace know how much area we have above the 48bit VA hole on Vega10. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu:implement ctx query2Monk Liu2017-12-041-0/+8
| | | | | | | | | this query will give flag bits to indicate what happend on the given context Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* amdgpu: add padding to the fence to handle ioctl.Dave Airlie2017-10-201-0/+1
| | | | | | | | I don't think this ioctl is in a Linus release yet. Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add VRAM lost queryChristian König2017-10-191-0/+1
| | | | | | | | Allows userspace to figure out if VRAM was lost. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: rename context priority levelsAndres Rodriguez2017-10-191-4/+4
| | | | | | | | | | Don't leak implementation details about how each priority behaves to usermode. This allows greater flexibility in the future. Squash into c2636dc53abd8269a0930bccd564f2f195dba729 Signed-off-by: Andres Rodriguez <andresx7@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add interface for editing a foreign process's priority v3Andres Rodriguez2017-10-091-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | The AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE ioctls are used to set the priority of a different process in the current system. When a request is dropped, the process's contexts will be restored to the priority specified at context creation time. A request can be dropped by setting the override priority to AMDGPU_CTX_PRIORITY_UNSET. An fd is used to identify the remote process. This is simpler than passing a pid number, which is vulnerable to re-use, etc. This functionality is limited to DRM_MASTER since abuse of this interface can have a negative impact on the system's performance. v2: removed unused output structure v3: change refcounted interface for a regular set operation Signed-off-by: Andres Rodriguez <andresx7@gmail.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: introduce AMDGPU_CTX_PRIORITY_UNSETAndres Rodriguez2017-10-091-0/+1
| | | | | | | | | Use _INVALID to identify bad parameters and _UNSET to represent the lack of interest in a specific value. Signed-off-by: Andres Rodriguez <andresx7@gmail.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add parameter to allocate high priority contexts v11Andres Rodriguez2017-10-091-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a new context creation parameter to express a global context priority. The priority ranking in descending order is as follows: * AMDGPU_CTX_PRIORITY_HIGH_HW * AMDGPU_CTX_PRIORITY_HIGH_SW * AMDGPU_CTX_PRIORITY_NORMAL * AMDGPU_CTX_PRIORITY_LOW_SW * AMDGPU_CTX_PRIORITY_LOW_HW The driver will attempt to schedule work to the hardware according to the priorities. No latency or throughput guarantees are provided by this patch. This interface intends to service the EGL_IMG_context_priority extension, and vulkan equivalents. Setting a priority above NORMAL requires CAP_SYS_NICE or DRM_MASTER. v2: Instead of using flags, repurpose __pad v3: Swap enum values of _NORMAL _HIGH for backwards compatibility v4: Validate usermode priority and store it v5: Move priority validation into amdgpu_ctx_ioctl(), headline reword v6: add UAPI note regarding priorities requiring CAP_SYS_ADMIN v7: remove ctx->priority v8: added AMDGPU_CTX_PRIORITY_LOW, s/CAP_SYS_ADMIN/CAP_SYS_NICE v9: change the priority parameter to __s32 v10: split priorities into _SW and _HW v11: Allow DRM_MASTER without CAP_SYS_NICE Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Andres Rodriguez <andresx7@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: introduce AMDGPU_GEM_CREATE_EXPLICIT_SYNC v2Andres Rodriguez2017-10-091-0/+2
| | | | | | | | | | | | | | | | | | Introduce a flag to signal that access to a BO will be synchronized through an external mechanism. Currently all buffers shared between contexts are subject to implicit synchronization. However, this is only required for protocols that currently don't support an explicit synchronization mechanism (DRI2/3). This patch introduces the AMDGPU_GEM_CREATE_EXPLICIT_SYNC, so that users can specify when it is safe to disable implicit sync. v2: only disable explicit sync in amdgpu_cs_ioctl Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Andres Rodriguez <andresx7@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add FENCE_TO_HANDLE ioctl that returns syncobj or sync_fileMarek Olšák2017-10-061-0/+16
| | | | | | | | | for being able to convert an amdgpu fence into one of the handles. Mesa will use this. Reviewed-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add IOCTL interface for per VM BOs v3Christian König2017-08-311-0/+2
| | | | | | | | | | | | | | Add the IOCTL interface so that applications can allocate per VM BOs. Still WIP since not all corner cases are tested yet, but this reduces average CS overhead for 10K BOs from 21ms down to 48us. v2: add some extra checks, remove the WIP tag v3: rename new flag to AMDGPU_GEM_CREATE_VM_ALWAYS_VALID Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Fix the exported always on CU bitmapFlora Cui2017-06-291-0/+3
| | | | | | | | | | | | Newer asics with 4 SEs are not able to fit the entire bitmask in the original field, use an array instead. v2: keep cu_ao_mask for backward compatibility. Signed-off-by: Flora Cui <Flora.Cui@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* amdgpu: use drm sync objects for shared semaphores (v6)Dave Airlie2017-06-161-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This creates a new command submission chunk for amdgpu to add in and out sync objects around the submission. Sync objects are managed via the drm syncobj ioctls. The command submission interface is enhanced with two new chunks, one for syncobj pre submission dependencies, and one for post submission sync obj signalling, and just takes a list of handles for each. This is based on work originally done by David Zhou at AMD, with input from Christian Konig on what things should look like. In theory VkFences could be backed with sync objects and just get passed into the cs as syncobj handles as well. NOTE: this interface addition needs a version bump to expose it to userspace. TODO: update to dep_sync when rebasing onto amdgpu master. (with this - r-b from Christian) v1.1: keep file reference on import. v2: move to using syncobjs v2.1: change some APIs to just use p pointer. v3: make more robust against CS failures, we now add the wait sems but only remove them once the CS job has been submitted. v4: rewrite names of API and base on new syncobj code. v5: move post deps earlier, rename some apis v6: lookup post deps earlier, and just replace fences in post deps stage (Christian) Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add an INFO query for monitoring VRAM CPU page faultsMarek Olšák2017-05-241-0/+2
| | | | | | | | v2: bump the DRM version Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* uapi/drm: add AMDGPU_HW_IP_VCN_ENC for encode CSLeo Liu2017-05-241-1/+2
| | | | | | | Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* uapi/drm: add AMDGPU_HW_IP_VCN_DEC for decode CSLeo Liu2017-05-241-1/+2
| | | | | | Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add RAVEN family id definitionChunming Zhou2017-05-241-0/+1
| | | | | | | | RAVEN is a new APU. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add vm ioctlChunming Zhou2017-05-241-0/+22
| | | | | | | | | | | | It will be used for reserving vmid for shader debugging that requires a fixed vmid. v2: fix warning (Alex) Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: export more gpu info for gfx9Junwei Zhang2017-04-281-0/+19
| | | | | | | | | | | v2: 64-bit aligned for gpu info v3: squash in wave_front_fix Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Qiang Yu <Qiang.Yu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: fix spelling in header commentAlex Deucher2017-04-281-1/+1
| | | | | Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu:fix race conditionMonk Liu2017-04-281-1/+4
| | | | | | | | | | | | | sequence is protected by spinlock so don't access sequence in paramter seq when invoking this function. ~0 means to get the latest sequence number and 0 means none to get. Change-Id: Ib7a03f3cf5594deeb4ad333cc59b47a6bddfd1ad Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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