| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | dt-bindings: reset: meson8b: fix duplicate reset IDs | Martin Blumenstingl | 2019-12-09 | 1 | -3/+3 |
| | | | | | | | | | | | | | | | | According to the public S805 datasheet the RESET2 register uses the following bits for the PIC_DC, PSC and NAND reset lines: - PIC_DC is at bit 3 (meaning: RESET_VD_RMEM + 3) - PSC is at bit 4 (meaning: RESET_VD_RMEM + 4) - NAND is at bit 5 (meaning: RESET_VD_RMEM + 4) Update the reset IDs of these three reset lines so they don't conflict with PIC_DC and map to the actual hardware reset lines. Fixes: 79795e20a184eb ("dt-bindings: reset: Add bindings for the Meson SoC Reset Controller") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> | ||||
| * | dt-bindings: reset: amlogic,meson8b-reset: update with SPDX Licence identifier | Neil Armstrong | 2019-08-01 | 1 | -50/+1 |
| | | | | | | Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> | ||||
| * | dt-bindings: reset: Add bindings for the Meson SoC Reset Controller | Neil Armstrong | 2016-06-01 | 1 | -0/+175 |
| Add DT bindings for the Meson SoC Reset Controller documentation and the associated include file. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> | |||||
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