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path: root/drivers/gpu/drm/nouveau/nvkm/subdev
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* drm/nouveau/fb/gp102-: allow module to load even when scrubber binary is missingBen Skeggs2020-01-292-12/+32
| | | | | | | | Without relaxing this requirement, TU10x boards will fail to load without an updated linux-firmware, and TU11x will completely fail to load because FW isn't available yet. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/acr: return error when registering LSF if ACR not supportedBen Skeggs2020-01-291-1/+5
| | | | | | | This fixes an oops on TU11x GPUs where SEC2 attempts to register its falcon, and triggers a NULL-pointer deref because ACR isn't yet supported. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/pmu/gm20b,gp10b: Fix Falcon bootstrappingThierry Reding2020-01-232-4/+14
| | | | | | | | | | | | | | The low-level Falcon bootstrapping callbacks are expected to return 0 on success or a negative error code on failure. However, the implementation on Tegra returns the ID or mask of the Falcons that were bootstrapped on success, thus breaking the calling code, which treats this as failure. Fix this by making sure we only return 0 or a negative error code, just like the code for discrete GPUs does. Fixes: 86ce2a71539c ("drm/nouveau/flcn/cmdq: move command generation to subdevs") Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/acr/tu10x: initial supportBen Skeggs2020-01-154-0/+225
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core: remove previous versioned fw loaderBen Skeggs2020-01-152-4/+3
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/secboot: removeBen Skeggs2020-01-1527-4153/+0
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/acr: implement new subdev to replace "secure boot"Ben Skeggs2020-01-1514-22/+1417
| | | | | | | | | | | | | | | | | | | | | | | ACR is responsible for managing the firmware for LS (Low Secure) falcons, this was previously handled in the driver by SECBOOT. This rewrite started from some test code that attempted to replicate the procedure RM uses in order to debug early Turing ACR firmwares that were provided by NVIDIA for development. Compared with SECBOOT, the code is structured into more individual steps, with the aim of making the process easier to follow/debug, whilst making it possible to support newer firmware versions that may have a different binary format or API interface. The HS (High Secure) binary(s) are now booted earlier in device init, to match the behaviour of RM, whereas SECBOOT would delay this until we try to boot the first LS falcon. There's also additional debugging features available, with the intention of making it easier to solve issues during FW/HW bring-up in the future. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fb/gp102-: unlock VPR as part of FB initBen Skeggs2020-01-156-121/+130
| | | | | | | | | | We perform memory allocations long before we hit the code in SECBOOT that would unlock the VPR, which could potentially result in memory allocation within the locked region. Run the scrubber binary right after VRAM init to ensure we don't. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/secboot: move code to boot LS falcons to subdevsBen Skeggs2020-01-1510-99/+36
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn/msgq: pass explicit message queue pointer to recv()Ben Skeggs2020-01-151-7/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn/msgq: move handling of init message to subdevsBen Skeggs2020-01-155-2/+76
| | | | | | | | | | When the PMU/SEC2 LS FWs have booted, they'll send a message to the host with various information, including the configuration of message/command queues that are available. Move the handling for this to the relevant subdevs. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn/cmdq: move command generation to subdevsBen Skeggs2020-01-156-14/+156
| | | | | | | This moves the code to generate commands for the ACR unit of the PMU/SEC2 LS firmwares to those subdevs. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn/cmdq: split the condition for queue readiness vs pmu acr ↵Ben Skeggs2020-01-151-0/+3
| | | | | | | | | readiness This is to allow for proper separation of the LS interface code from the queue handling code. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn/msgq: explicitly create message queue from subdevsBen Skeggs2020-01-151-1/+3
| | | | | | | | | Code to interface with LS firmwares is being moved to the subdevs where it belongs, rather than living in the common falcon code. This is an incremental step towards that goal. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn/cmdq: explicitly create command queue(s) from subdevsBen Skeggs2020-01-151-1/+8
| | | | | | | | | Code to interface with LS firmwares is being moved to the subdevs where it belongs, rather than living in the common falcon code. This is an incremental step towards that goal. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn/qmgr: explicitly create queue manager from subdevsBen Skeggs2020-01-151-3/+13
| | | | | | | | | Code to interface with LS firmwares is being moved to the subdevs where it belongs, rather than living in the common falcon code. This is an incremental step towards that goal. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn: reset sec2/gsp falcons harderBen Skeggs2020-01-151-1/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn: specify queue register offsets from subdevBen Skeggs2020-01-151-0/+2
| | | | | | Also fixes the values for Turing, even though we don't use it yet. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn: specify debug/production register offset from subdevBen Skeggs2020-01-151-0/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn: move bind_context WAR out of common codeBen Skeggs2020-01-151-1/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn: specify FBIF offset from subdevBen Skeggs2020-01-152-0/+2
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/nvdec: initialise SW state for falcon from constructorBen Skeggs2020-01-151-1/+1
| | | | | | | This will allow us to register the falcon with ACR, and further customise its behaviour by providing the nvkm_falcon_func structure directly. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/sec2: initialise SW state for falcon from constructorBen Skeggs2020-01-154-5/+5
| | | | | | | This will allow us to register the falcon with ACR, and further customise its behaviour by providing the nvkm_falcon_func structure directly. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/sec2: select implementation based on available firmwareBen Skeggs2020-01-152-31/+0
| | | | | | | This will allow for further customisation of the subdev depending on what firmware is available. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/gr/gf100-: select implementation based on available FWBen Skeggs2020-01-155-153/+0
| | | | | | | This will allow for further customisation of the subdev depending on what firmware is available. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/pmu: initialise SW state for falcon from constructorBen Skeggs2020-01-1519-23/+47
| | | | | | | This will allow us to register the falcon with ACR, and further customise its behaviour by providing the nvkm_falcon_func structure directly. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/pmu: select implementation based on available firmwareBen Skeggs2020-01-1516-29/+149
| | | | | | | This will allow for further customisation of the subdev depending on what firmware is available. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/pmu/gp10b: split from gm20b implementationBen Skeggs2020-01-154-11/+42
| | | | | | | ACR LS FW loading is moving out of SECBOOT and into their specific subdevs, and the available GM20B/GP10B FWs have interface differences. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/gsp: initialise SW state for falcon from constructorBen Skeggs2020-01-153-16/+20
| | | | | | | This will allow us to register the falcon with ACR, and further customise its behaviour by providing the nvkm_falcon_func structure directly. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/gsp: select implementation based on available firmwareBen Skeggs2020-01-154-30/+93
| | | | | | | This will allow for further customisation of the subdev depending on what firmware is available. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/acr: add loaders for currently available LS firmware imagesBen Skeggs2020-01-154-0/+260
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/acr: add stub implementation for all GPUs currently supported by ↵Ben Skeggs2020-01-1513-40/+351
| | | | | | | | | SECBOOT PMU, SEC2 and GR will be modified to register their falcons with ACR before the main commit switching everything over. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core: define ACR subdevBen Skeggs2020-01-152-0/+2
| | | | | | | This will replace the current SECBOOT subdev for handling firmware on secure falcons. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fault/gv100-: fix memory leak on module unloadBen Skeggs2020-01-151-0/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fault/tu102: define nvkm_fault_func.pinBen Skeggs2020-01-151-0/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/secboot/gm20b: initialize pointer in gm20b_secboot_new()Dan Carpenter2020-01-151-3/+2
| | | | | | | | | | We accidentally set "psb" which is a no-op instead of "*psb" so it generates a static checker warning. We should probably set it before the first error return so that it's always initialized. Fixes: 923f1bd27bf1 ("drm/nouveau/secboot/gm20b: add secure boot support") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/mmu: Add correct turing page kindsJames Jones2020-01-159-19/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | Turing introduced a new simplified page kind scheme, reducing the number of possible page kinds from 256 to 16. It also is the first NVIDIA GPU in which the highest possible page kind value is not reserved as an "invalid" page kind. To address this, the invalid page kind is made an explicit property of the MMU HAL, and a new table of page kinds is added to the tu102 MMU HAL. One hardware change not addressed here is that 0x00 is technically no longer a supported page kind, and pitch surfaces are instead intended to share the block-linear generic page kind 0x06. However, because that will be a rather invasive change to nouveau and 0x00 still works fine in practice on Turing hardware, addressing this new behavior is deferred. Signed-off-by: James Jones <jajones@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fb/gf100-: declare constants as unsigned long long.Wambui Karuga2020-01-156-6/+6
| | | | | | | | | | | | | Explicitly declare constants as unsigned long long to address the following sparse warnings: warning: constant is so big it is long v2: convert to unsigned long long for compatibility with 32-bit architectures. Signed-off-by: Wambui Karuga <wambui.karugax@gmail.com> Suggested by: lia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/ltc/gp10b: Add custom L2 cache implementationThierry Reding2020-01-153-0/+68
| | | | | | | | | There are extra registers that need to be programmed to make the level 2 cache work on GP10B, such as the stream ID register that is used when an SMMU is used to translate memory addresses. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/secboot/gm20b,gp10b: Read WPR configuration from GPU registersThierry Reding2020-01-153-35/+54
| | | | | | | | | The GPUs found on Tegra SoCs have registers that can be used to read the WPR configuration. Use these registers instead of reaching into the memory controller's register space to read the same information. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fault: Add support for GP10BThierry Reding2020-01-156-6/+78
| | | | | | | | | | | There is no BAR2 on GP10B and there is no need to map through BAR2 because all memory is shared between the GPU and the CPU. Add a custom implementation of the fault sub-device that uses nvkm_memory_addr() instead of nvkm_memory_bar2() to return the address of a pinned fault buffer. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* Merge tag 'drm-next-2019-09-18' of git://anongit.freedesktop.org/drm/drmLinus Torvalds2019-09-199-8/+98
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull drm updates from Dave Airlie: "This is the main pull request for 5.4-rc1 merge window. I don't think there is anything outstanding so next week should just be fixes, but we'll see if I missed anything. I landed some fixes earlier in the week but got delayed writing summary and sending it out, due to a mix of sick kid and jetlag! There are some fixes pending, but I'd rather get the main merge out of the way instead of delaying it longer. It's also pretty large in commit count and new amd header file size. The largest thing is four new amdgpu products (navi12/14, arcturus and renoir APU support). Otherwise it's pretty much lots of work across the board, i915 has started landing tigerlake support, lots of icelake fixes and lots of locking reworking for future gpu support, lots of header file rework (drmP.h is nearly gone), some old legacy hacks (DRM_WAIT_ON) have been put into the places they are needed. uapi: - content protection type property for HDCP core: - rework include dependencies - lots of drmP.h removals - link rate calculation robustness fix - make fb helper map only when required - add connector->DDC adapter link - DRM_WAIT_ON removed - drop DRM_AUTH usage from drivers dma-buf: - reservation object fence helper dma-fence: - shrink dma_fence struct - merge signal functions - store timestamps in dma_fence - selftests ttm: - embed drm_get_object struct into ttm_buffer_object - release_notify callback bridges: - sii902x - audio graph card support - tc358767 - aux data handling rework - ti-snd64dsi86 - debugfs support, DSI mode flags support panels: - Support for GiantPlus GPM940B0, Sharp LQ070Y3DG3B, Ortustech COM37H3M, Novatek NT39016, Sharp LS020B1DD01D, Raydium RM67191, Boe Himax8279d, Sharp LD-D5116Z01B - TI nspire, NEC NL8048HL11, LG Philips LB035Q02, Sharp LS037V7DW01, Sony ACX565AKM, Toppoly TD028TTEC1 Toppoly TD043MTEA1 i915: - Initial tigerlake platform support - Locking simplification work, general all over refactoring. - Selftests - HDCP debug info improvements - DSI properties - Icelake display PLL fixes, colorspace fixes, bandwidth fixes, DSI suspend/resume - GuC fixes - Perf fixes - ElkhartLake enablement - DP MST fixes - GVT - command parser enhancements amdgpu: - add wipe memory on release flag for buffer creation - Navi12/14 support (may be marked experimental) - Arcturus support - Renoir APU support - mclk DPM for Navi - DC display fixes - Raven scatter/gather support - RAS support for GFX - Navi12 + Arcturus power features - GPU reset for Picasso - smu11 i2c controller support amdkfd: - navi12/14 support - Arcturus support radeon: - kexec fix nouveau: - improved display color management - detect lack of GPU power cables vmwgfx: - evicition priority support - remove unused security feature msm: - msm8998 display support - better async commit support for cursor updates etnaviv: - per-process address space support - performance counter fixes - softpin support mcde: - DCS transfers fix exynos: - drmP.h cleanup lima: - reduce logging kirin: - misc clenaups komeda: - dual-link support - DT memory regions hisilicon: - misc fixes imx: - IPUv3 image converter fixes - 32-bit RGB V4L2 pixel format support ingenic: - more support for panel related cases mgag200: - cursor support fix panfrost: - export GPU features register to userspace - gpu heap allocations - per-fd address space support pl111: - CLD pads wiring support removed from DT rockchip: - rework to use DRM PSR helpers - fix bug in VOP_WIN_GET macro - DSI DT binding rework sun4i: - improve support for color encoding and range - DDC enabled GPIO tinydrm: - rework SPI support - improve MIPI-DBI support - moved to drm/tiny vkms: - rework CRC tracking dw-hdmi: - get_eld and i2s improvements gm12u320: - misc fixes meson: - global code cleanup - vpu feature detect omap: - alpha/pixel blend mode properties rcar-du: - misc fixes" * tag 'drm-next-2019-09-18' of git://anongit.freedesktop.org/drm/drm: (2112 commits) drm/nouveau/bar/gm20b: Avoid BAR1 teardown during init drm/nouveau: Fix ordering between TTM and GEM release drm/nouveau/prime: Extend DMA reservation object lock drm/nouveau: Fix fallout from reservation object rework drm/nouveau/kms/nv50-: Don't create MSTMs for eDP connectors drm/i915: Use NOEVICT for first pass on attemping to pin a GGTT mmap drm/i915: to make vgpu ppgtt notificaiton as atomic operation drm/i915: Flush the existing fence before GGTT read/write drm/i915: Hold irq-off for the entire fake lock period drm/i915/gvt: update RING_START reg of vGPU when the context is submitted to i915 drm/i915/gvt: update vgpu workload head pointer correctly drm/mcde: Fix DSI transfers drm/msm: Use the correct dma_sync calls harder drm/msm: remove unlikely() from WARN_ON() conditions drm/msm/dsi: Fix return value check for clk_get_parent drm/msm: add atomic traces drm/msm/dpu: async commit support drm/msm: async commit support drm/msm: split power control from prepare/complete_commit drm/msm: add kms->flush_commit() ...
| * drm/nouveau/bar/gm20b: Avoid BAR1 teardown during initThierry Reding2019-09-171-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | Writing the 0x1704 (BUS_BAR1_BLOCK) register causes the GPU to probe the memory region at the programmed address. The result is an address decode error in the external memory controller because address 0, which is what is written to the register, is not designated as accessible to devices. Avoid triggering DMA from the GPU by removing teardown of the BAR1. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| * drm/nouveau/volt: Fix for some cards having 0 maximum voltageMark Menzynski2019-08-231-0/+2
| | | | | | | | | | | | | | | | | | | | | | Some, mostly Fermi, vbioses appear to have zero max voltage. That causes Nouveau to not parse voltage entries, thus users not being able to set higher clocks. When changing this value Nvidia driver still appeared to ignore it, and I wasn't able to find out why, thus the code is ignoring the value if it is zero. CC: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Mark Menzynski <mmenzyns@redhat.com> Reviewed-by: Karol Herbst <kherbst@redhat.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| * drm/nouveau/gpio: check function 76 in the power check as wellMark Menzynski2019-08-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Added GPIO is "Power Alert". It's uncertain if this GPIO is set on GPU initialization or only if a change is detected by the GPU at runtime. This GPIO can be found on Tesla and sometimes on Fermi GPUs. Untested, wrote according to documentation. Signed-off-by: Mark Menzynski <mmenzyns@redhat.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| * drm/nouveau/gpio: check the gpio function 16 in the power check as wellMark Menzynski2019-08-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Added GPIO is "Thermal and External Power Detect". It's uncertain if this GPIO is set on GPU initialization or only if a change is detected by the GPU at runtime. This GPIO can be found in Rankine and Curie and rarely on Tesla GPUs VBIOS. Untested, wrote according to documentation. Signed-off-by: Mark Menzynski <mmenzyns@redhat.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| * drm/nouveau/gpio: fail if gpu external power is missingMark Menzynski2019-08-231-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, nouveau doesn't check if GPU is missing power. This patch makes nouveau fail when this happens on latest GPUs. It checks GPIO function 121 (External Power Emergency), which should detect power problems on GPU initialization. This can be disabled with nouveau.config=NvPowerChecks=1 Tested on TU104, GP106 and GF100. v3: * Add config override for disabling power checks Signed-off-by: Mark Menzynski <mmenzyns@redhat.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| * drm/nouveau/therm: don't attempt fan control where PMU is already managing itBen Skeggs2019-08-232-3/+22
| | | | | | | | | | | | | | | | | | | | | | There's already a condition in place which attempts to detect this, but since we've begun to require a PMU subdev even on boards where we don't load a custom FW, it's become inaccurate. This will prevent unnecessarily running a periodic fan update thread on GP100 and newer, where we don't yet override the default PMU FW. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| * drm/nouveau/therm: skip probing for devices not specified in thermal tablesBen Skeggs2019-08-232-0/+16
| | | | | | | | | | | | | | | | | | Saves some time during driver load, as described by the relevant section[1] of the DCB 4.x specification. [1] https://nvidia.github.io/open-gpu-doc/DCB/DCB-4.x-Specification.html#_i2c_device_table Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| * drm/nouveau/bios/init: handle INIT_RESET_END devinit opcodeRhys Kidd2019-08-231-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signal that the reset sequence has completed. This opcode signals that the software reset sequence has completed. Ordinarily, no actual operations are performed by the opcode. However it allows for possible software work arounds by devinit engines in software agents other than the VBIOS, such as the resman, FCODE, and EFI driver. Signed-off-by: Rhys Kidd <rhyskidd@gmail.com> Reviewed-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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