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* drm/nouveau/gr/tu10x: initial supportBen Skeggs2020-01-152-0/+4
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/acr/tu10x: initial supportBen Skeggs2020-01-151-0/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core: remove previous versioned fw loaderBen Skeggs2020-01-151-4/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/secboot: removeBen Skeggs2020-01-152-31/+0
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/acr: implement new subdev to replace "secure boot"Ben Skeggs2020-01-153-1/+281
| | | | | | | | | | | | | | | | | | | | | | | ACR is responsible for managing the firmware for LS (Low Secure) falcons, this was previously handled in the driver by SECBOOT. This rewrite started from some test code that attempted to replicate the procedure RM uses in order to debug early Turing ACR firmwares that were provided by NVIDIA for development. Compared with SECBOOT, the code is structured into more individual steps, with the aim of making the process easier to follow/debug, whilst making it possible to support newer firmware versions that may have a different binary format or API interface. The HS (High Secure) binary(s) are now booted earlier in device init, to match the behaviour of RM, whereas SECBOOT would delay this until we try to boot the first LS falcon. There's also additional debugging features available, with the intention of making it easier to solve issues during FW/HW bring-up in the future. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fb/gp102-: unlock VPR as part of FB initBen Skeggs2020-01-152-0/+33
| | | | | | | | | | We perform memory allocations long before we hit the code in SECBOOT that would unlock the VPR, which could potentially result in memory allocation within the locked region. Run the scrubber binary right after VRAM init to ensure we don't. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core/memory: add macros to read/write blocks from objectsBen Skeggs2020-01-151-0/+16
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/secboot: move code to boot LS falcons to subdevsBen Skeggs2020-01-156-12/+29
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn/msgq: rename msgq-related nvkm_msgqueue_queue to ↵Ben Skeggs2020-01-151-3/+0
| | | | | | nvkm_falcon_msgq Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn/msgq: pass explicit message queue pointer to recv()Ben Skeggs2020-01-152-1/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn/msgq: move handling of init message to subdevsBen Skeggs2020-01-156-1/+57
| | | | | | | | | | When the PMU/SEC2 LS FWs have booted, they'll send a message to the host with various information, including the configuration of message/command queues that are available. Move the handling for this to the relevant subdevs. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn/cmdq: move command generation to subdevsBen Skeggs2020-01-154-4/+99
| | | | | | | This moves the code to generate commands for the ACR unit of the PMU/SEC2 LS firmwares to those subdevs. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn/cmdq: rename cmdq-related nvkm_msqqueue_queue to ↵Ben Skeggs2020-01-151-0/+1
| | | | | | nvkm_falcon_cmdq Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn/cmdq: implement a more explicit send() interfaceBen Skeggs2020-01-151-0/+5
| | | | | | | Takes the command queue pointer directly instead of requiring a function to lookup based on an queue type, as well as an explicit timeout value. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn/cmdq: split the condition for queue readiness vs pmu acr ↵Ben Skeggs2020-01-151-0/+2
| | | | | | | | | readiness This is to allow for proper separation of the LS interface code from the queue handling code. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn/qmgr: allow arbtrary priv + return code for callbacksBen Skeggs2020-01-151-0/+18
| | | | | | | | | | | | Code to interface with LS firmwares is being moved to the subdevs where it belongs, rather than living in the common falcon code. Arbitrary private data passed to callbacks is to allow for something other than struct nvkm_msgqueue to be passed into the callback (like the pointer to the subdev itself, for example), and the return code will be used where we'd like to detect failure from synchronous messages. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn/msgq: explicitly create message queue from subdevsBen Skeggs2020-01-154-0/+10
| | | | | | | | | Code to interface with LS firmwares is being moved to the subdevs where it belongs, rather than living in the common falcon code. This is an incremental step towards that goal. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn/cmdq: explicitly create command queue(s) from subdevsBen Skeggs2020-01-154-0/+13
| | | | | | | | | Code to interface with LS firmwares is being moved to the subdevs where it belongs, rather than living in the common falcon code. This is an incremental step towards that goal. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn/qmgr: explicitly create queue manager from subdevsBen Skeggs2020-01-153-0/+7
| | | | | | | | | Code to interface with LS firmwares is being moved to the subdevs where it belongs, rather than living in the common falcon code. This is an incremental step towards that goal. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn: add printk macrosBen Skeggs2020-01-151-0/+9
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn: reset sec2/gsp falcons harderBen Skeggs2020-01-152-0/+2
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn: specify queue register offsets from subdevBen Skeggs2020-01-151-0/+6
| | | | | | Also fixes the values for Turing, even though we don't use it yet. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn: specify debug/production register offset from subdevBen Skeggs2020-01-151-0/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn: specify EMEM address from subdevBen Skeggs2020-01-151-1/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn: move bind_context WAR out of common codeBen Skeggs2020-01-151-0/+2
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn: specify FBIF offset from subdevBen Skeggs2020-01-151-0/+3
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/nvenc: add a stub implementation for the GPUs where it should be ↵Ben Skeggs2020-01-152-2/+12
| | | | | | | | supported Mostly so we don't lose info hidden in falcon. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/nvdec/gm107: rename from gp102 implementationBen Skeggs2020-01-151-1/+1
| | | | | | | NVDEC is available from GM107, and we currently only have a stub implementation anyway, let's make it explicit. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/nvdec: initialise SW state for falcon from constructorBen Skeggs2020-01-151-3/+2
| | | | | | | This will allow us to register the falcon with ACR, and further customise its behaviour by providing the nvkm_falcon_func structure directly. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/nvdec: select implementation based on available fwBen Skeggs2020-01-151-0/+1
| | | | | | | This will allow for further customisation of the subdev depending on what firmware is available. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/sec2: use falcon funcsBen Skeggs2020-01-151-1/+0
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/sec2: initialise SW state for falcon from constructorBen Skeggs2020-01-151-1/+2
| | | | | | | This will allow us to register the falcon with ACR, and further customise its behaviour by providing the nvkm_falcon_func structure directly. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/sec2: select implementation based on available firmwareBen Skeggs2020-01-151-0/+2
| | | | | | | This will allow for further customisation of the subdev depending on what firmware is available. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/sec2/gp108: split from gp102 implementationBen Skeggs2020-01-151-0/+1
| | | | | | | ACR LS FW loading is moving out of SECBOOT and into their specific subdevs, and the available GP108/GV100 FWs differ from the other GP10x boards. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/gr/gp108: split from gp107Ben Skeggs2020-01-151-0/+1
| | | | | | | ACR LS FW loading is moving out of SECBOOT and into their specific subdevs, and the available GP107/GP108 FWs have interface differences. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/pmu: initialise SW state for falcon from constructorBen Skeggs2020-01-151-2/+2
| | | | | | | This will allow us to register the falcon with ACR, and further customise its behaviour by providing the nvkm_falcon_func structure directly. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/pmu/gp10b: split from gm20b implementationBen Skeggs2020-01-151-0/+1
| | | | | | | ACR LS FW loading is moving out of SECBOOT and into their specific subdevs, and the available GM20B/GP10B FWs have interface differences. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/gsp: initialise SW state for falcon from constructorBen Skeggs2020-01-151-3/+2
| | | | | | | This will allow us to register the falcon with ACR, and further customise its behaviour by providing the nvkm_falcon_func structure directly. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/acr: add loaders for currently available LS firmware imagesBen Skeggs2020-01-154-0/+141
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/acr: add stub implementation for all GPUs currently supported by ↵Ben Skeggs2020-01-151-0/+8
| | | | | | | | | SECBOOT PMU, SEC2 and GR will be modified to register their falcons with ACR before the main commit switching everything over. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core: define ACR subdevBen Skeggs2020-01-152-0/+13
| | | | | | | This will replace the current SECBOOT subdev for handling firmware on secure falcons. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core: add representation of generic binary objectsBen Skeggs2020-01-151-0/+13
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core: add a macro to better handle multiple firmware versionsBen Skeggs2020-01-151-0/+40
| | | | | | | Will be used in upcoming commits to allow subdevs to better customise themselves based on which (if any) firmware is available. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn: export existing funcsBen Skeggs2020-01-152-3/+22
| | | | | | These will be used in upcoming commits which will provide more customisation. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/flcn: move fetching of configuration until first useBen Skeggs2020-01-151-0/+2
| | | | | | | | | | | | | | | We want to be able to register falcons with ACR during the constructor for the subdev it belongs to, however, we may not have access to the falcon's registers prior to DEVINIT. Delay touching registers until the first time the falcon is acquired. This may temporarily break secboot on non-production boards due to not being able to determine whether the falcon is in debug or production mode, the new ACR subdev will not have this issue, and it's not a use-case that's terribly important for bisectability. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/mmu: Add correct turing page kindsJames Jones2020-01-152-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Turing introduced a new simplified page kind scheme, reducing the number of possible page kinds from 256 to 16. It also is the first NVIDIA GPU in which the highest possible page kind value is not reserved as an "invalid" page kind. To address this, the invalid page kind is made an explicit property of the MMU HAL, and a new table of page kinds is added to the tu102 MMU HAL. One hardware change not addressed here is that 0x00 is technically no longer a supported page kind, and pitch surfaces are instead intended to share the block-linear generic page kind 0x06. However, because that will be a rather invasive change to nouveau and 0x00 still works fine in practice on Turing hardware, addressing this new behavior is deferred. Signed-off-by: James Jones <jajones@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/ltc/gp10b: Add custom L2 cache implementationThierry Reding2020-01-151-0/+1
| | | | | | | | | There are extra registers that need to be programmed to make the level 2 cache work on GP10B, such as the stream ID register that is used when an SMMU is used to translate memory addresses. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fault: Add support for GP10BThierry Reding2020-01-151-0/+1
| | | | | | | | | | | There is no BAR2 on GP10B and there is no need to map through BAR2 because all memory is shared between the GPU and the CPU. Add a custom implementation of the fault sub-device that uses nvkm_memory_addr() instead of nvkm_memory_bar2() to return the address of a pinned fault buffer. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/gpio: check function 76 in the power check as wellMark Menzynski2019-08-231-0/+1
| | | | | | | | | | | | | Added GPIO is "Power Alert". It's uncertain if this GPIO is set on GPU initialization or only if a change is detected by the GPU at runtime. This GPIO can be found on Tesla and sometimes on Fermi GPUs. Untested, wrote according to documentation. Signed-off-by: Mark Menzynski <mmenzyns@redhat.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/gpio: check the gpio function 16 in the power check as wellMark Menzynski2019-08-231-0/+1
| | | | | | | | | | | | | | Added GPIO is "Thermal and External Power Detect". It's uncertain if this GPIO is set on GPU initialization or only if a change is detected by the GPU at runtime. This GPIO can be found in Rankine and Curie and rarely on Tesla GPUs VBIOS. Untested, wrote according to documentation. Signed-off-by: Mark Menzynski <mmenzyns@redhat.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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