summaryrefslogtreecommitdiffstats
path: root/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
Commit message (Expand)AuthorAgeFilesLines
* clk: sunxi-ng: sun6i: Fix enable bit offset for hdmi-ddc module clockChen-Yu Tsai2017-03-061-1/+1
* clk: sunxi-ng: A31: Fix spdif clock registerMarcus Cooper2017-01-021-2/+2
* clk: sunxi-ng: sun6i-a31: Enable PLL-MIPI LDOs when ungating itChen-Yu Tsai2016-11-211-1/+1
* clk: sunxi-ng: sun6i-a31: Force AHB1 clock to use PLL6 as parentChen-Yu Tsai2016-10-191-0/+12
* clk: sunxi-ng: sun6i-a31: Fix register offset for mipi-csi clkChen-Yu Tsai2016-09-161-1/+1
* clk: sunxi-ng: sun6i-a31: set CLK_SET_RATE_UNGATE for all PLLsChen-Yu Tsai2016-09-161-10/+10
* clk: sunxi-ng: sun6i-a31: Set CLK_SET_RATE_PARENT for display output clocksChen-Yu Tsai2016-09-161-9/+13
* clk: sunxi-ng: Add A31/A31s clocksChen-Yu Tsai2016-08-251-0/+1235
OpenPOWER on IntegriCloud