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path: root/drivers/clk/socfpga/clk.h
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* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288Thomas Gleixner2019-06-051-10/+1
* clk: socfpga: stratix10: add clock driver for Stratix10 platformDinh Nguyen2018-04-061-0/+4
* clk: socfpga: Fix the smplsel on Arria10 and Stratix10Dinh Nguyen2017-06-191-0/+3
* clk: socfpga: Add a second parent option for the dbg_base_clkDinh Nguyen2015-08-241-0/+1
* clk: socfpga: switch to GENMASK()Andy Shevchenko2015-07-281-1/+0
* clk: socfpga: Remove clk.h and clkdev.h includesStephen Boyd2015-07-201-1/+0
* clk: socfpga: add a clock driver for the Arria 10 platformDinh Nguyen2015-05-211-0/+5
* clk: socfpga: update clk.h so for Arria10 platform to useDinh Nguyen2015-05-211-1/+5
* clk: socfpga: add divider registers to the main pll outputsDinh Nguyen2014-05-121-0/+4
* clk: socfpga: split clk codeSteffen Trumtrar2014-02-181-0/+57
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