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path: root/drivers/clk/mediatek/clk-mtk.h
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* clk: mediatek: Register clock gate with deviceWeiyi Lu2019-09-171-0/+5
* clk: reset: Modify reset-controller driveryong.liang2019-08-081-0/+3
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174Thomas Gleixner2019-05-301-9/+1
* clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_dataWeiyi Lu2019-04-111-0/+1
* clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_dataOwen Chen2019-04-111-0/+2
*-. Merge branches 'clk-ingenic', 'clk-mtk-mux', 'clk-qcom-sdm845-pcie', 'clk-mtk...Stephen Boyd2019-03-081-8/+21
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| | * clk: mediatek: Add flags to mtk_gateJasper Mattsson2019-02-261-0/+1
| | * clk: mediatek: Add MUX_FLAGS macroJasper Mattsson2019-02-261-2/+6
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| * clk: mediatek: add MUX_GATE_FLAGS_2chunhui dai2019-02-251-6/+14
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* clk: mediatek: adjust dependency of reset.c to avoid unexpectedly being builtSean Wang2018-01-101-7/+0
* clk: mediatek: Fix all warnings for missing struct clk_onecell_dataSean Wang2017-12-261-0/+1
* clk: mediatek: add the option for determining PLL source clockChen Zhong2017-11-021-0/+1
* clk: mediatek: Add MT2712 clock supportweiyi.lu@mediatek.com2017-11-021-0/+2
* clk: mediatek: Add MT2701 clock supportShunli Wang2016-11-081-5/+36
* clk: mediatek: make dpi0_sel propagate rate changesPhilipp Zabel2016-05-061-2/+13
* clk: mediatek: Add USB clock support in MT8173 APMIXEDSYSJames Liao2015-10-011-0/+3
* clk: mediatek: Add fixed clocks support for Mediatek SoC.James Liao2015-10-011-0/+17
* clk: mediatek: Remove unused code from MT8173.James Liao2015-10-011-2/+2
* Merge branch 'cleanup-clk-h-includes' into clk-nextStephen Boyd2015-07-281-1/+2
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| * clk: mediatek: Properly include clk.hStephen Boyd2015-07-201-1/+2
* | clk: mediatek: Add MT8173 MMPLL change rate supportJames Liao2015-07-281-0/+6
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* clk: mediatek: Add reset controller supportSascha Hauer2015-05-051-0/+10
* clk: mediatek: Add initial common clock support for Mediatek SoCs.James Liao2015-05-051-0/+159
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