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path: root/arch/mips/kernel/smp-mt.c
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* MIPS: GIC: Send IPIs using the GICSteven J. Hill2014-01-221-0/+27
* MIPS: MT: Mark existing TCs as presentMarkos Chandras2014-01-221-0/+1
* MIPS: Delete __cpuinit/__CPUINIT usage from MIPS codePaul Gortmaker2013-07-141-3/+3
* MIPS: Move 'gic_present' to common location.Steven J. Hill2013-05-091-2/+1
* MIPS: Whitespace cleanup.Ralf Baechle2013-02-011-2/+2
* MIPS: Fix build error for non-malta VSMP kernelAnoop P A2012-08-221-0/+2
* Disintegrate asm/system.h for MIPSDavid Howells2012-03-281-1/+0
* atomic: use <linux/atomic.h>Arun Sharma2011-07-261-1/+1
* Fix common misspellingsLucas De Marchi2011-03-311-1/+1
* MIPS: MT: Fix typo in comment.Ralf Baechle2010-12-161-1/+1
* cpumask: Use accessors for cpu_*_mask: mipsRusty Russell2009-09-241-1/+1
* cpumask: arch_send_call_function_ipi_mask: mipsRusty Russell2009-09-241-2/+2
* cpumask: centralize cpu_online_map and cpu_possible_mapRusty Russell2008-12-131-1/+1
* [MIPS] Add support for MIPS CMP platform.Ralf Baechle2008-04-281-81/+15
* [MIPS] Remove TLB sanitation codeChris Dearman2008-04-281-47/+0
* [MIPS] SMP: Call platform methods via ops structure.Ralf Baechle2008-01-291-87/+106
* [MIPS] MT: Scheduler support for SMTRalf Baechle2008-01-291-1/+5
* [MIPS] Fix "no space between function name and open parenthesis" warnings.Ralf Baechle2007-10-111-1/+1
* [MIPS] SMP: Scatter __cpuinit over the code as needed.Ralf Baechle2007-08-271-3/+3
* [MIPS] VSMP: Fix initialization ordering bug.Ralf Baechle2007-07-041-2/+2
* [MIPS] Separate performance counter interruptsChris Dearman2007-06-141-6/+6
* [MIPS] Define MIPS_CPU_IRQ_BASE in generic headerAtsushi Nemoto2007-02-061-5/+4
* [MIPS] use generic_handle_irq, handle_level_irq, handle_percpu_irqAtsushi Nemoto2006-11-301-0/+2
* [MIPS] VSMP: Synchronize cp0 counters on bootup.Ralf Baechle2006-10-311-0/+2
* [MIPS] VSMP: Fix initialization ordering bug.Ralf Baechle2006-10-311-69/+83
* [MIPS] Complete fixes after removal of pt_regs argument to int handlers.Ralf Baechle2006-10-081-8/+8
* [MIPS] MT: Initialise all writable bits in Cause register to zero.Chris Dearman2006-09-271-1/+1
* [PATCH] irq-flags: MIPS: Use the new IRQF_ constantsThomas Gleixner2006-07-021-2/+2
* [MIPS] FPU affinity for MT ASE.Ralf Baechle2006-04-191-0/+11
* [MIPS] MT: Improved multithreading support.Ralf Baechle2006-04-191-0/+349
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