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* iio: frequency: adf4371: Add support for output stage muteStefan Popa2019-06-261-0/+7
| | | | | | | | | | Another feature of the ADF4371/ADF4372 is that the supply current to the RF8P and RF8N output stage can shut down until the ADF4371 achieves lock as measured by the digital lock detect circuitry. The mute to lock detect bit (MUTE_LD) in REG25 enables this function. Signed-off-by: Stefan Popa <stefan.popa@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
* dt-bindings: iio: frequency: Add ADF4372 PLL documentationStefan Popa2019-06-261-2/+4
| | | | | | | | Document support for ADF4372 SPI Wideband Synthesizer. Signed-off-by: Stefan Popa <stefan.popa@analog.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
* dt-bindings: iio: frequency: Add docs for ADF4371 PLLStefan Popa2019-06-171-0/+54
Document support for Analog Devices ADF4371 SPI Wideband Synthesizer. Signed-off-by: Stefan Popa <stefan.popa@analog.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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