diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/powerpc/power9/translation.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/powerpc/power9/translation.json | 314 |
1 files changed, 137 insertions, 177 deletions
diff --git a/tools/perf/pmu-events/arch/powerpc/power9/translation.json b/tools/perf/pmu-events/arch/powerpc/power9/translation.json index d75859836f14..8c0f12024afa 100644 --- a/tools/perf/pmu-events/arch/powerpc/power9/translation.json +++ b/tools/perf/pmu-events/arch/powerpc/power9/translation.json @@ -1,272 +1,232 @@ [ {, - "EventCode": "0x10028", - "EventName": "PM_STALL_END_ICT_EMPTY", - "BriefDescription": "The number a times the core transitioned from a stall to ICT-empty for this thread", - "PublicDescription": "" - }, - {, - "EventCode": "0x1C04E", - "EventName": "PM_DATA_FROM_L2MISS_MOD", - "BriefDescription": "The processor's data cache was reloaded from a location other than the local core's L2 due to a demand load", - "PublicDescription": "" + "EventCode": "0x1E", + "EventName": "PM_CYC", + "BriefDescription": "Processor cycles" }, {, - "EventCode": "0x14044", - "EventName": "PM_INST_FROM_L3_NO_CONFLICT", - "BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 without conflict due to an instruction fetch (not prefetch)", - "PublicDescription": "" + "EventCode": "0x30010", + "EventName": "PM_PMC2_OVERFLOW", + "BriefDescription": "Overflow from counter 2" }, {, - "EventCode": "0x1404E", - "EventName": "PM_INST_FROM_L2MISS", - "BriefDescription": "The processor's Instruction cache was reloaded from a location other than the local core's L2 due to an instruction fetch (not prefetch)", - "PublicDescription": "" + "EventCode": "0x3C046", + "EventName": "PM_DATA_FROM_L21_SHR", + "BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a demand load" }, {, - "EventCode": "0x1D142", - "EventName": "PM_MRK_DATA_FROM_L3.1_ECO_SHR_CYC", - "BriefDescription": "Duration in cycles to reload with Shared (S) data from another core's ECO L3 on the same chip due to a marked load", - "PublicDescription": "" + "EventCode": "0x4D05C", + "EventName": "PM_DP_QP_FLOP_CMPL", + "BriefDescription": "Double-Precion or Quad-Precision instruction completed" }, {, - "EventCode": "0x15048", - "EventName": "PM_IPTEG_FROM_ON_CHIP_CACHE", - "BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a instruction side request", - "PublicDescription": "" + "EventCode": "0x4E04C", + "EventName": "PM_DPTEG_FROM_DMEM", + "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included" }, {, - "EventCode": "0x1504A", - "EventName": "PM_IPTEG_FROM_RL2L3_SHR", - "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request", - "PublicDescription": "" + "EventCode": "0x20016", + "EventName": "PM_ST_FIN", + "BriefDescription": "Store finish count. Includes speculative activity" }, {, - "EventCode": "0x1E058", - "EventName": "PM_STCX_FAIL", - "BriefDescription": "stcx failed", - "PublicDescription": "" + "EventCode": "0x44042", + "EventName": "PM_INST_FROM_L3", + "BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 due to an instruction fetch (not prefetch)" }, {, - "EventCode": "0x1F15E", - "EventName": "PM_MRK_PROBE_NOP_CMPL", - "BriefDescription": "Marked probeNops completed", - "PublicDescription": "" + "EventCode": "0x1504A", + "EventName": "PM_IPTEG_FROM_RL2L3_SHR", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request" }, {, - "EventCode": "0x20112", - "EventName": "PM_MRK_NTF_FIN", - "BriefDescription": "Marked next to finish instruction finished", - "PublicDescription": "" + "EventCode": "0x40132", + "EventName": "PM_MRK_LSU_FIN", + "BriefDescription": "lsu marked instr PPC finish" }, {, - "EventCode": "0x20016", - "EventName": "PM_ST_FIN", - "BriefDescription": "Store finish count. Includes speculative activity", - "PublicDescription": "" + "EventCode": "0x3C05C", + "EventName": "PM_CMPLU_STALL_VFXU", + "BriefDescription": "Finish stall due to a vector fixed point instruction in the execution pipeline. These instructions get routed to the ALU, ALU2, and DIV pipes" }, {, - "EventCode": "0x20018", - "EventName": "PM_ST_FWD", - "BriefDescription": "Store forwards that finished", - "PublicDescription": "" + "EventCode": "0x30066", + "EventName": "PM_LSU_FIN", + "BriefDescription": "LSU Finished a PPC instruction (up to 4 per cycle)" }, {, "EventCode": "0x2011C", "EventName": "PM_MRK_NTC_CYC", - "BriefDescription": "Cycles during which the marked instruction is next to complete (completion is held up because the marked instruction hasn't completed yet)", - "PublicDescription": "" + "BriefDescription": "Cycles during which the marked instruction is next to complete (completion is held up because the marked instruction hasn't completed yet)" + }, + {, + "EventCode": "0x3E048", + "EventName": "PM_DPTEG_FROM_DL2L3_SHR", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included" }, {, "EventCode": "0x2E018", "EventName": "PM_CMPLU_STALL_VFXLONG", - "BriefDescription": "Completion stall due to a long latency vector fixed point instruction (division, square root)", - "PublicDescription": "" + "BriefDescription": "Completion stall due to a long latency vector fixed point instruction (division, square root)" }, {, - "EventCode": "0x2E01C", - "EventName": "PM_CMPLU_STALL_TLBIE", - "BriefDescription": "Finish stall because the NTF instruction was a tlbie waiting for response from L2", - "PublicDescription": "" + "EventCode": "0x1C04E", + "EventName": "PM_DATA_FROM_L2MISS_MOD", + "BriefDescription": "The processor's data cache was reloaded from a location other than the local core's L2 due to a demand load" }, {, - "EventCode": "0x2003E", - "EventName": "PM_LSU_LMQ_SRQ_EMPTY_CYC", - "BriefDescription": "Cycles in which the LSU is empty for all threads (lmq and srq are completely empty)", - "PublicDescription": "" + "EventCode": "0x15048", + "EventName": "PM_IPTEG_FROM_ON_CHIP_CACHE", + "BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a instruction side request" }, {, - "EventCode": "0x24042", - "EventName": "PM_INST_FROM_L3_MEPF", - "BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to an instruction fetch (not prefetch)", - "PublicDescription": "" + "EventCode": "0x34046", + "EventName": "PM_INST_FROM_L21_SHR", + "BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the same chip due to an instruction fetch (not prefetch)" }, {, - "EventCode": "0x2D14A", - "EventName": "PM_MRK_DATA_FROM_RL2L3_MOD_CYC", - "BriefDescription": "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load", - "PublicDescription": "" + "EventCode": "0x1E058", + "EventName": "PM_STCX_FAIL", + "BriefDescription": "stcx failed" }, {, - "EventCode": "0x25046", - "EventName": "PM_IPTEG_FROM_RL2L3_MOD", - "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request", - "PublicDescription": "" + "EventCode": "0x20112", + "EventName": "PM_MRK_NTF_FIN", + "BriefDescription": "Marked next to finish instruction finished" + }, + {, + "EventCode": "0x300F0", + "EventName": "PM_ST_MISS_L1", + "BriefDescription": "Store Missed L1" + }, + {, + "EventCode": "0x4C046", + "EventName": "PM_DATA_FROM_L21_MOD", + "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a demand load" }, {, "EventCode": "0x2504A", "EventName": "PM_IPTEG_FROM_RL4", - "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a instruction side request", - "PublicDescription": "" + "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a instruction side request" }, {, - "EventCode": "0x2504C", - "EventName": "PM_IPTEG_FROM_MEMORY", - "BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a instruction side request", - "PublicDescription": "" + "EventCode": "0x2003E", + "EventName": "PM_LSU_LMQ_SRQ_EMPTY_CYC", + "BriefDescription": "Cycles in which the LSU is empty for all threads (lmq and srq are completely empty)" }, {, "EventCode": "0x201E6", "EventName": "PM_THRESH_EXC_32", - "BriefDescription": "Threshold counter exceeded a value of 32", - "PublicDescription": "" + "BriefDescription": "Threshold counter exceeded a value of 32" }, {, - "EventCode": "0x200F0", - "EventName": "PM_ST_CMPL", - "BriefDescription": "Stores completed from S2Q (2nd-level store queue).", - "PublicDescription": "" - }, - {, - "EventCode": "0x200FE", - "EventName": "PM_DATA_FROM_L2MISS", - "BriefDescription": "Demand LD - L2 Miss (not L2 hit)", - "PublicDescription": "" + "EventCode": "0x4405C", + "EventName": "PM_CMPLU_STALL_VDP", + "BriefDescription": "Finish stall because the NTF instruction was a vector instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Not qualified multicycle. Qualified by vector" }, {, - "EventCode": "0x30010", - "EventName": "PM_PMC2_OVERFLOW", - "BriefDescription": "Overflow from counter 2", - "PublicDescription": "" + "EventCode": "0x4D010", + "EventName": "PM_PMC1_SAVED", + "BriefDescription": "PMC1 Rewind Value saved" }, {, - "EventCode": "0x3C046", - "EventName": "PM_DATA_FROM_L2.1_SHR", - "BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a demand load", - "PublicDescription": "" + "EventCode": "0x200FE", + "EventName": "PM_DATA_FROM_L2MISS", + "BriefDescription": "Demand LD - L2 Miss (not L2 hit)" }, {, - "EventCode": "0x34042", - "EventName": "PM_INST_FROM_L3_DISP_CONFLICT", - "BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to an instruction fetch (not prefetch)", - "PublicDescription": "" + "EventCode": "0x2D14A", + "EventName": "PM_MRK_DATA_FROM_RL2L3_MOD_CYC", + "BriefDescription": "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load" }, {, - "EventCode": "0x34046", - "EventName": "PM_INST_FROM_L2.1_SHR", - "BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the same chip due to an instruction fetch (not prefetch)", - "PublicDescription": "" + "EventCode": "0x10028", + "EventName": "PM_STALL_END_ICT_EMPTY", + "BriefDescription": "The number a times the core transitioned from a stall to ICT-empty for this thread" }, {, - "EventCode": "0x3504A", - "EventName": "PM_IPTEG_FROM_RMEM", - "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a instruction side request", - "PublicDescription": "" + "EventCode": "0x2504C", + "EventName": "PM_IPTEG_FROM_MEMORY", + "BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a instruction side request" }, {, - "EventCode": "0x3E048", - "EventName": "PM_DPTEG_FROM_DL2L3_SHR", - "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", - "PublicDescription": "" + "EventCode": "0x4504A", + "EventName": "PM_IPTEG_FROM_OFF_CHIP_CACHE", + "BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a instruction side request" }, {, - "EventCode": "0x3E04C", - "EventName": "PM_DPTEG_FROM_DL4", - "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", - "PublicDescription": "" + "EventCode": "0x1404E", + "EventName": "PM_INST_FROM_L2MISS", + "BriefDescription": "The processor's Instruction cache was reloaded from a location other than the local core's L2 due to an instruction fetch (not prefetch)" }, {, - "EventCode": "0x3C05A", - "EventName": "PM_CMPLU_STALL_VDPLONG", - "BriefDescription": "Finish stall because the NTF instruction was a scalar multi-cycle instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Qualified by NOT vector AND multicycle", - "PublicDescription": "" + "EventCode": "0x34042", + "EventName": "PM_INST_FROM_L3_DISP_CONFLICT", + "BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to an instruction fetch (not prefetch)" }, {, - "EventCode": "0x3C05C", - "EventName": "PM_CMPLU_STALL_VFXU", - "BriefDescription": "Finish stall due to a vector fixed point instruction in the execution pipeline. These instructions get routed to the ALU, ALU2, and DIV pipes", - "PublicDescription": "" + "EventCode": "0x4E048", + "EventName": "PM_DPTEG_FROM_DL2L3_MOD", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included" }, {, - "EventCode": "0x30066", - "EventName": "PM_LSU_FIN", - "BriefDescription": "LSU Finished a PPC instruction (up to 4 per cycle)", - "PublicDescription": "" + "EventCode": "0x200F0", + "EventName": "PM_ST_CMPL", + "BriefDescription": "Stores completed from S2Q (2nd-level store queue)." }, {, - "EventCode": "0x300F0", - "EventName": "PM_ST_MISS_L1", - "BriefDescription": "Store Missed L1", - "PublicDescription": "" + "EventCode": "0x4E05C", + "EventName": "PM_LSU_REJECT_LHS", + "BriefDescription": "LSU Reject due to LHS (up to 4 per cycle)" }, {, - "EventCode": "0x4D010", - "EventName": "PM_PMC1_SAVED", - "BriefDescription": "PMC1 Rewind Value saved", - "PublicDescription": "" + "EventCode": "0x14044", + "EventName": "PM_INST_FROM_L3_NO_CONFLICT", + "BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 without conflict due to an instruction fetch (not prefetch)" }, {, - "EventCode": "0x40132", - "EventName": "PM_MRK_LSU_FIN", - "BriefDescription": "lsu marked instr PPC finish", - "PublicDescription": "" + "EventCode": "0x3E04C", + "EventName": "PM_DPTEG_FROM_DL4", + "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included" }, {, - "EventCode": "0x4C046", - "EventName": "PM_DATA_FROM_L2.1_MOD", - "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a demand load", - "PublicDescription": "" + "EventCode": "0x1F15E", + "EventName": "PM_MRK_PROBE_NOP_CMPL", + "BriefDescription": "Marked probeNops completed" }, {, - "EventCode": "0x44042", - "EventName": "PM_INST_FROM_L3", - "BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 due to an instruction fetch (not prefetch)", - "PublicDescription": "" + "EventCode": "0x20018", + "EventName": "PM_ST_FWD", + "BriefDescription": "Store forwards that finished" }, {, - "EventCode": "0x4504A", - "EventName": "PM_IPTEG_FROM_OFF_CHIP_CACHE", - "BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a instruction side request", - "PublicDescription": "" + "EventCode": "0x1D142", + "EventName": "PM_MRK_DATA_FROM_L31_ECO_SHR_CYC", + "BriefDescription": "Duration in cycles to reload with Shared (S) data from another core's ECO L3 on the same chip due to a marked load" }, {, - "EventCode": "0x4E048", - "EventName": "PM_DPTEG_FROM_DL2L3_MOD", - "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", - "PublicDescription": "" + "EventCode": "0x24042", + "EventName": "PM_INST_FROM_L3_MEPF", + "BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to an instruction fetch (not prefetch)" }, {, - "EventCode": "0x4E04C", - "EventName": "PM_DPTEG_FROM_DMEM", - "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", - "PublicDescription": "" + "EventCode": "0x25046", + "EventName": "PM_IPTEG_FROM_RL2L3_MOD", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request" }, {, - "EventCode": "0x4405C", - "EventName": "PM_CMPLU_STALL_VDP", - "BriefDescription": "Finish stall because the NTF instruction was a vector instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Not qualified multicycle. Qualified by vector", - "PublicDescription": "" + "EventCode": "0x3504A", + "EventName": "PM_IPTEG_FROM_RMEM", + "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a instruction side request" }, {, - "EventCode": "0x4D05C", - "EventName": "PM_DP_QP_FLOP_CMPL", - "BriefDescription": "Double-Precion or Quad-Precision instruction completed", - "PublicDescription": "" + "EventCode": "0x3C05A", + "EventName": "PM_CMPLU_STALL_VDPLONG", + "BriefDescription": "Finish stall because the NTF instruction was a scalar multi-cycle instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Qualified by NOT vector AND multicycle" }, {, - "EventCode": "0x4E05C", - "EventName": "PM_LSU_REJECT_LHS", - "BriefDescription": "LSU Reject due to LHS (up to 4 per cycle)", - "PublicDescription": "" + "EventCode": "0x2E01C", + "EventName": "PM_CMPLU_STALL_TLBIE", + "BriefDescription": "Finish stall because the NTF instruction was a tlbie waiting for response from L2" } -] +]
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