diff options
Diffstat (limited to 'drivers/pinctrl/sh-pfc/pfc-r8a77470.c')
-rw-r--r-- | drivers/pinctrl/sh-pfc/pfc-r8a77470.c | 111 |
1 files changed, 66 insertions, 45 deletions
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c index 76f7c73b85b6..c05dc1490486 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c @@ -2746,7 +2746,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_5_0_FN, FN_IP13_31_28, )) }, { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { + GROUP(4, 4, 4, 4, 4, 4, 4, 4), + GROUP( /* IP0_31_28 [4] */ FN_SD0_WP, FN_IRQ7, FN_CAN0_TX_A, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -2770,10 +2771,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, 0, 0, /* IP0_3_0 [4] */ FN_SD0_CLK, 0, 0, FN_SSI_SCK1_C, FN_RX3_C, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, } + 0, 0, 0, 0, 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { + GROUP(4, 4, 4, 4, 4, 4, 4, 4), + GROUP( /* IP1_31_28 [4] */ FN_D5, FN_HRX2, FN_SCL1_B, FN_PWM2_C, FN_TCLK2_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -2797,10 +2799,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, 0, 0, /* IP1_3_0 [4] */ FN_MMC0_D4, FN_SD1_CD, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, } + 0, 0, 0, 0, 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { + GROUP(4, 4, 4, 4, 4, 4, 4, 4), + GROUP( /* IP2_31_28 [4] */ FN_D13, FN_MSIOF2_SYNC_A, 0, FN_RX4_C, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -2824,10 +2827,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP2_3_0 [4] */ FN_D6, FN_HTX2, FN_SDA1_B, FN_PWM4_C, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, } + 0, 0, 0, 0, 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { + GROUP(4, 4, 4, 4, 4, 4, 4, 4), + GROUP( /* IP3_31_28 [4] */ FN_QSPI0_SSL, FN_WE1_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -2852,10 +2856,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP3_3_0 [4] */ FN_D14, FN_MSIOF2_SS1, 0, FN_TX4_C, FN_CAN1_RX_B, 0, FN_AVB_AVTP_CAPTURE_A, - 0, 0, 0, 0, 0, 0, 0, 0, 0, } + 0, 0, 0, 0, 0, 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { + GROUP(4, 4, 4, 4, 4, 4, 4, 4), + GROUP( /* IP4_31_28 [4] */ FN_DU0_DR6, 0, FN_RX2_C, 0, 0, 0, FN_A6, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -2879,10 +2884,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, 0, 0, /* IP4_3_0 [4] */ FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK_A, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, } + 0, 0, 0, 0, 0, 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { + GROUP(4, 4, 4, 4, 4, 4, 4, 4), + GROUP( /* IP5_31_28 [4] */ FN_DU0_DG6, 0, FN_HRX1_C, 0, 0, 0, FN_A14, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -2906,10 +2912,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, 0, 0, /* IP5_3_0 [4] */ FN_DU0_DR7, 0, FN_TX2_C, 0, FN_PWM2_B, 0, FN_A7, 0, - 0, 0, 0, 0, 0, 0, 0, 0, } + 0, 0, 0, 0, 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { + GROUP(4, 4, 4, 4, 4, 4, 4, 4), + GROUP( /* IP6_31_28 [4] */ FN_DU0_DB6, 0, 0, 0, 0, 0, FN_A22, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -2933,10 +2940,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP6_3_0 [4] */ FN_DU0_DG7, 0, FN_HTX1_C, 0, FN_PWM6_B, 0, FN_A15, - 0, 0, 0, 0, 0, 0, 0, 0, 0, } + 0, 0, 0, 0, 0, 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { + GROUP(4, 4, 4, 4, 4, 4, 4, 4), + GROUP( /* IP7_31_28 [4] */ FN_DU0_DISP, 0, 0, 0, FN_CAN1_RX_C, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -2960,10 +2968,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, /* IP7_3_0 [4] */ FN_DU0_DB7, 0, 0, 0, 0, 0, FN_A23, 0, 0, - 0, 0, 0, 0, 0, 0, 0, } + 0, 0, 0, 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060060, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { + GROUP(4, 4, 4, 4, 4, 4, 4, 4), + GROUP( /* IP8_31_28 [4] */ FN_VI1_DATA5, 0, 0, 0, FN_AVB_RXD4, FN_ETH_LINK, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -2987,10 +2996,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, 0, /* IP8_3_0 [4] */ FN_DU0_CDE, 0, 0, 0, FN_CAN1_TX_C, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, } + 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060064, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { + GROUP(4, 4, 4, 4, 4, 4, 4, 4), + GROUP( /* IP9_31_28 [4] */ FN_VI1_DATA9, 0, 0, FN_SDA2_B, FN_AVB_TXD0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -3014,10 +3024,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, /* IP9_3_0 [4] */ FN_VI1_DATA6, 0, 0, 0, FN_AVB_RXD5, FN_ETH_TXD1, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, } + 0, 0, 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060068, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { + GROUP(4, 4, 4, 4, 4, 4, 4, 4), + GROUP( /* IP10_31_28 [4] */ FN_SCL1_A, FN_RX4_A, FN_PWM5_D, FN_DU1_DR0, 0, 0, FN_SSI_SCK6_B, FN_VI0_G0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -3042,10 +3053,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, 0, /* IP10_3_0 [4] */ FN_VI1_DATA10, 0, 0, FN_CAN0_RX_B, FN_AVB_TXD1, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, } + 0, 0, 0, 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR11", 0xE606006C, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { + GROUP(4, 4, 4, 4, 4, 4, 4, 4), + GROUP( /* IP11_31_28 [4] */ FN_HRX1_A, FN_SCL4_A, FN_PWM6_A, FN_DU1_DG0, FN_RX0_A, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -3073,10 +3085,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, 0, 0, /* IP11_3_0 [4] */ FN_SDA1_A, FN_TX4_A, 0, FN_DU1_DR1, 0, 0, FN_SSI_WS6_B, - FN_VI0_G1, 0, 0, 0, 0, 0, 0, 0, 0, } + FN_VI0_G1, 0, 0, 0, 0, 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060070, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { + GROUP(4, 4, 4, 4, 4, 4, 4, 4), + GROUP( /* IP12_31_28 [4] */ FN_SD2_DAT2, FN_RX2_A, 0, FN_DU1_DB0, FN_SSI_SDATA2_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -3100,10 +3113,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP12_3_0 [4] */ FN_HTX1_A, FN_SDA4_A, 0, FN_DU1_DG1, FN_TX0_A, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, } + 0, 0, 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060074, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { + GROUP(4, 4, 4, 4, 4, 4, 4, 4), + GROUP( /* IP13_31_28 [4] */ FN_SSI_SCK5_A, 0, 0, FN_DU1_DOTCLKOUT1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -3128,10 +3142,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP13_3_0 [4] */ FN_SD2_DAT3, FN_TX2_A, 0, FN_DU1_DB1, FN_SSI_WS9_B, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, } + 0, 0, 0, 0, 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060078, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { + GROUP(4, 4, 4, 4, 4, 4, 4, 4), + GROUP( /* IP14_31_28 [4] */ FN_SSI_SDATA7_A, 0, 0, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, FN_VI0_G5, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -3155,10 +3170,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP14_3_0 [4] */ FN_SSI_WS5_A, 0, FN_SCL3_C, FN_DU1_DOTCLKIN, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, } + 0, 0, 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR15", 0xE606007C, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { + GROUP(4, 4, 4, 4, 4, 4, 4, 4), + GROUP( /* IP15_31_28 [4] */ FN_SSI_WS4_A, 0, FN_AVB_PHY_INT, 0, 0, 0, FN_VI0_R5, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -3182,10 +3198,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_VI0_G7, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP15_3_0 [4] */ FN_SSI_SCK0129_A, FN_MSIOF1_RXD_A, FN_RX5_D, 0, 0, 0, - FN_VI0_G6, 0, 0, 0, 0, 0, 0, 0, 0, 0, } + FN_VI0_G6, 0, 0, 0, 0, 0, 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060080, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { + GROUP(4, 4, 4, 4, 4, 4, 4, 4), + GROUP( /* IP16_31_28 [4] */ FN_SSI_SDATA2_A, FN_HRTS1_N_B, 0, 0, 0, 0, FN_VI0_DATA4_VI0_B4, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -3210,10 +3227,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_DACK2, FN_VI0_CLK, FN_AVB_COL, 0, 0, 0, 0, 0, 0, 0, 0, /* IP16_3_0 [4] */ FN_SSI_SDATA4_A, 0, FN_AVB_CRS, 0, 0, 0, FN_VI0_R6, 0, 0, 0, - 0, 0, 0, 0, 0, 0, } + 0, 0, 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR17", 0xE6060084, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { + GROUP(4, 4, 4, 4, 4, 4, 4, 4), + GROUP( /* IP17_31_28 [4] */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP17_27_24 [4] */ @@ -3236,11 +3254,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_VI0_DATA6_VI0_B6, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP17_3_0 [4] */ FN_SSI_SCK9_A, FN_RX2_B, FN_SCL3_E, 0, 0, FN_EX_WAIT1, - FN_VI0_DATA5_VI0_B5, 0, 0, 0, 0, 0, 0, 0, 0, 0, } + FN_VI0_DATA5_VI0_B5, 0, 0, 0, 0, 0, 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xE60600C0, 32, - 1, 1, 1, 1, 1, 2, 1, 1, 2, 2, 2, 1, 3, 3, - 1, 2, 3, 3, 1) { + GROUP(1, 1, 1, 1, 1, 2, 1, 1, 2, 2, 2, 1, + 3, 3, 1, 2, 3, 3, 1), + GROUP( /* RESERVED [1] */ 0, 0, /* RESERVED [1] */ @@ -3283,11 +3302,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3, FN_SEL_I2C00_4, 0, 0, 0, /* SEL_AVB [1] */ - FN_SEL_AVB_0, FN_SEL_AVB_1, } + FN_SEL_AVB_0, FN_SEL_AVB_1, )) }, { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xE60600C4, 32, - 1, 3, 3, 2, 2, 1, 2, 2, - 2, 1, 1, 1, 1, 1, 2, 1, 1, 2, 2, 1) { + GROUP(1, 3, 3, 2, 2, 1, 2, 2, 2, 1, 1, 1, + 1, 1, 2, 1, 1, 2, 2, 1), + GROUP( /* SEL_SCIFCLK [1] */ FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1, /* SEL_SCIF5 [3] */ @@ -3329,11 +3349,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* SEL_HSCIF1 [2] */ FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, 0, /* SEL_HSCIF0 [1] */ - FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,} + FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, )) }, { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE60600C8, 32, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2) { + GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2, 2), + GROUP( /* RESERVED [1] */ 0, 0, /* RESERVED [1] */ @@ -3375,7 +3396,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* SEL_SSI1 [2] */ FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI1_2, FN_SEL_SSI1_3, /* SEL_SSI0 [2] */ - FN_SEL_SSI0_0, FN_SEL_SSI0_1, 0, 0, } + FN_SEL_SSI0_0, FN_SEL_SSI0_1, 0, 0, )) }, { }, }; |