diff options
Diffstat (limited to 'arch')
34 files changed, 1980 insertions, 1961 deletions
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile index 5fc202cdfdb6..995e7cc02bec 100644 --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile @@ -12,7 +12,8 @@ obj- := # Core -obj-$(CONFIG_ARCH_EXYNOS4) += common.o clock.o +obj-$(CONFIG_ARCH_EXYNOS) += common.o +obj-$(CONFIG_ARCH_EXYNOS4) += clock-exynos4.o obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c new file mode 100644 index 000000000000..060dde7d7ad6 --- /dev/null +++ b/arch/arm/mach-exynos/clock-exynos4.c @@ -0,0 +1,1568 @@ +/* + * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * EXYNOS4 - Clock support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/syscore_ops.h> + +#include <plat/cpu-freq.h> +#include <plat/clock.h> +#include <plat/cpu.h> +#include <plat/pll.h> +#include <plat/s5p-clock.h> +#include <plat/clock-clksrc.h> +#include <plat/pm.h> + +#include <mach/map.h> +#include <mach/regs-clock.h> +#include <mach/sysmmu.h> + +#include "common.h" +#include "clock-exynos4.h" + +#ifdef CONFIG_PM_SLEEP +static struct sleep_save exynos4_clock_save[] = { + SAVE_ITEM(EXYNOS4_CLKDIV_LEFTBUS), + SAVE_ITEM(EXYNOS4_CLKGATE_IP_LEFTBUS), + SAVE_ITEM(EXYNOS4_CLKDIV_RIGHTBUS), + SAVE_ITEM(EXYNOS4_CLKGATE_IP_RIGHTBUS), + SAVE_ITEM(EXYNOS4_CLKSRC_TOP0), + SAVE_ITEM(EXYNOS4_CLKSRC_TOP1), + SAVE_ITEM(EXYNOS4_CLKSRC_CAM), + SAVE_ITEM(EXYNOS4_CLKSRC_TV), + SAVE_ITEM(EXYNOS4_CLKSRC_MFC), + SAVE_ITEM(EXYNOS4_CLKSRC_G3D), + SAVE_ITEM(EXYNOS4_CLKSRC_LCD0), + SAVE_ITEM(EXYNOS4_CLKSRC_MAUDIO), + SAVE_ITEM(EXYNOS4_CLKSRC_FSYS), + SAVE_ITEM(EXYNOS4_CLKSRC_PERIL0), + SAVE_ITEM(EXYNOS4_CLKSRC_PERIL1), + SAVE_ITEM(EXYNOS4_CLKDIV_CAM), + SAVE_ITEM(EXYNOS4_CLKDIV_TV), + SAVE_ITEM(EXYNOS4_CLKDIV_MFC), + SAVE_ITEM(EXYNOS4_CLKDIV_G3D), + SAVE_ITEM(EXYNOS4_CLKDIV_LCD0), + SAVE_ITEM(EXYNOS4_CLKDIV_MAUDIO), + SAVE_ITEM(EXYNOS4_CLKDIV_FSYS0), + SAVE_ITEM(EXYNOS4_CLKDIV_FSYS1), + SAVE_ITEM(EXYNOS4_CLKDIV_FSYS2), + SAVE_ITEM(EXYNOS4_CLKDIV_FSYS3), + SAVE_ITEM(EXYNOS4_CLKDIV_PERIL0), + SAVE_ITEM(EXYNOS4_CLKDIV_PERIL1), + SAVE_ITEM(EXYNOS4_CLKDIV_PERIL2), + SAVE_ITEM(EXYNOS4_CLKDIV_PERIL3), + SAVE_ITEM(EXYNOS4_CLKDIV_PERIL4), + SAVE_ITEM(EXYNOS4_CLKDIV_PERIL5), + SAVE_ITEM(EXYNOS4_CLKDIV_TOP), + SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TOP), + SAVE_ITEM(EXYNOS4_CLKSRC_MASK_CAM), + SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TV), + SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD0), + SAVE_ITEM(EXYNOS4_CLKSRC_MASK_MAUDIO), + SAVE_ITEM(EXYNOS4_CLKSRC_MASK_FSYS), + SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL0), + SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL1), + SAVE_ITEM(EXYNOS4_CLKDIV2_RATIO), + SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCAM), + SAVE_ITEM(EXYNOS4_CLKGATE_IP_CAM), + SAVE_ITEM(EXYNOS4_CLKGATE_IP_TV), + SAVE_ITEM(EXYNOS4_CLKGATE_IP_MFC), + SAVE_ITEM(EXYNOS4_CLKGATE_IP_G3D), + SAVE_ITEM(EXYNOS4_CLKGATE_IP_LCD0), + SAVE_ITEM(EXYNOS4_CLKGATE_IP_FSYS), + SAVE_ITEM(EXYNOS4_CLKGATE_IP_GPS), + SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIL), + SAVE_ITEM(EXYNOS4_CLKGATE_BLOCK), + SAVE_ITEM(EXYNOS4_CLKSRC_MASK_DMC), + SAVE_ITEM(EXYNOS4_CLKSRC_DMC), + SAVE_ITEM(EXYNOS4_CLKDIV_DMC0), + SAVE_ITEM(EXYNOS4_CLKDIV_DMC1), + SAVE_ITEM(EXYNOS4_CLKGATE_IP_DMC), + SAVE_ITEM(EXYNOS4_CLKSRC_CPU), + SAVE_ITEM(EXYNOS4_CLKDIV_CPU), + SAVE_ITEM(EXYNOS4_CLKDIV_CPU + 0x4), + SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCPU), + SAVE_ITEM(EXYNOS4_CLKGATE_IP_CPU), +}; +#endif + +static struct clk exynos4_clk_sclk_hdmi27m = { + .name = "sclk_hdmi27m", + .rate = 27000000, +}; + +static struct clk exynos4_clk_sclk_hdmiphy = { + .name = "sclk_hdmiphy", +}; + +static struct clk exynos4_clk_sclk_usbphy0 = { + .name = "sclk_usbphy0", + .rate = 27000000, +}; + +static struct clk exynos4_clk_sclk_usbphy1 = { + .name = "sclk_usbphy1", +}; + +static struct clk dummy_apb_pclk = { + .name = "apb_pclk", + .id = -1, +}; + +static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TOP, clk, enable); +} + +static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_CAM, clk, enable); +} + +static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_LCD0, clk, enable); +} + +int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_FSYS, clk, enable); +} + +static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL0, clk, enable); +} + +static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL1, clk, enable); +} + +static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS4_CLKGATE_IP_MFC, clk, enable); +} + +static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TV, clk, enable); +} + +static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS4_CLKGATE_IP_CAM, clk, enable); +} + +static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable); +} + +static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable); +} + +static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS4_CLKGATE_IP_LCD0, clk, enable); +} + +int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS4210_CLKGATE_IP_LCD1, clk, enable); +} + +int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS4_CLKGATE_IP_FSYS, clk, enable); +} + +static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIL, clk, enable); +} + +static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable); +} + +static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable); +} + +static int exynos4_clk_dac_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable); +} + +/* Core list of CMU_CPU side */ + +static struct clksrc_clk exynos4_clk_mout_apll = { + .clk = { + .name = "mout_apll", + }, + .sources = &clk_src_apll, + .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 0, .size = 1 }, +}; + +static struct clksrc_clk exynos4_clk_sclk_apll = { + .clk = { + .name = "sclk_apll", + .parent = &exynos4_clk_mout_apll.clk, + }, + .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 24, .size = 3 }, +}; + +static struct clksrc_clk exynos4_clk_mout_epll = { + .clk = { + .name = "mout_epll", + }, + .sources = &clk_src_epll, + .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 4, .size = 1 }, +}; + +struct clksrc_clk exynos4_clk_mout_mpll = { + .clk = { + .name = "mout_mpll", + }, + .sources = &clk_src_mpll, + + /* reg_src will be added in each SoCs' clock */ +}; + +static struct clk *exynos4_clkset_moutcore_list[] = { + [0] = &exynos4_clk_mout_apll.clk, + [1] = &exynos4_clk_mout_mpll.clk, +}; + +static struct clksrc_sources exynos4_clkset_moutcore = { + .sources = exynos4_clkset_moutcore_list, + .nr_sources = ARRAY_SIZE(exynos4_clkset_moutcore_list), +}; + +static struct clksrc_clk exynos4_clk_moutcore = { + .clk = { + .name = "moutcore", + }, + .sources = &exynos4_clkset_moutcore, + .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 16, .size = 1 }, +}; + +static struct clksrc_clk exynos4_clk_coreclk = { + .clk = { + .name = "core_clk", + .parent = &exynos4_clk_moutcore.clk, + }, + .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 0, .size = 3 }, +}; + +static struct clksrc_clk exynos4_clk_armclk = { + .clk = { + .name = "armclk", + .parent = &exynos4_clk_coreclk.clk, + }, +}; + +static struct clksrc_clk exynos4_clk_aclk_corem0 = { + .clk = { + .name = "aclk_corem0", + .parent = &exynos4_clk_coreclk.clk, + }, + .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 }, +}; + +static struct clksrc_clk exynos4_clk_aclk_cores = { + .clk = { + .name = "aclk_cores", + .parent = &exynos4_clk_coreclk.clk, + }, + .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 }, +}; + +static struct clksrc_clk exynos4_clk_aclk_corem1 = { + .clk = { + .name = "aclk_corem1", + .parent = &exynos4_clk_coreclk.clk, + }, + .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 8, .size = 3 }, +}; + +static struct clksrc_clk exynos4_clk_periphclk = { + .clk = { + .name = "periphclk", + .parent = &exynos4_clk_coreclk.clk, + }, + .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 12, .size = 3 }, +}; + +/* Core list of CMU_CORE side */ + +static struct clk *exynos4_clkset_corebus_list[] = { + [0] = &exynos4_clk_mout_mpll.clk, + [1] = &exynos4_clk_sclk_apll.clk, +}; + +struct clksrc_sources exynos4_clkset_mout_corebus = { + .sources = exynos4_clkset_corebus_list, + .nr_sources = ARRAY_SIZE(exynos4_clkset_corebus_list), +}; + +static struct clksrc_clk exynos4_clk_mout_corebus = { + .clk = { + .name = "mout_corebus", + }, + .sources = &exynos4_clkset_mout_corebus, + .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 4, .size = 1 }, +}; + +static struct clksrc_clk exynos4_clk_sclk_dmc = { + .clk = { + .name = "sclk_dmc", + .parent = &exynos4_clk_mout_corebus.clk, + }, + .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 12, .size = 3 }, +}; + +static struct clksrc_clk exynos4_clk_aclk_cored = { + .clk = { + .name = "aclk_cored", + .parent = &exynos4_clk_sclk_dmc.clk, + }, + .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 16, .size = 3 }, +}; + +static struct clksrc_clk exynos4_clk_aclk_corep = { + .clk = { + .name = "aclk_corep", + .parent = &exynos4_clk_aclk_cored.clk, + }, + .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 20, .size = 3 }, +}; + +static struct clksrc_clk exynos4_clk_aclk_acp = { + .clk = { + .name = "aclk_acp", + .parent = &exynos4_clk_mout_corebus.clk, + }, + .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 0, .size = 3 }, +}; + +static struct clksrc_clk exynos4_clk_pclk_acp = { + .clk = { + .name = "pclk_acp", + .parent = &exynos4_clk_aclk_acp.clk, + }, + .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 4, .size = 3 }, +}; + +/* Core list of CMU_TOP side */ + +struct clk *exynos4_clkset_aclk_top_list[] = { + [0] = &exynos4_clk_mout_mpll.clk, + [1] = &exynos4_clk_sclk_apll.clk, +}; + +static struct clksrc_sources exynos4_clkset_aclk = { + .sources = exynos4_clkset_aclk_top_list, + .nr_sources = ARRAY_SIZE(exynos4_clkset_aclk_top_list), +}; + +static struct clksrc_clk exynos4_clk_aclk_200 = { + .clk = { + .name = "aclk_200", + }, + .sources = &exynos4_clkset_aclk, + .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 12, .size = 1 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 0, .size = 3 }, +}; + +static struct clksrc_clk exynos4_clk_aclk_100 = { + .clk = { + .name = "aclk_100", + }, + .sources = &exynos4_clkset_aclk, + .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 16, .size = 1 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 4, .size = 4 }, +}; + +static struct clksrc_clk exynos4_clk_aclk_160 = { + .clk = { + .name = "aclk_160", + }, + .sources = &exynos4_clkset_aclk, + .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 20, .size = 1 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 8, .size = 3 }, +}; + +struct clksrc_clk exynos4_clk_aclk_133 = { + .clk = { + .name = "aclk_133", + }, + .sources = &exynos4_clkset_aclk, + .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 24, .size = 1 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 12, .size = 3 }, +}; + +static struct clk *exynos4_clkset_vpllsrc_list[] = { + [0] = &clk_fin_vpll, + [1] = &exynos4_clk_sclk_hdmi27m, +}; + +static struct clksrc_sources exynos4_clkset_vpllsrc = { + .sources = exynos4_clkset_vpllsrc_list, + .nr_sources = ARRAY_SIZE(exynos4_clkset_vpllsrc_list), +}; + +static struct clksrc_clk exynos4_clk_vpllsrc = { + .clk = { + .name = "vpll_src", + .enable = exynos4_clksrc_mask_top_ctrl, + .ctrlbit = (1 << 0), + }, + .sources = &exynos4_clkset_vpllsrc, + .reg_src = { .reg = EXYNOS4_CLKSRC_TOP1, .shift = 0, .size = 1 }, +}; + +static struct clk *exynos4_clkset_sclk_vpll_list[] = { + [0] = &exynos4_clk_vpllsrc.clk, + [1] = &clk_fout_vpll, +}; + +static struct clksrc_sources exynos4_clkset_sclk_vpll = { + .sources = exynos4_clkset_sclk_vpll_list, + .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_vpll_list), +}; + +static struct clksrc_clk exynos4_clk_sclk_vpll = { + .clk = { + .name = "sclk_vpll", + }, + .sources = &exynos4_clkset_sclk_vpll, + .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 8, .size = 1 }, +}; + +static struct clk exynos4_init_clocks_off[] = { + { + .name = "timers", + .parent = &exynos4_clk_aclk_100.clk, + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1<<24), + }, { + .name = "csis", + .devname = "s5p-mipi-csis.0", + .enable = exynos4_clk_ip_cam_ctrl, + .ctrlbit = (1 << 4), + }, { + .name = "csis", + .devname = "s5p-mipi-csis.1", + .enable = exynos4_clk_ip_cam_ctrl, + .ctrlbit = (1 << 5), + }, { + .name = "jpeg", + .id = 0, + .enable = exynos4_clk_ip_cam_ctrl, + .ctrlbit = (1 << 6), + }, { + .name = "fimc", + .devname = "exynos4-fimc.0", + .enable = exynos4_clk_ip_cam_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "fimc", + .devname = "exynos4-fimc.1", + .enable = exynos4_clk_ip_cam_ctrl, + .ctrlbit = (1 << 1), + }, { + .name = "fimc", + .devname = "exynos4-fimc.2", + .enable = exynos4_clk_ip_cam_ctrl, + .ctrlbit = (1 << 2), + }, { + .name = "fimc", + .devname = "exynos4-fimc.3", + .enable = exynos4_clk_ip_cam_ctrl, + .ctrlbit = (1 << 3), + }, { + .name = "fimd", + .devname = "exynos4-fb.0", + .enable = exynos4_clk_ip_lcd0_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "hsmmc", + .devname = "s3c-sdhci.0", + .parent = &exynos4_clk_aclk_133.clk, + .enable = exynos4_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 5), + }, { + .name = "hsmmc", + .devname = "s3c-sdhci.1", + .parent = &exynos4_clk_aclk_133.clk, + .enable = exynos4_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 6), + }, { + .name = "hsmmc", + .devname = "s3c-sdhci.2", + .parent = &exynos4_clk_aclk_133.clk, + .enable = exynos4_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 7), + }, { + .name = "hsmmc", + .devname = "s3c-sdhci.3", + .parent = &exynos4_clk_aclk_133.clk, + .enable = exynos4_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 8), + }, { + .name = "dwmmc", + .parent = &exynos4_clk_aclk_133.clk, + .enable = exynos4_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 9), + }, { + .name = "dac", + .devname = "s5p-sdo", + .enable = exynos4_clk_ip_tv_ctrl, + .ctrlbit = (1 << 2), + }, { + .name = "mixer", + .devname = "s5p-mixer", + .enable = exynos4_clk_ip_tv_ctrl, + .ctrlbit = (1 << 1), + }, { + .name = "vp", + .devname = "s5p-mixer", + .enable = exynos4_clk_ip_tv_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "hdmi", + .devname = "exynos4-hdmi", + .enable = exynos4_clk_ip_tv_ctrl, + .ctrlbit = (1 << 3), + }, { + .name = "hdmiphy", + .devname = "exynos4-hdmi", + .enable = exynos4_clk_hdmiphy_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "dacphy", + .devname = "s5p-sdo", + .enable = exynos4_clk_dac_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "adc", + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 15), + }, { + .name = "keypad", + .enable = exynos4_clk_ip_perir_ctrl, + .ctrlbit = (1 << 16), + }, { + .name = "rtc", + .enable = exynos4_clk_ip_perir_ctrl, + .ctrlbit = (1 << 15), + }, { + .name = "watchdog", + .parent = &exynos4_clk_aclk_100.clk, + .enable = exynos4_clk_ip_perir_ctrl, + .ctrlbit = (1 << 14), + }, { + .name = "usbhost", + .enable = exynos4_clk_ip_fsys_ctrl , + .ctrlbit = (1 << 12), + }, { + .name = "otg", + .enable = exynos4_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 13), + }, { + .name = "spi", + .devname = "s3c64xx-spi.0", + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 16), + }, { + .name = "spi", + .devname = "s3c64xx-spi.1", + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 17), + }, { + .name = "spi", + .devname = "s3c64xx-spi.2", + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 18), + }, { + .name = "iis", + .devname = "samsung-i2s.0", + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 19), + }, { + .name = "iis", + .devname = "samsung-i2s.1", + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 20), + }, { + .name = "iis", + .devname = "samsung-i2s.2", + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 21), + }, { + .name = "ac97", + .devname = "samsung-ac97", + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 27), + }, { + .name = "fimg2d", + .enable = exynos4_clk_ip_image_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "mfc", + .devname = "s5p-mfc", + .enable = exynos4_clk_ip_mfc_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "i2c", + .devname = "s3c2440-i2c.0", + .parent = &exynos4_clk_aclk_100.clk, + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 6), + }, { + .name = "i2c", + .devname = "s3c2440-i2c.1", + .parent = &exynos4_clk_aclk_100.clk, + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 7), + }, { + .name = "i2c", + .devname = "s3c2440-i2c.2", + .parent = &exynos4_clk_aclk_100.clk, + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 8), + }, { + .name = "i2c", + .devname = "s3c2440-i2c.3", + .parent = &exynos4_clk_aclk_100.clk, + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 9), + }, { + .name = "i2c", + .devname = "s3c2440-i2c.4", + .parent = &exynos4_clk_aclk_100.clk, + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 10), + }, { + .name = "i2c", + .devname = "s3c2440-i2c.5", + .parent = &exynos4_clk_aclk_100.clk, + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 11), + }, { + .name = "i2c", + .devname = "s3c2440-i2c.6", + .parent = &exynos4_clk_aclk_100.clk, + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 12), + }, { + .name = "i2c", + .devname = "s3c2440-i2c.7", + .parent = &exynos4_clk_aclk_100.clk, + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 13), + }, { + .name = "i2c", + .devname = "s3c2440-hdmiphy-i2c", + .parent = &exynos4_clk_aclk_100.clk, + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 14), + }, { + .name = "SYSMMU_MDMA", + .enable = exynos4_clk_ip_image_ctrl, + .ctrlbit = (1 << 5), + }, { + .name = "SYSMMU_FIMC0", + .enable = exynos4_clk_ip_cam_ctrl, + .ctrlbit = (1 << 7), + }, { + .name = "SYSMMU_FIMC1", + .enable = exynos4_clk_ip_cam_ctrl, + .ctrlbit = (1 << 8), + }, { + .name = "SYSMMU_FIMC2", + .enable = exynos4_clk_ip_cam_ctrl, + .ctrlbit = (1 << 9), + }, { + .name = "SYSMMU_FIMC3", + .enable = exynos4_clk_ip_cam_ctrl, + .ctrlbit = (1 << 10), + }, { + .name = "SYSMMU_JPEG", + .enable = exynos4_clk_ip_cam_ctrl, + .ctrlbit = (1 << 11), + }, { + .name = "SYSMMU_FIMD0", + .enable = exynos4_clk_ip_lcd0_ctrl, + .ctrlbit = (1 << 4), + }, { + .name = "SYSMMU_FIMD1", + .enable = exynos4_clk_ip_lcd1_ctrl, + .ctrlbit = (1 << 4), + }, { + .name = "SYSMMU_PCIe", + .enable = exynos4_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 18), + }, { + .name = "SYSMMU_G2D", + .enable = exynos4_clk_ip_image_ctrl, + .ctrlbit = (1 << 3), + }, { + .name = "SYSMMU_ROTATOR", + .enable = exynos4_clk_ip_image_ctrl, + .ctrlbit = (1 << 4), + }, { + .name = "SYSMMU_TV", + .enable = exynos4_clk_ip_tv_ctrl, + .ctrlbit = (1 << 4), + }, { + .name = "SYSMMU_MFC_L", + .enable = exynos4_clk_ip_mfc_ctrl, + .ctrlbit = (1 << 1), + }, { + .name = "SYSMMU_MFC_R", + .enable = exynos4_clk_ip_mfc_ctrl, + .ctrlbit = (1 << 2), + } +}; + +static struct clk exynos4_init_clocks_on[] = { + { + .name = "uart", + .devname = "s5pv210-uart.0", + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "uart", + .devname = "s5pv210-uart.1", + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 1), + }, { + .name = "uart", + .devname = "s5pv210-uart.2", + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 2), + }, { + .name = "uart", + .devname = "s5pv210-uart.3", + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 3), + }, { + .name = "uart", + .devname = "s5pv210-uart.4", + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 4), + }, { + .name = "uart", + .devname = "s5pv210-uart.5", + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 5), + } +}; + +static struct clk exynos4_clk_pdma0 = { + .name = "dma", + .devname = "dma-pl330.0", + .enable = exynos4_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 0), +}; + +static struct clk exynos4_clk_pdma1 = { + .name = "dma", + .devname = "dma-pl330.1", + .enable = exynos4_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 1), +}; + +struct clk *exynos4_clkset_group_list[] = { + [0] = &clk_ext_xtal_mux, + [1] = &clk_xusbxti, + [2] = &exynos4_clk_sclk_hdmi27m, + [3] = &exynos4_clk_sclk_usbphy0, + [4] = &exynos4_clk_sclk_usbphy1, + [5] = &exynos4_clk_sclk_hdmiphy, + [6] = &exynos4_clk_mout_mpll.clk, + [7] = &exynos4_clk_mout_epll.clk, + [8] = &exynos4_clk_sclk_vpll.clk, +}; + +struct clksrc_sources exynos4_clkset_group = { + .sources = exynos4_clkset_group_list, + .nr_sources = ARRAY_SIZE(exynos4_clkset_group_list), +}; + +static struct clk *exynos4_clkset_mout_g2d0_list[] = { + [0] = &exynos4_clk_mout_mpll.clk, + [1] = &exynos4_clk_sclk_apll.clk, +}; + +static struct clksrc_sources exynos4_clkset_mout_g2d0 = { + .sources = exynos4_clkset_mout_g2d0_list, + .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d0_list), +}; + +static struct clksrc_clk exynos4_clk_mout_g2d0 = { + .clk = { + .name = "mout_g2d0", + }, + .sources = &exynos4_clkset_mout_g2d0, + .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 }, +}; + +static struct clk *exynos4_clkset_mout_g2d1_list[] = { + [0] = &exynos4_clk_mout_epll.clk, + [1] = &exynos4_clk_sclk_vpll.clk, +}; + +static struct clksrc_sources exynos4_clkset_mout_g2d1 = { + .sources = exynos4_clkset_mout_g2d1_list, + .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d1_list), +}; + +static struct clksrc_clk exynos4_clk_mout_g2d1 = { + .clk = { + .name = "mout_g2d1", + }, + .sources = &exynos4_clkset_mout_g2d1, + .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 }, +}; + +static struct clk *exynos4_clkset_mout_g2d_list[] = { + [0] = &exynos4_clk_mout_g2d0.clk, + [1] = &exynos4_clk_mout_g2d1.clk, +}; + +static struct clksrc_sources exynos4_clkset_mout_g2d = { + .sources = exynos4_clkset_mout_g2d_list, + .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d_list), +}; + +static struct clk *exynos4_clkset_mout_mfc0_list[] = { + [0] = &exynos4_clk_mout_mpll.clk, + [1] = &exynos4_clk_sclk_apll.clk, +}; + +static struct clksrc_sources exynos4_clkset_mout_mfc0 = { + .sources = exynos4_clkset_mout_mfc0_list, + .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc0_list), +}; + +static struct clksrc_clk exynos4_clk_mout_mfc0 = { + .clk = { + .name = "mout_mfc0", + }, + .sources = &exynos4_clkset_mout_mfc0, + .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 0, .size = 1 }, +}; + +static struct clk *exynos4_clkset_mout_mfc1_list[] = { + [0] = &exynos4_clk_mout_epll.clk, + [1] = &exynos4_clk_sclk_vpll.clk, +}; + +static struct clksrc_sources exynos4_clkset_mout_mfc1 = { + .sources = exynos4_clkset_mout_mfc1_list, + .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc1_list), +}; + +static struct clksrc_clk exynos4_clk_mout_mfc1 = { + .clk = { + .name = "mout_mfc1", + }, + .sources = &exynos4_clkset_mout_mfc1, + .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 4, .size = 1 }, +}; + +static struct clk *exynos4_clkset_mout_mfc_list[] = { + [0] = &exynos4_clk_mout_mfc0.clk, + [1] = &exynos4_clk_mout_mfc1.clk, +}; + +static struct clksrc_sources exynos4_clkset_mout_mfc = { + .sources = exynos4_clkset_mout_mfc_list, + .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc_list), +}; + +static struct clk *exynos4_clkset_sclk_dac_list[] = { + [0] = &exynos4_clk_sclk_vpll.clk, + [1] = &exynos4_clk_sclk_hdmiphy, +}; + +static struct clksrc_sources exynos4_clkset_sclk_dac = { + .sources = exynos4_clkset_sclk_dac_list, + .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_dac_list), +}; + +static struct clksrc_clk exynos4_clk_sclk_dac = { + .clk = { + .name = "sclk_dac", + .enable = exynos4_clksrc_mask_tv_ctrl, + .ctrlbit = (1 << 8), + }, + .sources = &exynos4_clkset_sclk_dac, + .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 8, .size = 1 }, +}; + +static struct clksrc_clk exynos4_clk_sclk_pixel = { + .clk = { + .name = "sclk_pixel", + .parent = &exynos4_clk_sclk_vpll.clk, + }, + .reg_div = { .reg = EXYNOS4_CLKDIV_TV, .shift = 0, .size = 4 }, +}; + +static struct clk *exynos4_clkset_sclk_hdmi_list[] = { + [0] = &exynos4_clk_sclk_pixel.clk, + [1] = &exynos4_clk_sclk_hdmiphy, +}; + +static struct clksrc_sources exynos4_clkset_sclk_hdmi = { + .sources = exynos4_clkset_sclk_hdmi_list, + .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_hdmi_list), +}; + +static struct clksrc_clk exynos4_clk_sclk_hdmi = { + .clk = { + .name = "sclk_hdmi", + .enable = exynos4_clksrc_mask_tv_ctrl, + .ctrlbit = (1 << 0), + }, + .sources = &exynos4_clkset_sclk_hdmi, + .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 0, .size = 1 }, +}; + +static struct clk *exynos4_clkset_sclk_mixer_list[] = { + [0] = &exynos4_clk_sclk_dac.clk, + [1] = &exynos4_clk_sclk_hdmi.clk, +}; + +static struct clksrc_sources exynos4_clkset_sclk_mixer = { + .sources = exynos4_clkset_sclk_mixer_list, + .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_mixer_list), +}; + +static struct clksrc_clk exynos4_clk_sclk_mixer = { + .clk = { + .name = "sclk_mixer", + .enable = exynos4_clksrc_mask_tv_ctrl, + .ctrlbit = (1 << 4), + }, + .sources = &exynos4_clkset_sclk_mixer, + .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 4, .size = 1 }, +}; + +static struct clksrc_clk *exynos4_sclk_tv[] = { + &exynos4_clk_sclk_dac, + &exynos4_clk_sclk_pixel, + &exynos4_clk_sclk_hdmi, + &exynos4_clk_sclk_mixer, +}; + +static struct clksrc_clk exynos4_clk_dout_mmc0 = { + .clk = { + .name = "dout_mmc0", + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 0, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk exynos4_clk_dout_mmc1 = { + .clk = { + .name = "dout_mmc1", + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 4, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 16, .size = 4 }, +}; + +static struct clksrc_clk exynos4_clk_dout_mmc2 = { + .clk = { + .name = "dout_mmc2", + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 8, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk exynos4_clk_dout_mmc3 = { + .clk = { + .name = "dout_mmc3", + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 12, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 16, .size = 4 }, +}; + +static struct clksrc_clk exynos4_clk_dout_mmc4 = { + .clk = { + .name = "dout_mmc4", + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 16, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk exynos4_clksrcs[] = { + { + .clk = { + .name = "sclk_pwm", + .enable = exynos4_clksrc_mask_peril0_ctrl, + .ctrlbit = (1 << 24), + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 24, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL3, .shift = 0, .size = 4 }, + }, { + .clk = { + .name = "sclk_csis", + .devname = "s5p-mipi-csis.0", + .enable = exynos4_clksrc_mask_cam_ctrl, + .ctrlbit = (1 << 24), + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 24, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 24, .size = 4 }, + }, { + .clk = { + .name = "sclk_csis", + .devname = "s5p-mipi-csis.1", + .enable = exynos4_clksrc_mask_cam_ctrl, + .ctrlbit = (1 << 28), + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 28, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 28, .size = 4 }, + }, { + .clk = { + .name = "sclk_cam0", + .enable = exynos4_clksrc_mask_cam_ctrl, + .ctrlbit = (1 << 16), + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 16, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 16, .size = 4 }, + }, { + .clk = { + .name = "sclk_cam1", + .enable = exynos4_clksrc_mask_cam_ctrl, + .ctrlbit = (1 << 20), + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 20, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 20, .size = 4 }, + }, { + .clk = { + .name = "sclk_fimc", + .devname = "exynos4-fimc.0", + .enable = exynos4_clksrc_mask_cam_ctrl, + .ctrlbit = (1 << 0), + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 0, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 0, .size = 4 }, + }, { + .clk = { + .name = "sclk_fimc", + .devname = "exynos4-fimc.1", + .enable = exynos4_clksrc_mask_cam_ctrl, + .ctrlbit = (1 << 4), + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 4, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 4, .size = 4 }, + }, { + .clk = { + .name = "sclk_fimc", + .devname = "exynos4-fimc.2", + .enable = exynos4_clksrc_mask_cam_ctrl, + .ctrlbit = (1 << 8), + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 8, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 8, .size = 4 }, + }, { + .clk = { + .name = "sclk_fimc", + .devname = "exynos4-fimc.3", + .enable = exynos4_clksrc_mask_cam_ctrl, + .ctrlbit = (1 << 12), + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 12, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 12, .size = 4 }, + }, { + .clk = { + .name = "sclk_fimd", + .devname = "exynos4-fb.0", + .enable = exynos4_clksrc_mask_lcd0_ctrl, + .ctrlbit = (1 << 0), + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 0, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 }, + }, { + .clk = { + .name = "sclk_fimg2d", + }, + .sources = &exynos4_clkset_mout_g2d, + .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 }, + }, { + .clk = { + .name = "sclk_mfc", + .devname = "s5p-mfc", + }, + .sources = &exynos4_clkset_mout_mfc, + .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 8, .size = 1 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 }, + }, { + .clk = { + .name = "sclk_dwmmc", + .parent = &exynos4_clk_dout_mmc4.clk, + .enable = exynos4_clksrc_mask_fsys_ctrl, + .ctrlbit = (1 << 16), + }, + .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8 }, + } +}; + +static struct clksrc_clk exynos4_clk_sclk_uart0 = { + .clk = { + .name = "uclk1", + .devname = "exynos4210-uart.0", + .enable = exynos4_clksrc_mask_peril0_ctrl, + .ctrlbit = (1 << 0), + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 0, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk exynos4_clk_sclk_uart1 = { + .clk = { + .name = "uclk1", + .devname = "exynos4210-uart.1", + .enable = exynos4_clksrc_mask_peril0_ctrl, + .ctrlbit = (1 << 4), + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 4, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 4, .size = 4 }, +}; + +static struct clksrc_clk exynos4_clk_sclk_uart2 = { + .clk = { + .name = "uclk1", + .devname = "exynos4210-uart.2", + .enable = exynos4_clksrc_mask_peril0_ctrl, + .ctrlbit = (1 << 8), + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 8, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 8, .size = 4 }, +}; + +static struct clksrc_clk exynos4_clk_sclk_uart3 = { + .clk = { + .name = "uclk1", + .devname = "exynos4210-uart.3", + .enable = exynos4_clksrc_mask_peril0_ctrl, + .ctrlbit = (1 << 12), + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 12, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 12, .size = 4 }, +}; + +static struct clksrc_clk exynos4_clk_sclk_mmc0 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.0", + .parent = &exynos4_clk_dout_mmc0.clk, + .enable = exynos4_clksrc_mask_fsys_ctrl, + .ctrlbit = (1 << 0), + }, + .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 8, .size = 8 }, +}; + +static struct clksrc_clk exynos4_clk_sclk_mmc1 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.1", + .parent = &exynos4_clk_dout_mmc1.clk, + .enable = exynos4_clksrc_mask_fsys_ctrl, + .ctrlbit = (1 << 4), + }, + .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 24, .size = 8 }, +}; + +static struct clksrc_clk exynos4_clk_sclk_mmc2 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.2", + .parent = &exynos4_clk_dout_mmc2.clk, + .enable = exynos4_clksrc_mask_fsys_ctrl, + .ctrlbit = (1 << 8), + }, + .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 8, .size = 8 }, +}; + +static struct clksrc_clk exynos4_clk_sclk_mmc3 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.3", + .parent = &exynos4_clk_dout_mmc3.clk, + .enable = exynos4_clksrc_mask_fsys_ctrl, + .ctrlbit = (1 << 12), + }, + .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 }, +}; + +static struct clksrc_clk exynos4_clk_sclk_spi0 = { + .clk = { + .name = "sclk_spi", + .devname = "s3c64xx-spi.0", + .enable = exynos4_clksrc_mask_peril1_ctrl, + .ctrlbit = (1 << 16), + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk exynos4_clk_sclk_spi1 = { + .clk = { + .name = "sclk_spi", + .devname = "s3c64xx-spi.1", + .enable = exynos4_clksrc_mask_peril1_ctrl, + .ctrlbit = (1 << 20), + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 }, +}; + +static struct clksrc_clk exynos4_clk_sclk_spi2 = { + .clk = { + .name = "sclk_spi", + .devname = "s3c64xx-spi.2", + .enable = exynos4_clksrc_mask_peril1_ctrl, + .ctrlbit = (1 << 24), + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 }, +}; + +/* Clock initialization code */ +static struct clksrc_clk *exynos4_sysclks[] = { + &exynos4_clk_mout_apll, + &exynos4_clk_sclk_apll, + &exynos4_clk_mout_epll, + &exynos4_clk_mout_mpll, + &exynos4_clk_moutcore, + &exynos4_clk_coreclk, + &exynos4_clk_armclk, + &exynos4_clk_aclk_corem0, + &exynos4_clk_aclk_cores, + &exynos4_clk_aclk_corem1, + &exynos4_clk_periphclk, + &exynos4_clk_mout_corebus, + &exynos4_clk_sclk_dmc, + &exynos4_clk_aclk_cored, + &exynos4_clk_aclk_corep, + &exynos4_clk_aclk_acp, + &exynos4_clk_pclk_acp, + &exynos4_clk_vpllsrc, + &exynos4_clk_sclk_vpll, + &exynos4_clk_aclk_200, + &exynos4_clk_aclk_100, + &exynos4_clk_aclk_160, + &exynos4_clk_aclk_133, + &exynos4_clk_dout_mmc0, + &exynos4_clk_dout_mmc1, + &exynos4_clk_dout_mmc2, + &exynos4_clk_dout_mmc3, + &exynos4_clk_dout_mmc4, + &exynos4_clk_mout_mfc0, + &exynos4_clk_mout_mfc1, +}; + +static struct clk *exynos4_clk_cdev[] = { + &exynos4_clk_pdma0, + &exynos4_clk_pdma1, +}; + +static struct clksrc_clk *exynos4_clksrc_cdev[] = { + &exynos4_clk_sclk_uart0, + &exynos4_clk_sclk_uart1, + &exynos4_clk_sclk_uart2, + &exynos4_clk_sclk_uart3, + &exynos4_clk_sclk_mmc0, + &exynos4_clk_sclk_mmc1, + &exynos4_clk_sclk_mmc2, + &exynos4_clk_sclk_mmc3, + &exynos4_clk_sclk_spi0, + &exynos4_clk_sclk_spi1, + &exynos4_clk_sclk_spi2, + +}; + +static struct clk_lookup exynos4_clk_lookup[] = { + CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos4_clk_sclk_uart0.clk), + CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk), + CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk), + CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk), + CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk), + CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk), + CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk), + CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk), + CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0), + CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1), + CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk), + CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk), + CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk), +}; + +static int xtal_rate; + +static unsigned long exynos4_fout_apll_get_rate(struct clk *clk) +{ + if (soc_is_exynos4210()) + return s5p_get_pll45xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0), + pll_4508); + else if (soc_is_exynos4212() || soc_is_exynos4412()) + return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0)); + else + return 0; +} + +static struct clk_ops exynos4_fout_apll_ops = { + .get_rate = exynos4_fout_apll_get_rate, +}; + +static u32 exynos4_vpll_div[][8] = { + { 54000000, 3, 53, 3, 1024, 0, 17, 0 }, + { 108000000, 3, 53, 2, 1024, 0, 17, 0 }, +}; + +static unsigned long exynos4_vpll_get_rate(struct clk *clk) +{ + return clk->rate; +} + +static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned int vpll_con0, vpll_con1 = 0; + unsigned int i; + + /* Return if nothing changed */ + if (clk->rate == rate) + return 0; + + vpll_con0 = __raw_readl(EXYNOS4_VPLL_CON0); + vpll_con0 &= ~(0x1 << 27 | \ + PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \ + PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \ + PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT); + + vpll_con1 = __raw_readl(EXYNOS4_VPLL_CON1); + vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT | \ + PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \ + PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT); + + for (i = 0; i < ARRAY_SIZE(exynos4_vpll_div); i++) { + if (exynos4_vpll_div[i][0] == rate) { + vpll_con0 |= exynos4_vpll_div[i][1] << PLL46XX_PDIV_SHIFT; + vpll_con0 |= exynos4_vpll_div[i][2] << PLL46XX_MDIV_SHIFT; + vpll_con0 |= exynos4_vpll_div[i][3] << PLL46XX_SDIV_SHIFT; + vpll_con1 |= exynos4_vpll_div[i][4] << PLL46XX_KDIV_SHIFT; + vpll_con1 |= exynos4_vpll_div[i][5] << PLL46XX_MFR_SHIFT; + vpll_con1 |= exynos4_vpll_div[i][6] << PLL46XX_MRR_SHIFT; + vpll_con0 |= exynos4_vpll_div[i][7] << 27; + break; + } + } + + if (i == ARRAY_SIZE(exynos4_vpll_div)) { + printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n", + __func__); + return -EINVAL; + } + + __raw_writel(vpll_con0, EXYNOS4_VPLL_CON0); + __raw_writel(vpll_con1, EXYNOS4_VPLL_CON1); + + /* Wait for VPLL lock */ + while (!(__raw_readl(EXYNOS4_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT))) + continue; + + clk->rate = rate; + return 0; +} + +static struct clk_ops exynos4_vpll_ops = { + .get_rate = exynos4_vpll_get_rate, + .set_rate = exynos4_vpll_set_rate, +}; + +void __init_or_cpufreq exynos4_setup_clocks(void) +{ + struct clk *xtal_clk; + unsigned long apll = 0; + unsigned long mpll = 0; + unsigned long epll = 0; + unsigned long vpll = 0; + unsigned long vpllsrc; + unsigned long xtal; + unsigned long armclk; + unsigned long sclk_dmc; + unsigned long aclk_200; + unsigned long aclk_100; + unsigned long aclk_160; + unsigned long aclk_133; + unsigned int ptr; + + printk(KERN_DEBUG "%s: registering clocks\n", __func__); + + xtal_clk = clk_get(NULL, "xtal"); + BUG_ON(IS_ERR(xtal_clk)); + + xtal = clk_get_rate(xtal_clk); + + xtal_rate = xtal; + + clk_put(xtal_clk); + + printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); + + if (soc_is_exynos4210()) { + apll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_APLL_CON0), + pll_4508); + mpll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0), + pll_4508); + epll = s5p_get_pll46xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0), + __raw_readl(EXYNOS4_EPLL_CON1), pll_4600); + + vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk); + vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0), + __raw_readl(EXYNOS4_VPLL_CON1), pll_4650c); + } else if (soc_is_exynos4212() || soc_is_exynos4412()) { + apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_APLL_CON0)); + mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0)); + epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0), + __raw_readl(EXYNOS4_EPLL_CON1)); + + vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk); + vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0), + __raw_readl(EXYNOS4_VPLL_CON1)); + } else { + /* nothing */ + } + + clk_fout_apll.ops = &exynos4_fout_apll_ops; + clk_fout_mpll.rate = mpll; + clk_fout_epll.rate = epll; + clk_fout_vpll.ops = &exynos4_vpll_ops; + clk_fout_vpll.rate = vpll; + + printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld", + apll, mpll, epll, vpll); + + armclk = clk_get_rate(&exynos4_clk_armclk.clk); + sclk_dmc = clk_get_rate(&exynos4_clk_sclk_dmc.clk); + + aclk_200 = clk_get_rate(&exynos4_clk_aclk_200.clk); + aclk_100 = clk_get_rate(&exynos4_clk_aclk_100.clk); + aclk_160 = clk_get_rate(&exynos4_clk_aclk_160.clk); + aclk_133 = clk_get_rate(&exynos4_clk_aclk_133.clk); + + printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n" + "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n", + armclk, sclk_dmc, aclk_200, + aclk_100, aclk_160, aclk_133); + + clk_f.rate = armclk; + clk_h.rate = sclk_dmc; + clk_p.rate = aclk_100; + + for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrcs); ptr++) + s3c_set_clksrc(&exynos4_clksrcs[ptr], true); +} + +static struct clk *exynos4_clks[] __initdata = { + &exynos4_clk_sclk_hdmi27m, + &exynos4_clk_sclk_hdmiphy, + &exynos4_clk_sclk_usbphy0, + &exynos4_clk_sclk_usbphy1, +}; + +#ifdef CONFIG_PM_SLEEP +static int exynos4_clock_suspend(void) +{ + s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save)); + return 0; +} + +static void exynos4_clock_resume(void) +{ + s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save)); +} + +#else +#define exynos4_clock_suspend NULL +#define exynos4_clock_resume NULL +#endif + +static struct syscore_ops exynos4_clock_syscore_ops = { + .suspend = exynos4_clock_suspend, + .resume = exynos4_clock_resume, +}; + +void __init exynos4_register_clocks(void) +{ + int ptr; + + s3c24xx_register_clocks(exynos4_clks, ARRAY_SIZE(exynos4_clks)); + + for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sysclks); ptr++) + s3c_register_clksrc(exynos4_sysclks[ptr], 1); + + for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sclk_tv); ptr++) + s3c_register_clksrc(exynos4_sclk_tv[ptr], 1); + + for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrc_cdev); ptr++) + s3c_register_clksrc(exynos4_clksrc_cdev[ptr], 1); + + s3c_register_clksrc(exynos4_clksrcs, ARRAY_SIZE(exynos4_clksrcs)); + s3c_register_clocks(exynos4_init_clocks_on, ARRAY_SIZE(exynos4_init_clocks_on)); + + s3c24xx_register_clocks(exynos4_clk_cdev, ARRAY_SIZE(exynos4_clk_cdev)); + for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clk_cdev); ptr++) + s3c_disable_clocks(exynos4_clk_cdev[ptr], 1); + + s3c_register_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off)); + s3c_disable_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off)); + clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup)); + + register_syscore_ops(&exynos4_clock_syscore_ops); + s3c24xx_register_clock(&dummy_apb_pclk); + + s3c_pwmclk_init(); +} diff --git a/arch/arm/mach-exynos/clock-exynos4.h b/arch/arm/mach-exynos/clock-exynos4.h new file mode 100644 index 000000000000..cb71c29c14d1 --- /dev/null +++ b/arch/arm/mach-exynos/clock-exynos4.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Header file for exynos4 clock support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_CLOCK_H +#define __ASM_ARCH_CLOCK_H __FILE__ + +#include <linux/clk.h> + +extern struct clksrc_clk exynos4_clk_aclk_133; +extern struct clksrc_clk exynos4_clk_mout_mpll; + +extern struct clksrc_sources exynos4_clkset_mout_corebus; +extern struct clksrc_sources exynos4_clkset_group; + +extern struct clk *exynos4_clkset_aclk_top_list[]; +extern struct clk *exynos4_clkset_group_list[]; + +extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable); +extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable); +extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable); + +#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/mach-exynos/clock-exynos4210.c b/arch/arm/mach-exynos/clock-exynos4210.c index 13312ccb2d93..3b131e4b6ef5 100644 --- a/arch/arm/mach-exynos/clock-exynos4210.c +++ b/arch/arm/mach-exynos/clock-exynos4210.c @@ -1,7 +1,5 @@ /* - * linux/arch/arm/mach-exynos4/clock-exynos4210.c - * - * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd. * http://www.samsung.com * * EXYNOS4210 - Clock support @@ -28,20 +26,20 @@ #include <mach/hardware.h> #include <mach/map.h> #include <mach/regs-clock.h> -#include <mach/exynos4-clock.h> #include "common.h" +#include "clock-exynos4.h" #ifdef CONFIG_PM_SLEEP static struct sleep_save exynos4210_clock_save[] = { - SAVE_ITEM(S5P_CLKSRC_IMAGE), - SAVE_ITEM(S5P_CLKSRC_LCD1), - SAVE_ITEM(S5P_CLKDIV_IMAGE), - SAVE_ITEM(S5P_CLKDIV_LCD1), - SAVE_ITEM(S5P_CLKSRC_MASK_LCD1), - SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4210), - SAVE_ITEM(S5P_CLKGATE_IP_LCD1), - SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210), + SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE), + SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE), + SAVE_ITEM(EXYNOS4210_CLKSRC_LCD1), + SAVE_ITEM(EXYNOS4210_CLKDIV_LCD1), + SAVE_ITEM(EXYNOS4210_CLKSRC_MASK_LCD1), + SAVE_ITEM(EXYNOS4210_CLKGATE_IP_IMAGE), + SAVE_ITEM(EXYNOS4210_CLKGATE_IP_LCD1), + SAVE_ITEM(EXYNOS4210_CLKGATE_IP_PERIR), }; #endif @@ -51,7 +49,7 @@ static struct clksrc_clk *sysclks[] = { static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable) { - return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable); + return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable); } static struct clksrc_clk clksrcs[] = { @@ -62,9 +60,9 @@ static struct clksrc_clk clksrcs[] = { .enable = exynos4_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 24), }, - .sources = &clkset_mout_corebus, - .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 }, - .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 }, + .sources = &exynos4_clkset_mout_corebus, + .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 24, .size = 1 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS0, .shift = 20, .size = 4 }, }, { .clk = { .name = "sclk_fimd", @@ -72,9 +70,9 @@ static struct clksrc_clk clksrcs[] = { .enable = exynos4_clksrc_mask_lcd1_ctrl, .ctrlbit = (1 << 0), }, - .sources = &clkset_group, - .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 }, - .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 }, + .reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 }, }, }; @@ -82,13 +80,13 @@ static struct clk init_clocks_off[] = { { .name = "sataphy", .id = -1, - .parent = &clk_aclk_133.clk, + .parent = &exynos4_clk_aclk_133.clk, .enable = exynos4_clk_ip_fsys_ctrl, .ctrlbit = (1 << 3), }, { .name = "sata", .id = -1, - .parent = &clk_aclk_133.clk, + .parent = &exynos4_clk_aclk_133.clk, .enable = exynos4_clk_ip_fsys_ctrl, .ctrlbit = (1 << 10), }, { @@ -117,7 +115,7 @@ static void exynos4210_clock_resume(void) #define exynos4210_clock_resume NULL #endif -struct syscore_ops exynos4210_clock_syscore_ops = { +static struct syscore_ops exynos4210_clock_syscore_ops = { .suspend = exynos4210_clock_suspend, .resume = exynos4210_clock_resume, }; @@ -126,9 +124,9 @@ void __init exynos4210_register_clocks(void) { int ptr; - clk_mout_mpll.reg_src.reg = S5P_CLKSRC_CPU; - clk_mout_mpll.reg_src.shift = 8; - clk_mout_mpll.reg_src.size = 1; + exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_CPU; + exynos4_clk_mout_mpll.reg_src.shift = 8; + exynos4_clk_mout_mpll.reg_src.size = 1; for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) s3c_register_clksrc(sysclks[ptr], 1); diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c index 48af28566fa1..3ecc01e06f74 100644 --- a/arch/arm/mach-exynos/clock-exynos4212.c +++ b/arch/arm/mach-exynos/clock-exynos4212.c @@ -1,7 +1,5 @@ /* - * linux/arch/arm/mach-exynos4/clock-exynos4212.c - * - * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd. * http://www.samsung.com * * EXYNOS4212 - Clock support @@ -28,22 +26,22 @@ #include <mach/hardware.h> #include <mach/map.h> #include <mach/regs-clock.h> -#include <mach/exynos4-clock.h> #include "common.h" +#include "clock-exynos4.h" #ifdef CONFIG_PM_SLEEP static struct sleep_save exynos4212_clock_save[] = { - SAVE_ITEM(S5P_CLKSRC_IMAGE), - SAVE_ITEM(S5P_CLKDIV_IMAGE), - SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212), - SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212), + SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE), + SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE), + SAVE_ITEM(EXYNOS4212_CLKGATE_IP_IMAGE), + SAVE_ITEM(EXYNOS4212_CLKGATE_IP_PERIR), }; #endif static struct clk *clk_src_mpll_user_list[] = { [0] = &clk_fin_mpll, - [1] = &clk_mout_mpll.clk, + [1] = &exynos4_clk_mout_mpll.clk, }; static struct clksrc_sources clk_src_mpll_user = { @@ -56,7 +54,7 @@ static struct clksrc_clk clk_mout_mpll_user = { .name = "mout_mpll_user", }, .sources = &clk_src_mpll_user, - .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 24, .size = 1 }, + .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 }, }; static struct clksrc_clk *sysclks[] = { @@ -89,7 +87,7 @@ static void exynos4212_clock_resume(void) #define exynos4212_clock_resume NULL #endif -struct syscore_ops exynos4212_clock_syscore_ops = { +static struct syscore_ops exynos4212_clock_syscore_ops = { .suspend = exynos4212_clock_suspend, .resume = exynos4212_clock_resume, }; @@ -99,15 +97,15 @@ void __init exynos4212_register_clocks(void) int ptr; /* usbphy1 is removed */ - clkset_group_list[4] = NULL; + exynos4_clkset_group_list[4] = NULL; /* mout_mpll_user is used */ - clkset_group_list[6] = &clk_mout_mpll_user.clk; - clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk; + exynos4_clkset_group_list[6] = &clk_mout_mpll_user.clk; + exynos4_clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk; - clk_mout_mpll.reg_src.reg = S5P_CLKSRC_DMC; - clk_mout_mpll.reg_src.shift = 12; - clk_mout_mpll.reg_src.size = 1; + exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC; + exynos4_clk_mout_mpll.reg_src.shift = 12; + exynos4_clk_mout_mpll.reg_src.size = 1; for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) s3c_register_clksrc(sysclks[ptr], 1); diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c deleted file mode 100644 index ac249e46a21c..000000000000 --- a/arch/arm/mach-exynos/clock.c +++ /dev/null @@ -1,1569 +0,0 @@ -/* linux/arch/arm/mach-exynos4/clock.c - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS4 - Clock support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/err.h> -#include <linux/io.h> -#include <linux/syscore_ops.h> - -#include <plat/cpu-freq.h> -#include <plat/clock.h> -#include <plat/cpu.h> -#include <plat/pll.h> -#include <plat/s5p-clock.h> -#include <plat/clock-clksrc.h> -#include <plat/pm.h> - -#include <mach/map.h> -#include <mach/regs-clock.h> -#include <mach/sysmmu.h> -#include <mach/exynos4-clock.h> - -#include "common.h" - -#ifdef CONFIG_PM_SLEEP -static struct sleep_save exynos4_clock_save[] = { - SAVE_ITEM(S5P_CLKDIV_LEFTBUS), - SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS), - SAVE_ITEM(S5P_CLKDIV_RIGHTBUS), - SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS), - SAVE_ITEM(S5P_CLKSRC_TOP0), - SAVE_ITEM(S5P_CLKSRC_TOP1), - SAVE_ITEM(S5P_CLKSRC_CAM), - SAVE_ITEM(S5P_CLKSRC_TV), - SAVE_ITEM(S5P_CLKSRC_MFC), - SAVE_ITEM(S5P_CLKSRC_G3D), - SAVE_ITEM(S5P_CLKSRC_LCD0), - SAVE_ITEM(S5P_CLKSRC_MAUDIO), - SAVE_ITEM(S5P_CLKSRC_FSYS), - SAVE_ITEM(S5P_CLKSRC_PERIL0), - SAVE_ITEM(S5P_CLKSRC_PERIL1), - SAVE_ITEM(S5P_CLKDIV_CAM), - SAVE_ITEM(S5P_CLKDIV_TV), - SAVE_ITEM(S5P_CLKDIV_MFC), - SAVE_ITEM(S5P_CLKDIV_G3D), - SAVE_ITEM(S5P_CLKDIV_LCD0), - SAVE_ITEM(S5P_CLKDIV_MAUDIO), - SAVE_ITEM(S5P_CLKDIV_FSYS0), - SAVE_ITEM(S5P_CLKDIV_FSYS1), - SAVE_ITEM(S5P_CLKDIV_FSYS2), - SAVE_ITEM(S5P_CLKDIV_FSYS3), - SAVE_ITEM(S5P_CLKDIV_PERIL0), - SAVE_ITEM(S5P_CLKDIV_PERIL1), - SAVE_ITEM(S5P_CLKDIV_PERIL2), - SAVE_ITEM(S5P_CLKDIV_PERIL3), - SAVE_ITEM(S5P_CLKDIV_PERIL4), - SAVE_ITEM(S5P_CLKDIV_PERIL5), - SAVE_ITEM(S5P_CLKDIV_TOP), - SAVE_ITEM(S5P_CLKSRC_MASK_TOP), - SAVE_ITEM(S5P_CLKSRC_MASK_CAM), - SAVE_ITEM(S5P_CLKSRC_MASK_TV), - SAVE_ITEM(S5P_CLKSRC_MASK_LCD0), - SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO), - SAVE_ITEM(S5P_CLKSRC_MASK_FSYS), - SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0), - SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1), - SAVE_ITEM(S5P_CLKDIV2_RATIO), - SAVE_ITEM(S5P_CLKGATE_SCLKCAM), - SAVE_ITEM(S5P_CLKGATE_IP_CAM), - SAVE_ITEM(S5P_CLKGATE_IP_TV), - SAVE_ITEM(S5P_CLKGATE_IP_MFC), - SAVE_ITEM(S5P_CLKGATE_IP_G3D), - SAVE_ITEM(S5P_CLKGATE_IP_LCD0), - SAVE_ITEM(S5P_CLKGATE_IP_FSYS), - SAVE_ITEM(S5P_CLKGATE_IP_GPS), - SAVE_ITEM(S5P_CLKGATE_IP_PERIL), - SAVE_ITEM(S5P_CLKGATE_BLOCK), - SAVE_ITEM(S5P_CLKSRC_MASK_DMC), - SAVE_ITEM(S5P_CLKSRC_DMC), - SAVE_ITEM(S5P_CLKDIV_DMC0), - SAVE_ITEM(S5P_CLKDIV_DMC1), - SAVE_ITEM(S5P_CLKGATE_IP_DMC), - SAVE_ITEM(S5P_CLKSRC_CPU), - SAVE_ITEM(S5P_CLKDIV_CPU), - SAVE_ITEM(S5P_CLKDIV_CPU + 0x4), - SAVE_ITEM(S5P_CLKGATE_SCLKCPU), - SAVE_ITEM(S5P_CLKGATE_IP_CPU), -}; -#endif - -struct clk clk_sclk_hdmi27m = { - .name = "sclk_hdmi27m", - .rate = 27000000, -}; - -struct clk clk_sclk_hdmiphy = { - .name = "sclk_hdmiphy", -}; - -struct clk clk_sclk_usbphy0 = { - .name = "sclk_usbphy0", - .rate = 27000000, -}; - -struct clk clk_sclk_usbphy1 = { - .name = "sclk_usbphy1", -}; - -static struct clk dummy_apb_pclk = { - .name = "apb_pclk", - .id = -1, -}; - -static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable); -} - -static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable); -} - -static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable); -} - -int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable); -} - -static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable); -} - -static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable); -} - -static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable); -} - -static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(S5P_CLKSRC_MASK_TV, clk, enable); -} - -static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable); -} - -static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(S5P_CLKGATE_IP_TV, clk, enable); -} - -static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable); -} - -static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable); -} - -int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable); -} - -int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable); -} - -static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable); -} - -static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable); -} - -static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable); -} - -static int exynos4_clk_dac_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable); -} - -/* Core list of CMU_CPU side */ - -static struct clksrc_clk clk_mout_apll = { - .clk = { - .name = "mout_apll", - }, - .sources = &clk_src_apll, - .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 }, -}; - -struct clksrc_clk clk_sclk_apll = { - .clk = { - .name = "sclk_apll", - .parent = &clk_mout_apll.clk, - }, - .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 }, -}; - -struct clksrc_clk clk_mout_epll = { - .clk = { - .name = "mout_epll", - }, - .sources = &clk_src_epll, - .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 }, -}; - -struct clksrc_clk clk_mout_mpll = { - .clk = { - .name = "mout_mpll", - }, - .sources = &clk_src_mpll, - - /* reg_src will be added in each SoCs' clock */ -}; - -static struct clk *clkset_moutcore_list[] = { - [0] = &clk_mout_apll.clk, - [1] = &clk_mout_mpll.clk, -}; - -static struct clksrc_sources clkset_moutcore = { - .sources = clkset_moutcore_list, - .nr_sources = ARRAY_SIZE(clkset_moutcore_list), -}; - -static struct clksrc_clk clk_moutcore = { - .clk = { - .name = "moutcore", - }, - .sources = &clkset_moutcore, - .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 }, -}; - -static struct clksrc_clk clk_coreclk = { - .clk = { - .name = "core_clk", - .parent = &clk_moutcore.clk, - }, - .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 }, -}; - -static struct clksrc_clk clk_armclk = { - .clk = { - .name = "armclk", - .parent = &clk_coreclk.clk, - }, -}; - -static struct clksrc_clk clk_aclk_corem0 = { - .clk = { - .name = "aclk_corem0", - .parent = &clk_coreclk.clk, - }, - .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 }, -}; - -static struct clksrc_clk clk_aclk_cores = { - .clk = { - .name = "aclk_cores", - .parent = &clk_coreclk.clk, - }, - .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 }, -}; - -static struct clksrc_clk clk_aclk_corem1 = { - .clk = { - .name = "aclk_corem1", - .parent = &clk_coreclk.clk, - }, - .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 }, -}; - -static struct clksrc_clk clk_periphclk = { - .clk = { - .name = "periphclk", - .parent = &clk_coreclk.clk, - }, - .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 }, -}; - -/* Core list of CMU_CORE side */ - -struct clk *clkset_corebus_list[] = { - [0] = &clk_mout_mpll.clk, - [1] = &clk_sclk_apll.clk, -}; - -struct clksrc_sources clkset_mout_corebus = { - .sources = clkset_corebus_list, - .nr_sources = ARRAY_SIZE(clkset_corebus_list), -}; - -static struct clksrc_clk clk_mout_corebus = { - .clk = { - .name = "mout_corebus", - }, - .sources = &clkset_mout_corebus, - .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 }, -}; - -static struct clksrc_clk clk_sclk_dmc = { - .clk = { - .name = "sclk_dmc", - .parent = &clk_mout_corebus.clk, - }, - .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 }, -}; - -static struct clksrc_clk clk_aclk_cored = { - .clk = { - .name = "aclk_cored", - .parent = &clk_sclk_dmc.clk, - }, - .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 }, -}; - -static struct clksrc_clk clk_aclk_corep = { - .clk = { - .name = "aclk_corep", - .parent = &clk_aclk_cored.clk, - }, - .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 }, -}; - -static struct clksrc_clk clk_aclk_acp = { - .clk = { - .name = "aclk_acp", - .parent = &clk_mout_corebus.clk, - }, - .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 }, -}; - -static struct clksrc_clk clk_pclk_acp = { - .clk = { - .name = "pclk_acp", - .parent = &clk_aclk_acp.clk, - }, - .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 }, -}; - -/* Core list of CMU_TOP side */ - -struct clk *clkset_aclk_top_list[] = { - [0] = &clk_mout_mpll.clk, - [1] = &clk_sclk_apll.clk, -}; - -struct clksrc_sources clkset_aclk = { - .sources = clkset_aclk_top_list, - .nr_sources = ARRAY_SIZE(clkset_aclk_top_list), -}; - -static struct clksrc_clk clk_aclk_200 = { - .clk = { - .name = "aclk_200", - }, - .sources = &clkset_aclk, - .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 }, - .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 }, -}; - -static struct clksrc_clk clk_aclk_100 = { - .clk = { - .name = "aclk_100", - }, - .sources = &clkset_aclk, - .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 }, - .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 }, -}; - -static struct clksrc_clk clk_aclk_160 = { - .clk = { - .name = "aclk_160", - }, - .sources = &clkset_aclk, - .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 }, - .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 }, -}; - -struct clksrc_clk clk_aclk_133 = { - .clk = { - .name = "aclk_133", - }, - .sources = &clkset_aclk, - .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 }, - .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 }, -}; - -static struct clk *clkset_vpllsrc_list[] = { - [0] = &clk_fin_vpll, - [1] = &clk_sclk_hdmi27m, -}; - -static struct clksrc_sources clkset_vpllsrc = { - .sources = clkset_vpllsrc_list, - .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list), -}; - -static struct clksrc_clk clk_vpllsrc = { - .clk = { - .name = "vpll_src", - .enable = exynos4_clksrc_mask_top_ctrl, - .ctrlbit = (1 << 0), - }, - .sources = &clkset_vpllsrc, - .reg_src = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 }, -}; - -static struct clk *clkset_sclk_vpll_list[] = { - [0] = &clk_vpllsrc.clk, - [1] = &clk_fout_vpll, -}; - -static struct clksrc_sources clkset_sclk_vpll = { - .sources = clkset_sclk_vpll_list, - .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list), -}; - -struct clksrc_clk clk_sclk_vpll = { - .clk = { - .name = "sclk_vpll", - }, - .sources = &clkset_sclk_vpll, - .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 }, -}; - -static struct clk init_clocks_off[] = { - { - .name = "timers", - .parent = &clk_aclk_100.clk, - .enable = exynos4_clk_ip_peril_ctrl, - .ctrlbit = (1<<24), - }, { - .name = "csis", - .devname = "s5p-mipi-csis.0", - .enable = exynos4_clk_ip_cam_ctrl, - .ctrlbit = (1 << 4), - }, { - .name = "csis", - .devname = "s5p-mipi-csis.1", - .enable = exynos4_clk_ip_cam_ctrl, - .ctrlbit = (1 << 5), - }, { - .name = "jpeg", - .id = 0, - .enable = exynos4_clk_ip_cam_ctrl, - .ctrlbit = (1 << 6), - }, { - .name = "fimc", - .devname = "exynos4-fimc.0", - .enable = exynos4_clk_ip_cam_ctrl, - .ctrlbit = (1 << 0), - }, { - .name = "fimc", - .devname = "exynos4-fimc.1", - .enable = exynos4_clk_ip_cam_ctrl, - .ctrlbit = (1 << 1), - }, { - .name = "fimc", - .devname = "exynos4-fimc.2", - .enable = exynos4_clk_ip_cam_ctrl, - .ctrlbit = (1 << 2), - }, { - .name = "fimc", - .devname = "exynos4-fimc.3", - .enable = exynos4_clk_ip_cam_ctrl, - .ctrlbit = (1 << 3), - }, { - .name = "fimd", - .devname = "exynos4-fb.0", - .enable = exynos4_clk_ip_lcd0_ctrl, - .ctrlbit = (1 << 0), - }, { - .name = "hsmmc", - .devname = "s3c-sdhci.0", - .parent = &clk_aclk_133.clk, - .enable = exynos4_clk_ip_fsys_ctrl, - .ctrlbit = (1 << 5), - }, { - .name = "hsmmc", - .devname = "s3c-sdhci.1", - .parent = &clk_aclk_133.clk, - .enable = exynos4_clk_ip_fsys_ctrl, - .ctrlbit = (1 << 6), - }, { - .name = "hsmmc", - .devname = "s3c-sdhci.2", - .parent = &clk_aclk_133.clk, - .enable = exynos4_clk_ip_fsys_ctrl, - .ctrlbit = (1 << 7), - }, { - .name = "hsmmc", - .devname = "s3c-sdhci.3", - .parent = &clk_aclk_133.clk, - .enable = exynos4_clk_ip_fsys_ctrl, - .ctrlbit = (1 << 8), - }, { - .name = "dwmmc", - .parent = &clk_aclk_133.clk, - .enable = exynos4_clk_ip_fsys_ctrl, - .ctrlbit = (1 << 9), - }, { - .name = "dac", - .devname = "s5p-sdo", - .enable = exynos4_clk_ip_tv_ctrl, - .ctrlbit = (1 << 2), - }, { - .name = "mixer", - .devname = "s5p-mixer", - .enable = exynos4_clk_ip_tv_ctrl, - .ctrlbit = (1 << 1), - }, { - .name = "vp", - .devname = "s5p-mixer", - .enable = exynos4_clk_ip_tv_ctrl, - .ctrlbit = (1 << 0), - }, { - .name = "hdmi", - .devname = "exynos4-hdmi", - .enable = exynos4_clk_ip_tv_ctrl, - .ctrlbit = (1 << 3), - }, { - .name = "hdmiphy", - .devname = "exynos4-hdmi", - .enable = exynos4_clk_hdmiphy_ctrl, - .ctrlbit = (1 << 0), - }, { - .name = "dacphy", - .devname = "s5p-sdo", - .enable = exynos4_clk_dac_ctrl, - .ctrlbit = (1 << 0), - }, { - .name = "adc", - .enable = exynos4_clk_ip_peril_ctrl, - .ctrlbit = (1 << 15), - }, { - .name = "keypad", - .enable = exynos4_clk_ip_perir_ctrl, - .ctrlbit = (1 << 16), - }, { - .name = "rtc", - .enable = exynos4_clk_ip_perir_ctrl, - .ctrlbit = (1 << 15), - }, { - .name = "watchdog", - .parent = &clk_aclk_100.clk, - .enable = exynos4_clk_ip_perir_ctrl, - .ctrlbit = (1 << 14), - }, { - .name = "usbhost", - .enable = exynos4_clk_ip_fsys_ctrl , - .ctrlbit = (1 << 12), - }, { - .name = "otg", - .enable = exynos4_clk_ip_fsys_ctrl, - .ctrlbit = (1 << 13), - }, { - .name = "spi", - .devname = "s3c64xx-spi.0", - .enable = exynos4_clk_ip_peril_ctrl, - .ctrlbit = (1 << 16), - }, { - .name = "spi", - .devname = "s3c64xx-spi.1", - .enable = exynos4_clk_ip_peril_ctrl, - .ctrlbit = (1 << 17), - }, { - .name = "spi", - .devname = "s3c64xx-spi.2", - .enable = exynos4_clk_ip_peril_ctrl, - .ctrlbit = (1 << 18), - }, { - .name = "iis", - .devname = "samsung-i2s.0", - .enable = exynos4_clk_ip_peril_ctrl, - .ctrlbit = (1 << 19), - }, { - .name = "iis", - .devname = "samsung-i2s.1", - .enable = exynos4_clk_ip_peril_ctrl, - .ctrlbit = (1 << 20), - }, { - .name = "iis", - .devname = "samsung-i2s.2", - .enable = exynos4_clk_ip_peril_ctrl, - .ctrlbit = (1 << 21), - }, { - .name = "ac97", - .devname = "samsung-ac97", - .enable = exynos4_clk_ip_peril_ctrl, - .ctrlbit = (1 << 27), - }, { - .name = "fimg2d", - .enable = exynos4_clk_ip_image_ctrl, - .ctrlbit = (1 << 0), - }, { - .name = "mfc", - .devname = "s5p-mfc", - .enable = exynos4_clk_ip_mfc_ctrl, - .ctrlbit = (1 << 0), - }, { - .name = "i2c", - .devname = "s3c2440-i2c.0", - .parent = &clk_aclk_100.clk, - .enable = exynos4_clk_ip_peril_ctrl, - .ctrlbit = (1 << 6), - }, { - .name = "i2c", - .devname = "s3c2440-i2c.1", - .parent = &clk_aclk_100.clk, - .enable = exynos4_clk_ip_peril_ctrl, - .ctrlbit = (1 << 7), - }, { - .name = "i2c", - .devname = "s3c2440-i2c.2", - .parent = &clk_aclk_100.clk, - .enable = exynos4_clk_ip_peril_ctrl, - .ctrlbit = (1 << 8), - }, { - .name = "i2c", - .devname = "s3c2440-i2c.3", - .parent = &clk_aclk_100.clk, - .enable = exynos4_clk_ip_peril_ctrl, - .ctrlbit = (1 << 9), - }, { - .name = "i2c", - .devname = "s3c2440-i2c.4", - .parent = &clk_aclk_100.clk, - .enable = exynos4_clk_ip_peril_ctrl, - .ctrlbit = (1 << 10), - }, { - .name = "i2c", - .devname = "s3c2440-i2c.5", - .parent = &clk_aclk_100.clk, - .enable = exynos4_clk_ip_peril_ctrl, - .ctrlbit = (1 << 11), - }, { - .name = "i2c", - .devname = "s3c2440-i2c.6", - .parent = &clk_aclk_100.clk, - .enable = exynos4_clk_ip_peril_ctrl, - .ctrlbit = (1 << 12), - }, { - .name = "i2c", - .devname = "s3c2440-i2c.7", - .parent = &clk_aclk_100.clk, - .enable = exynos4_clk_ip_peril_ctrl, - .ctrlbit = (1 << 13), - }, { - .name = "i2c", - .devname = "s3c2440-hdmiphy-i2c", - .parent = &clk_aclk_100.clk, - .enable = exynos4_clk_ip_peril_ctrl, - .ctrlbit = (1 << 14), - }, { - .name = "SYSMMU_MDMA", - .enable = exynos4_clk_ip_image_ctrl, - .ctrlbit = (1 << 5), - }, { - .name = "SYSMMU_FIMC0", - .enable = exynos4_clk_ip_cam_ctrl, - .ctrlbit = (1 << 7), - }, { - .name = "SYSMMU_FIMC1", - .enable = exynos4_clk_ip_cam_ctrl, - .ctrlbit = (1 << 8), - }, { - .name = "SYSMMU_FIMC2", - .enable = exynos4_clk_ip_cam_ctrl, - .ctrlbit = (1 << 9), - }, { - .name = "SYSMMU_FIMC3", - .enable = exynos4_clk_ip_cam_ctrl, - .ctrlbit = (1 << 10), - }, { - .name = "SYSMMU_JPEG", - .enable = exynos4_clk_ip_cam_ctrl, - .ctrlbit = (1 << 11), - }, { - .name = "SYSMMU_FIMD0", - .enable = exynos4_clk_ip_lcd0_ctrl, - .ctrlbit = (1 << 4), - }, { - .name = "SYSMMU_FIMD1", - .enable = exynos4_clk_ip_lcd1_ctrl, - .ctrlbit = (1 << 4), - }, { - .name = "SYSMMU_PCIe", - .enable = exynos4_clk_ip_fsys_ctrl, - .ctrlbit = (1 << 18), - }, { - .name = "SYSMMU_G2D", - .enable = exynos4_clk_ip_image_ctrl, - .ctrlbit = (1 << 3), - }, { - .name = "SYSMMU_ROTATOR", - .enable = exynos4_clk_ip_image_ctrl, - .ctrlbit = (1 << 4), - }, { - .name = "SYSMMU_TV", - .enable = exynos4_clk_ip_tv_ctrl, - .ctrlbit = (1 << 4), - }, { - .name = "SYSMMU_MFC_L", - .enable = exynos4_clk_ip_mfc_ctrl, - .ctrlbit = (1 << 1), - }, { - .name = "SYSMMU_MFC_R", - .enable = exynos4_clk_ip_mfc_ctrl, - .ctrlbit = (1 << 2), - } -}; - -static struct clk init_clocks[] = { - { - .name = "uart", - .devname = "s5pv210-uart.0", - .enable = exynos4_clk_ip_peril_ctrl, - .ctrlbit = (1 << 0), - }, { - .name = "uart", - .devname = "s5pv210-uart.1", - .enable = exynos4_clk_ip_peril_ctrl, - .ctrlbit = (1 << 1), - }, { - .name = "uart", - .devname = "s5pv210-uart.2", - .enable = exynos4_clk_ip_peril_ctrl, - .ctrlbit = (1 << 2), - }, { - .name = "uart", - .devname = "s5pv210-uart.3", - .enable = exynos4_clk_ip_peril_ctrl, - .ctrlbit = (1 << 3), - }, { - .name = "uart", - .devname = "s5pv210-uart.4", - .enable = exynos4_clk_ip_peril_ctrl, - .ctrlbit = (1 << 4), - }, { - .name = "uart", - .devname = "s5pv210-uart.5", - .enable = exynos4_clk_ip_peril_ctrl, - .ctrlbit = (1 << 5), - } -}; - -static struct clk clk_pdma0 = { - .name = "dma", - .devname = "dma-pl330.0", - .enable = exynos4_clk_ip_fsys_ctrl, - .ctrlbit = (1 << 0), -}; - -static struct clk clk_pdma1 = { - .name = "dma", - .devname = "dma-pl330.1", - .enable = exynos4_clk_ip_fsys_ctrl, - .ctrlbit = (1 << 1), -}; - -struct clk *clkset_group_list[] = { - [0] = &clk_ext_xtal_mux, - [1] = &clk_xusbxti, - [2] = &clk_sclk_hdmi27m, - [3] = &clk_sclk_usbphy0, - [4] = &clk_sclk_usbphy1, - [5] = &clk_sclk_hdmiphy, - [6] = &clk_mout_mpll.clk, - [7] = &clk_mout_epll.clk, - [8] = &clk_sclk_vpll.clk, -}; - -struct clksrc_sources clkset_group = { - .sources = clkset_group_list, - .nr_sources = ARRAY_SIZE(clkset_group_list), -}; - -static struct clk *clkset_mout_g2d0_list[] = { - [0] = &clk_mout_mpll.clk, - [1] = &clk_sclk_apll.clk, -}; - -static struct clksrc_sources clkset_mout_g2d0 = { - .sources = clkset_mout_g2d0_list, - .nr_sources = ARRAY_SIZE(clkset_mout_g2d0_list), -}; - -static struct clksrc_clk clk_mout_g2d0 = { - .clk = { - .name = "mout_g2d0", - }, - .sources = &clkset_mout_g2d0, - .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 }, -}; - -static struct clk *clkset_mout_g2d1_list[] = { - [0] = &clk_mout_epll.clk, - [1] = &clk_sclk_vpll.clk, -}; - -static struct clksrc_sources clkset_mout_g2d1 = { - .sources = clkset_mout_g2d1_list, - .nr_sources = ARRAY_SIZE(clkset_mout_g2d1_list), -}; - -static struct clksrc_clk clk_mout_g2d1 = { - .clk = { - .name = "mout_g2d1", - }, - .sources = &clkset_mout_g2d1, - .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 }, -}; - -static struct clk *clkset_mout_g2d_list[] = { - [0] = &clk_mout_g2d0.clk, - [1] = &clk_mout_g2d1.clk, -}; - -static struct clksrc_sources clkset_mout_g2d = { - .sources = clkset_mout_g2d_list, - .nr_sources = ARRAY_SIZE(clkset_mout_g2d_list), -}; - -static struct clk *clkset_mout_mfc0_list[] = { - [0] = &clk_mout_mpll.clk, - [1] = &clk_sclk_apll.clk, -}; - -static struct clksrc_sources clkset_mout_mfc0 = { - .sources = clkset_mout_mfc0_list, - .nr_sources = ARRAY_SIZE(clkset_mout_mfc0_list), -}; - -static struct clksrc_clk clk_mout_mfc0 = { - .clk = { - .name = "mout_mfc0", - }, - .sources = &clkset_mout_mfc0, - .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 }, -}; - -static struct clk *clkset_mout_mfc1_list[] = { - [0] = &clk_mout_epll.clk, - [1] = &clk_sclk_vpll.clk, -}; - -static struct clksrc_sources clkset_mout_mfc1 = { - .sources = clkset_mout_mfc1_list, - .nr_sources = ARRAY_SIZE(clkset_mout_mfc1_list), -}; - -static struct clksrc_clk clk_mout_mfc1 = { - .clk = { - .name = "mout_mfc1", - }, - .sources = &clkset_mout_mfc1, - .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 }, -}; - -static struct clk *clkset_mout_mfc_list[] = { - [0] = &clk_mout_mfc0.clk, - [1] = &clk_mout_mfc1.clk, -}; - -static struct clksrc_sources clkset_mout_mfc = { - .sources = clkset_mout_mfc_list, - .nr_sources = ARRAY_SIZE(clkset_mout_mfc_list), -}; - -static struct clk *clkset_sclk_dac_list[] = { - [0] = &clk_sclk_vpll.clk, - [1] = &clk_sclk_hdmiphy, -}; - -static struct clksrc_sources clkset_sclk_dac = { - .sources = clkset_sclk_dac_list, - .nr_sources = ARRAY_SIZE(clkset_sclk_dac_list), -}; - -static struct clksrc_clk clk_sclk_dac = { - .clk = { - .name = "sclk_dac", - .enable = exynos4_clksrc_mask_tv_ctrl, - .ctrlbit = (1 << 8), - }, - .sources = &clkset_sclk_dac, - .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 8, .size = 1 }, -}; - -static struct clksrc_clk clk_sclk_pixel = { - .clk = { - .name = "sclk_pixel", - .parent = &clk_sclk_vpll.clk, - }, - .reg_div = { .reg = S5P_CLKDIV_TV, .shift = 0, .size = 4 }, -}; - -static struct clk *clkset_sclk_hdmi_list[] = { - [0] = &clk_sclk_pixel.clk, - [1] = &clk_sclk_hdmiphy, -}; - -static struct clksrc_sources clkset_sclk_hdmi = { - .sources = clkset_sclk_hdmi_list, - .nr_sources = ARRAY_SIZE(clkset_sclk_hdmi_list), -}; - -static struct clksrc_clk clk_sclk_hdmi = { - .clk = { - .name = "sclk_hdmi", - .enable = exynos4_clksrc_mask_tv_ctrl, - .ctrlbit = (1 << 0), - }, - .sources = &clkset_sclk_hdmi, - .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 0, .size = 1 }, -}; - -static struct clk *clkset_sclk_mixer_list[] = { - [0] = &clk_sclk_dac.clk, - [1] = &clk_sclk_hdmi.clk, -}; - -static struct clksrc_sources clkset_sclk_mixer = { - .sources = clkset_sclk_mixer_list, - .nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list), -}; - -static struct clksrc_clk clk_sclk_mixer = { - .clk = { - .name = "sclk_mixer", - .enable = exynos4_clksrc_mask_tv_ctrl, - .ctrlbit = (1 << 4), - }, - .sources = &clkset_sclk_mixer, - .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 4, .size = 1 }, -}; - -static struct clksrc_clk *sclk_tv[] = { - &clk_sclk_dac, - &clk_sclk_pixel, - &clk_sclk_hdmi, - &clk_sclk_mixer, -}; - -static struct clksrc_clk clk_dout_mmc0 = { - .clk = { - .name = "dout_mmc0", - }, - .sources = &clkset_group, - .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 }, - .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 }, -}; - -static struct clksrc_clk clk_dout_mmc1 = { - .clk = { - .name = "dout_mmc1", - }, - .sources = &clkset_group, - .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 }, - .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 }, -}; - -static struct clksrc_clk clk_dout_mmc2 = { - .clk = { - .name = "dout_mmc2", - }, - .sources = &clkset_group, - .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 }, - .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 }, -}; - -static struct clksrc_clk clk_dout_mmc3 = { - .clk = { - .name = "dout_mmc3", - }, - .sources = &clkset_group, - .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 }, - .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 }, -}; - -static struct clksrc_clk clk_dout_mmc4 = { - .clk = { - .name = "dout_mmc4", - }, - .sources = &clkset_group, - .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 }, - .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 }, -}; - -static struct clksrc_clk clksrcs[] = { - { - .clk = { - .name = "sclk_pwm", - .enable = exynos4_clksrc_mask_peril0_ctrl, - .ctrlbit = (1 << 24), - }, - .sources = &clkset_group, - .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 }, - .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 }, - }, { - .clk = { - .name = "sclk_csis", - .devname = "s5p-mipi-csis.0", - .enable = exynos4_clksrc_mask_cam_ctrl, - .ctrlbit = (1 << 24), - }, - .sources = &clkset_group, - .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 }, - .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 }, - }, { - .clk = { - .name = "sclk_csis", - .devname = "s5p-mipi-csis.1", - .enable = exynos4_clksrc_mask_cam_ctrl, - .ctrlbit = (1 << 28), - }, - .sources = &clkset_group, - .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 }, - .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 }, - }, { - .clk = { - .name = "sclk_cam0", - .enable = exynos4_clksrc_mask_cam_ctrl, - .ctrlbit = (1 << 16), - }, - .sources = &clkset_group, - .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 }, - .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 }, - }, { - .clk = { - .name = "sclk_cam1", - .enable = exynos4_clksrc_mask_cam_ctrl, - .ctrlbit = (1 << 20), - }, - .sources = &clkset_group, - .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 }, - .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 }, - }, { - .clk = { - .name = "sclk_fimc", - .devname = "exynos4-fimc.0", - .enable = exynos4_clksrc_mask_cam_ctrl, - .ctrlbit = (1 << 0), - }, - .sources = &clkset_group, - .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 }, - .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 }, - }, { - .clk = { - .name = "sclk_fimc", - .devname = "exynos4-fimc.1", - .enable = exynos4_clksrc_mask_cam_ctrl, - .ctrlbit = (1 << 4), - }, - .sources = &clkset_group, - .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 }, - .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 }, - }, { - .clk = { - .name = "sclk_fimc", - .devname = "exynos4-fimc.2", - .enable = exynos4_clksrc_mask_cam_ctrl, - .ctrlbit = (1 << 8), - }, - .sources = &clkset_group, - .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 }, - .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 }, - }, { - .clk = { - .name = "sclk_fimc", - .devname = "exynos4-fimc.3", - .enable = exynos4_clksrc_mask_cam_ctrl, - .ctrlbit = (1 << 12), - }, - .sources = &clkset_group, - .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 }, - .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 }, - }, { - .clk = { - .name = "sclk_fimd", - .devname = "exynos4-fb.0", - .enable = exynos4_clksrc_mask_lcd0_ctrl, - .ctrlbit = (1 << 0), - }, - .sources = &clkset_group, - .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 }, - .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 }, - }, { - .clk = { - .name = "sclk_fimg2d", - }, - .sources = &clkset_mout_g2d, - .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 }, - .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 }, - }, { - .clk = { - .name = "sclk_mfc", - .devname = "s5p-mfc", - }, - .sources = &clkset_mout_mfc, - .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 }, - .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 }, - }, { - .clk = { - .name = "sclk_dwmmc", - .parent = &clk_dout_mmc4.clk, - .enable = exynos4_clksrc_mask_fsys_ctrl, - .ctrlbit = (1 << 16), - }, - .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 }, - } -}; - -static struct clksrc_clk clk_sclk_uart0 = { - .clk = { - .name = "uclk1", - .devname = "exynos4210-uart.0", - .enable = exynos4_clksrc_mask_peril0_ctrl, - .ctrlbit = (1 << 0), - }, - .sources = &clkset_group, - .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 }, - .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 }, -}; - -static struct clksrc_clk clk_sclk_uart1 = { - .clk = { - .name = "uclk1", - .devname = "exynos4210-uart.1", - .enable = exynos4_clksrc_mask_peril0_ctrl, - .ctrlbit = (1 << 4), - }, - .sources = &clkset_group, - .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 }, - .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 }, -}; - -static struct clksrc_clk clk_sclk_uart2 = { - .clk = { - .name = "uclk1", - .devname = "exynos4210-uart.2", - .enable = exynos4_clksrc_mask_peril0_ctrl, - .ctrlbit = (1 << 8), - }, - .sources = &clkset_group, - .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 }, - .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 }, -}; - -static struct clksrc_clk clk_sclk_uart3 = { - .clk = { - .name = "uclk1", - .devname = "exynos4210-uart.3", - .enable = exynos4_clksrc_mask_peril0_ctrl, - .ctrlbit = (1 << 12), - }, - .sources = &clkset_group, - .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 }, - .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 }, -}; - -static struct clksrc_clk clk_sclk_mmc0 = { - .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.0", - .parent = &clk_dout_mmc0.clk, - .enable = exynos4_clksrc_mask_fsys_ctrl, - .ctrlbit = (1 << 0), - }, - .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 }, -}; - -static struct clksrc_clk clk_sclk_mmc1 = { - .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.1", - .parent = &clk_dout_mmc1.clk, - .enable = exynos4_clksrc_mask_fsys_ctrl, - .ctrlbit = (1 << 4), - }, - .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 }, -}; - -static struct clksrc_clk clk_sclk_mmc2 = { - .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.2", - .parent = &clk_dout_mmc2.clk, - .enable = exynos4_clksrc_mask_fsys_ctrl, - .ctrlbit = (1 << 8), - }, - .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 }, -}; - -static struct clksrc_clk clk_sclk_mmc3 = { - .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.3", - .parent = &clk_dout_mmc3.clk, - .enable = exynos4_clksrc_mask_fsys_ctrl, - .ctrlbit = (1 << 12), - }, - .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 }, -}; - -static struct clksrc_clk clk_sclk_spi0 = { - .clk = { - .name = "sclk_spi", - .devname = "s3c64xx-spi.0", - .enable = exynos4_clksrc_mask_peril1_ctrl, - .ctrlbit = (1 << 16), - }, - .sources = &clkset_group, - .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 }, - .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 }, -}; - -static struct clksrc_clk clk_sclk_spi1 = { - .clk = { - .name = "sclk_spi", - .devname = "s3c64xx-spi.1", - .enable = exynos4_clksrc_mask_peril1_ctrl, - .ctrlbit = (1 << 20), - }, - .sources = &clkset_group, - .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 }, - .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 }, -}; - -static struct clksrc_clk clk_sclk_spi2 = { - .clk = { - .name = "sclk_spi", - .devname = "s3c64xx-spi.2", - .enable = exynos4_clksrc_mask_peril1_ctrl, - .ctrlbit = (1 << 24), - }, - .sources = &clkset_group, - .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 }, - .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 }, -}; - -/* Clock initialization code */ -static struct clksrc_clk *sysclks[] = { - &clk_mout_apll, - &clk_sclk_apll, - &clk_mout_epll, - &clk_mout_mpll, - &clk_moutcore, - &clk_coreclk, - &clk_armclk, - &clk_aclk_corem0, - &clk_aclk_cores, - &clk_aclk_corem1, - &clk_periphclk, - &clk_mout_corebus, - &clk_sclk_dmc, - &clk_aclk_cored, - &clk_aclk_corep, - &clk_aclk_acp, - &clk_pclk_acp, - &clk_vpllsrc, - &clk_sclk_vpll, - &clk_aclk_200, - &clk_aclk_100, - &clk_aclk_160, - &clk_aclk_133, - &clk_dout_mmc0, - &clk_dout_mmc1, - &clk_dout_mmc2, - &clk_dout_mmc3, - &clk_dout_mmc4, - &clk_mout_mfc0, - &clk_mout_mfc1, -}; - -static struct clk *clk_cdev[] = { - &clk_pdma0, - &clk_pdma1, -}; - -static struct clksrc_clk *clksrc_cdev[] = { - &clk_sclk_uart0, - &clk_sclk_uart1, - &clk_sclk_uart2, - &clk_sclk_uart3, - &clk_sclk_mmc0, - &clk_sclk_mmc1, - &clk_sclk_mmc2, - &clk_sclk_mmc3, - &clk_sclk_spi0, - &clk_sclk_spi1, - &clk_sclk_spi2, - -}; - -static struct clk_lookup exynos4_clk_lookup[] = { - CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &clk_sclk_uart0.clk), - CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk), - CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk), - CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk), - CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), - CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), - CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), - CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk), - CLKDEV_INIT("dma-pl330.0", "apb_pclk", &clk_pdma0), - CLKDEV_INIT("dma-pl330.1", "apb_pclk", &clk_pdma1), - CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &clk_sclk_spi0.clk), - CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &clk_sclk_spi1.clk), - CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &clk_sclk_spi2.clk), -}; - -static int xtal_rate; - -static unsigned long exynos4_fout_apll_get_rate(struct clk *clk) -{ - if (soc_is_exynos4210()) - return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0), - pll_4508); - else if (soc_is_exynos4212() || soc_is_exynos4412()) - return s5p_get_pll35xx(xtal_rate, __raw_readl(S5P_APLL_CON0)); - else - return 0; -} - -static struct clk_ops exynos4_fout_apll_ops = { - .get_rate = exynos4_fout_apll_get_rate, -}; - -static u32 vpll_div[][8] = { - { 54000000, 3, 53, 3, 1024, 0, 17, 0 }, - { 108000000, 3, 53, 2, 1024, 0, 17, 0 }, -}; - -static unsigned long exynos4_vpll_get_rate(struct clk *clk) -{ - return clk->rate; -} - -static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate) -{ - unsigned int vpll_con0, vpll_con1 = 0; - unsigned int i; - - /* Return if nothing changed */ - if (clk->rate == rate) - return 0; - - vpll_con0 = __raw_readl(S5P_VPLL_CON0); - vpll_con0 &= ~(0x1 << 27 | \ - PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \ - PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \ - PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT); - - vpll_con1 = __raw_readl(S5P_VPLL_CON1); - vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT | \ - PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \ - PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT); - - for (i = 0; i < ARRAY_SIZE(vpll_div); i++) { - if (vpll_div[i][0] == rate) { - vpll_con0 |= vpll_div[i][1] << PLL46XX_PDIV_SHIFT; - vpll_con0 |= vpll_div[i][2] << PLL46XX_MDIV_SHIFT; - vpll_con0 |= vpll_div[i][3] << PLL46XX_SDIV_SHIFT; - vpll_con1 |= vpll_div[i][4] << PLL46XX_KDIV_SHIFT; - vpll_con1 |= vpll_div[i][5] << PLL46XX_MFR_SHIFT; - vpll_con1 |= vpll_div[i][6] << PLL46XX_MRR_SHIFT; - vpll_con0 |= vpll_div[i][7] << 27; - break; - } - } - - if (i == ARRAY_SIZE(vpll_div)) { - printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n", - __func__); - return -EINVAL; - } - - __raw_writel(vpll_con0, S5P_VPLL_CON0); - __raw_writel(vpll_con1, S5P_VPLL_CON1); - - /* Wait for VPLL lock */ - while (!(__raw_readl(S5P_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT))) - continue; - - clk->rate = rate; - return 0; -} - -static struct clk_ops exynos4_vpll_ops = { - .get_rate = exynos4_vpll_get_rate, - .set_rate = exynos4_vpll_set_rate, -}; - -void __init_or_cpufreq exynos4_setup_clocks(void) -{ - struct clk *xtal_clk; - unsigned long apll = 0; - unsigned long mpll = 0; - unsigned long epll = 0; - unsigned long vpll = 0; - unsigned long vpllsrc; - unsigned long xtal; - unsigned long armclk; - unsigned long sclk_dmc; - unsigned long aclk_200; - unsigned long aclk_100; - unsigned long aclk_160; - unsigned long aclk_133; - unsigned int ptr; - - printk(KERN_DEBUG "%s: registering clocks\n", __func__); - - xtal_clk = clk_get(NULL, "xtal"); - BUG_ON(IS_ERR(xtal_clk)); - - xtal = clk_get_rate(xtal_clk); - - xtal_rate = xtal; - - clk_put(xtal_clk); - - printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); - - if (soc_is_exynos4210()) { - apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), - pll_4508); - mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), - pll_4508); - epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0), - __raw_readl(S5P_EPLL_CON1), pll_4600); - - vpllsrc = clk_get_rate(&clk_vpllsrc.clk); - vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0), - __raw_readl(S5P_VPLL_CON1), pll_4650c); - } else if (soc_is_exynos4212() || soc_is_exynos4412()) { - apll = s5p_get_pll35xx(xtal, __raw_readl(S5P_APLL_CON0)); - mpll = s5p_get_pll35xx(xtal, __raw_readl(S5P_MPLL_CON0)); - epll = s5p_get_pll36xx(xtal, __raw_readl(S5P_EPLL_CON0), - __raw_readl(S5P_EPLL_CON1)); - - vpllsrc = clk_get_rate(&clk_vpllsrc.clk); - vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(S5P_VPLL_CON0), - __raw_readl(S5P_VPLL_CON1)); - } else { - /* nothing */ - } - - clk_fout_apll.ops = &exynos4_fout_apll_ops; - clk_fout_mpll.rate = mpll; - clk_fout_epll.rate = epll; - clk_fout_vpll.ops = &exynos4_vpll_ops; - clk_fout_vpll.rate = vpll; - - printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld", - apll, mpll, epll, vpll); - - armclk = clk_get_rate(&clk_armclk.clk); - sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk); - - aclk_200 = clk_get_rate(&clk_aclk_200.clk); - aclk_100 = clk_get_rate(&clk_aclk_100.clk); - aclk_160 = clk_get_rate(&clk_aclk_160.clk); - aclk_133 = clk_get_rate(&clk_aclk_133.clk); - - printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n" - "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n", - armclk, sclk_dmc, aclk_200, - aclk_100, aclk_160, aclk_133); - - clk_f.rate = armclk; - clk_h.rate = sclk_dmc; - clk_p.rate = aclk_100; - - for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) - s3c_set_clksrc(&clksrcs[ptr], true); -} - -static struct clk *clks[] __initdata = { - &clk_sclk_hdmi27m, - &clk_sclk_hdmiphy, - &clk_sclk_usbphy0, - &clk_sclk_usbphy1, -}; - -#ifdef CONFIG_PM_SLEEP -static int exynos4_clock_suspend(void) -{ - s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save)); - return 0; -} - -static void exynos4_clock_resume(void) -{ - s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save)); -} - -#else -#define exynos4_clock_suspend NULL -#define exynos4_clock_resume NULL -#endif - -struct syscore_ops exynos4_clock_syscore_ops = { - .suspend = exynos4_clock_suspend, - .resume = exynos4_clock_resume, -}; - -void __init exynos4_register_clocks(void) -{ - int ptr; - - s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); - - for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) - s3c_register_clksrc(sysclks[ptr], 1); - - for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++) - s3c_register_clksrc(sclk_tv[ptr], 1); - - for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++) - s3c_register_clksrc(clksrc_cdev[ptr], 1); - - s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); - s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); - - s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev)); - for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++) - s3c_disable_clocks(clk_cdev[ptr], 1); - - s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); - s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); - clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup)); - - register_syscore_ops(&exynos4_clock_syscore_ops); - s3c24xx_register_clock(&dummy_apb_pclk); - - s3c_pwmclk_init(); -} diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index 7f1f2687147d..519ef0ecd0fa 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -695,7 +695,7 @@ static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc) chained_irq_exit(chip, desc); } -int __init exynos4_init_irq_eint(void) +static int __init exynos4_init_irq_eint(void) { int irq; diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index 1ac49de0f398..8c1efe692c20 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -15,12 +15,21 @@ void exynos_init_io(struct map_desc *mach_desc, int size); void exynos4_init_irq(void); +#ifdef CONFIG_ARCH_EXYNOS4 void exynos4_register_clocks(void); void exynos4_setup_clocks(void); void exynos4210_register_clocks(void); void exynos4212_register_clocks(void); +#else +#define exynos4_register_clocks() +#define exynos4_setup_clocks() + +#define exynos4210_register_clocks() +#define exynos4212_register_clocks() +#endif + void exynos4_restart(char mode, const char *cmd); extern struct sys_timer exynos4_timer; diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c index 91370def4a70..25f3ef2c36e5 100644 --- a/arch/arm/mach-exynos/dma.c +++ b/arch/arm/mach-exynos/dma.c @@ -36,7 +36,7 @@ static u64 dma_dmamask = DMA_BIT_MASK(32); -u8 pdma0_peri[] = { +static u8 pdma0_peri[] = { DMACH_PCM0_RX, DMACH_PCM0_TX, DMACH_PCM2_RX, @@ -69,15 +69,15 @@ u8 pdma0_peri[] = { DMACH_AC97_PCMOUT, }; -struct dma_pl330_platdata exynos4_pdma0_pdata = { +static struct dma_pl330_platdata exynos4_pdma0_pdata = { .nr_valid_peri = ARRAY_SIZE(pdma0_peri), .peri_id = pdma0_peri, }; -AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330, EXYNOS4_PA_PDMA0, - {IRQ_PDMA0}, &exynos4_pdma0_pdata); +static AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330, + EXYNOS4_PA_PDMA0, {IRQ_PDMA0}, &exynos4_pdma0_pdata); -u8 pdma1_peri[] = { +static u8 pdma1_peri[] = { DMACH_PCM0_RX, DMACH_PCM0_TX, DMACH_PCM1_RX, @@ -105,13 +105,13 @@ u8 pdma1_peri[] = { DMACH_SLIMBUS5_TX, }; -struct dma_pl330_platdata exynos4_pdma1_pdata = { +static struct dma_pl330_platdata exynos4_pdma1_pdata = { .nr_valid_peri = ARRAY_SIZE(pdma1_peri), .peri_id = pdma1_peri, }; -AMBA_AHB_DEVICE(exynos4_pdma1, "dma-pl330.1", 0x00041330, EXYNOS4_PA_PDMA1, - {IRQ_PDMA1}, &exynos4_pdma1_pdata); +static AMBA_AHB_DEVICE(exynos4_pdma1, "dma-pl330.1", 0x00041330, + EXYNOS4_PA_PDMA1, {IRQ_PDMA1}, &exynos4_pdma1_pdata); static int __init exynos4_dma_init(void) { diff --git a/arch/arm/mach-exynos/include/mach/exynos4-clock.h b/arch/arm/mach-exynos/include/mach/exynos4-clock.h deleted file mode 100644 index a07fcbf55251..000000000000 --- a/arch/arm/mach-exynos/include/mach/exynos4-clock.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * linux/arch/arm/mach-exynos4/include/mach/exynos4-clock.h - * - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Header file for exynos4 clock support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_CLOCK_H -#define __ASM_ARCH_CLOCK_H __FILE__ - -#include <linux/clk.h> - -extern struct clk clk_sclk_hdmi27m; -extern struct clk clk_sclk_usbphy0; -extern struct clk clk_sclk_usbphy1; -extern struct clk clk_sclk_hdmiphy; - -extern struct clksrc_clk clk_sclk_apll; -extern struct clksrc_clk clk_mout_mpll; -extern struct clksrc_clk clk_aclk_133; -extern struct clksrc_clk clk_mout_epll; -extern struct clksrc_clk clk_sclk_vpll; - -extern struct clk *clkset_corebus_list[]; -extern struct clksrc_sources clkset_mout_corebus; - -extern struct clk *clkset_aclk_top_list[]; -extern struct clksrc_sources clkset_aclk; - -extern struct clk *clkset_group_list[]; -extern struct clksrc_sources clkset_group; - -extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable); -extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable); -extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable); - -#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h index 6c37ebe94829..1e4abd64a547 100644 --- a/arch/arm/mach-exynos/include/mach/regs-clock.h +++ b/arch/arm/mach-exynos/include/mach/regs-clock.h @@ -16,195 +16,247 @@ #include <plat/cpu.h> #include <mach/map.h> -#define S5P_CLKREG(x) (S5P_VA_CMU + (x)) - -#define S5P_CLKDIV_LEFTBUS S5P_CLKREG(0x04500) -#define S5P_CLKDIV_STAT_LEFTBUS S5P_CLKREG(0x04600) -#define S5P_CLKGATE_IP_LEFTBUS S5P_CLKREG(0x04800) - -#define S5P_CLKDIV_RIGHTBUS S5P_CLKREG(0x08500) -#define S5P_CLKDIV_STAT_RIGHTBUS S5P_CLKREG(0x08600) -#define S5P_CLKGATE_IP_RIGHTBUS S5P_CLKREG(0x08800) - -#define S5P_EPLL_LOCK S5P_CLKREG(0x0C010) -#define S5P_VPLL_LOCK S5P_CLKREG(0x0C020) - -#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110) -#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114) -#define S5P_VPLL_CON0 S5P_CLKREG(0x0C120) -#define S5P_VPLL_CON1 S5P_CLKREG(0x0C124) - -#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210) -#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214) -#define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220) -#define S5P_CLKSRC_TV S5P_CLKREG(0x0C224) -#define S5P_CLKSRC_MFC S5P_CLKREG(0x0C228) -#define S5P_CLKSRC_G3D S5P_CLKREG(0x0C22C) -#define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230) -#define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234) -#define S5P_CLKSRC_MAUDIO S5P_CLKREG(0x0C23C) -#define S5P_CLKSRC_FSYS S5P_CLKREG(0x0C240) -#define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250) -#define S5P_CLKSRC_PERIL1 S5P_CLKREG(0x0C254) - -#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310) -#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320) -#define S5P_CLKSRC_MASK_TV S5P_CLKREG(0x0C324) -#define S5P_CLKSRC_MASK_LCD0 S5P_CLKREG(0x0C334) -#define S5P_CLKSRC_MASK_MAUDIO S5P_CLKREG(0x0C33C) -#define S5P_CLKSRC_MASK_FSYS S5P_CLKREG(0x0C340) -#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350) -#define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354) - -#define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510) -#define S5P_CLKDIV_CAM S5P_CLKREG(0x0C520) -#define S5P_CLKDIV_TV S5P_CLKREG(0x0C524) -#define S5P_CLKDIV_MFC S5P_CLKREG(0x0C528) -#define S5P_CLKDIV_G3D S5P_CLKREG(0x0C52C) -#define S5P_CLKDIV_IMAGE S5P_CLKREG(0x0C530) -#define S5P_CLKDIV_LCD0 S5P_CLKREG(0x0C534) -#define S5P_CLKDIV_MAUDIO S5P_CLKREG(0x0C53C) -#define S5P_CLKDIV_FSYS0 S5P_CLKREG(0x0C540) -#define S5P_CLKDIV_FSYS1 S5P_CLKREG(0x0C544) -#define S5P_CLKDIV_FSYS2 S5P_CLKREG(0x0C548) -#define S5P_CLKDIV_FSYS3 S5P_CLKREG(0x0C54C) -#define S5P_CLKDIV_PERIL0 S5P_CLKREG(0x0C550) -#define S5P_CLKDIV_PERIL1 S5P_CLKREG(0x0C554) -#define S5P_CLKDIV_PERIL2 S5P_CLKREG(0x0C558) -#define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x0C55C) -#define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560) -#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564) -#define S5P_CLKDIV2_RATIO S5P_CLKREG(0x0C580) - -#define S5P_CLKDIV_STAT_TOP S5P_CLKREG(0x0C610) - -#define S5P_CLKGATE_SCLKCAM S5P_CLKREG(0x0C820) -#define S5P_CLKGATE_IP_CAM S5P_CLKREG(0x0C920) -#define S5P_CLKGATE_IP_TV S5P_CLKREG(0x0C924) -#define S5P_CLKGATE_IP_MFC S5P_CLKREG(0x0C928) -#define S5P_CLKGATE_IP_G3D S5P_CLKREG(0x0C92C) -#define S5P_CLKGATE_IP_IMAGE (soc_is_exynos4210() ? \ - S5P_CLKREG(0x0C930) : \ - S5P_CLKREG(0x04930)) -#define S5P_CLKGATE_IP_IMAGE_4210 S5P_CLKREG(0x0C930) -#define S5P_CLKGATE_IP_IMAGE_4212 S5P_CLKREG(0x04930) -#define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934) -#define S5P_CLKGATE_IP_FSYS S5P_CLKREG(0x0C940) -#define S5P_CLKGATE_IP_GPS S5P_CLKREG(0x0C94C) -#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950) -#define S5P_CLKGATE_IP_PERIR (soc_is_exynos4210() ? \ - S5P_CLKREG(0x0C960) : \ - S5P_CLKREG(0x08960)) -#define S5P_CLKGATE_IP_PERIR_4210 S5P_CLKREG(0x0C960) -#define S5P_CLKGATE_IP_PERIR_4212 S5P_CLKREG(0x08960) -#define S5P_CLKGATE_BLOCK S5P_CLKREG(0x0C970) - -#define S5P_CLKSRC_MASK_DMC S5P_CLKREG(0x10300) -#define S5P_CLKSRC_DMC S5P_CLKREG(0x10200) -#define S5P_CLKDIV_DMC0 S5P_CLKREG(0x10500) -#define S5P_CLKDIV_DMC1 S5P_CLKREG(0x10504) -#define S5P_CLKDIV_STAT_DMC0 S5P_CLKREG(0x10600) -#define S5P_CLKGATE_IP_DMC S5P_CLKREG(0x10900) - -#define S5P_APLL_LOCK S5P_CLKREG(0x14000) -#define S5P_MPLL_LOCK (soc_is_exynos4210() ? \ - S5P_CLKREG(0x14004) : \ - S5P_CLKREG(0x10008)) -#define S5P_APLL_CON0 S5P_CLKREG(0x14100) -#define S5P_APLL_CON1 S5P_CLKREG(0x14104) -#define S5P_MPLL_CON0 (soc_is_exynos4210() ? \ - S5P_CLKREG(0x14108) : \ - S5P_CLKREG(0x10108)) -#define S5P_MPLL_CON1 (soc_is_exynos4210() ? \ - S5P_CLKREG(0x1410C) : \ - S5P_CLKREG(0x1010C)) - -#define S5P_CLKSRC_CPU S5P_CLKREG(0x14200) -#define S5P_CLKMUX_STATCPU S5P_CLKREG(0x14400) - -#define S5P_CLKDIV_CPU S5P_CLKREG(0x14500) -#define S5P_CLKDIV_CPU1 S5P_CLKREG(0x14504) -#define S5P_CLKDIV_STATCPU S5P_CLKREG(0x14600) -#define S5P_CLKDIV_STATCPU1 S5P_CLKREG(0x14604) - -#define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800) -#define S5P_CLKGATE_IP_CPU S5P_CLKREG(0x14900) - -#define S5P_APLL_LOCKTIME (0x1C20) /* 300us */ - -#define S5P_APLLCON0_ENABLE_SHIFT (31) -#define S5P_APLLCON0_LOCKED_SHIFT (29) -#define S5P_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1) -#define S5P_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1) - -#define S5P_EPLLCON0_ENABLE_SHIFT (31) -#define S5P_EPLLCON0_LOCKED_SHIFT (29) - -#define S5P_VPLLCON0_ENABLE_SHIFT (31) -#define S5P_VPLLCON0_LOCKED_SHIFT (29) - -#define S5P_CLKSRC_CPU_MUXCORE_SHIFT (16) -#define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT) - -#define S5P_CLKDIV_CPU0_CORE_SHIFT (0) -#define S5P_CLKDIV_CPU0_CORE_MASK (0x7 << S5P_CLKDIV_CPU0_CORE_SHIFT) -#define S5P_CLKDIV_CPU0_COREM0_SHIFT (4) -#define S5P_CLKDIV_CPU0_COREM0_MASK (0x7 << S5P_CLKDIV_CPU0_COREM0_SHIFT) -#define S5P_CLKDIV_CPU0_COREM1_SHIFT (8) -#define S5P_CLKDIV_CPU0_COREM1_MASK (0x7 << S5P_CLKDIV_CPU0_COREM1_SHIFT) -#define S5P_CLKDIV_CPU0_PERIPH_SHIFT (12) -#define S5P_CLKDIV_CPU0_PERIPH_MASK (0x7 << S5P_CLKDIV_CPU0_PERIPH_SHIFT) -#define S5P_CLKDIV_CPU0_ATB_SHIFT (16) -#define S5P_CLKDIV_CPU0_ATB_MASK (0x7 << S5P_CLKDIV_CPU0_ATB_SHIFT) -#define S5P_CLKDIV_CPU0_PCLKDBG_SHIFT (20) -#define S5P_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT) -#define S5P_CLKDIV_CPU0_APLL_SHIFT (24) -#define S5P_CLKDIV_CPU0_APLL_MASK (0x7 << S5P_CLKDIV_CPU0_APLL_SHIFT) - -#define S5P_CLKDIV_DMC0_ACP_SHIFT (0) -#define S5P_CLKDIV_DMC0_ACP_MASK (0x7 << S5P_CLKDIV_DMC0_ACP_SHIFT) -#define S5P_CLKDIV_DMC0_ACPPCLK_SHIFT (4) -#define S5P_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT) -#define S5P_CLKDIV_DMC0_DPHY_SHIFT (8) -#define S5P_CLKDIV_DMC0_DPHY_MASK (0x7 << S5P_CLKDIV_DMC0_DPHY_SHIFT) -#define S5P_CLKDIV_DMC0_DMC_SHIFT (12) -#define S5P_CLKDIV_DMC0_DMC_MASK (0x7 << S5P_CLKDIV_DMC0_DMC_SHIFT) -#define S5P_CLKDIV_DMC0_DMCD_SHIFT (16) -#define S5P_CLKDIV_DMC0_DMCD_MASK (0x7 << S5P_CLKDIV_DMC0_DMCD_SHIFT) -#define S5P_CLKDIV_DMC0_DMCP_SHIFT (20) -#define S5P_CLKDIV_DMC0_DMCP_MASK (0x7 << S5P_CLKDIV_DMC0_DMCP_SHIFT) -#define S5P_CLKDIV_DMC0_COPY2_SHIFT (24) -#define S5P_CLKDIV_DMC0_COPY2_MASK (0x7 << S5P_CLKDIV_DMC0_COPY2_SHIFT) -#define S5P_CLKDIV_DMC0_CORETI_SHIFT (28) -#define S5P_CLKDIV_DMC0_CORETI_MASK (0x7 << S5P_CLKDIV_DMC0_CORETI_SHIFT) - -#define S5P_CLKDIV_TOP_ACLK200_SHIFT (0) -#define S5P_CLKDIV_TOP_ACLK200_MASK (0x7 << S5P_CLKDIV_TOP_ACLK200_SHIFT) -#define S5P_CLKDIV_TOP_ACLK100_SHIFT (4) -#define S5P_CLKDIV_TOP_ACLK100_MASK (0xf << S5P_CLKDIV_TOP_ACLK100_SHIFT) -#define S5P_CLKDIV_TOP_ACLK160_SHIFT (8) -#define S5P_CLKDIV_TOP_ACLK160_MASK (0x7 << S5P_CLKDIV_TOP_ACLK160_SHIFT) -#define S5P_CLKDIV_TOP_ACLK133_SHIFT (12) -#define S5P_CLKDIV_TOP_ACLK133_MASK (0x7 << S5P_CLKDIV_TOP_ACLK133_SHIFT) -#define S5P_CLKDIV_TOP_ONENAND_SHIFT (16) -#define S5P_CLKDIV_TOP_ONENAND_MASK (0x7 << S5P_CLKDIV_TOP_ONENAND_SHIFT) - -#define S5P_CLKDIV_BUS_GDLR_SHIFT (0) -#define S5P_CLKDIV_BUS_GDLR_MASK (0x7 << S5P_CLKDIV_BUS_GDLR_SHIFT) -#define S5P_CLKDIV_BUS_GPLR_SHIFT (4) -#define S5P_CLKDIV_BUS_GPLR_MASK (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT) +#define EXYNOS_CLKREG(x) (S5P_VA_CMU + (x)) + +#define EXYNOS4_CLKDIV_LEFTBUS EXYNOS_CLKREG(0x04500) +#define EXYNOS4_CLKDIV_STAT_LEFTBUS EXYNOS_CLKREG(0x04600) +#define EXYNOS4_CLKGATE_IP_LEFTBUS EXYNOS_CLKREG(0x04800) + +#define EXYNOS4_CLKDIV_RIGHTBUS EXYNOS_CLKREG(0x08500) +#define EXYNOS4_CLKDIV_STAT_RIGHTBUS EXYNOS_CLKREG(0x08600) +#define EXYNOS4_CLKGATE_IP_RIGHTBUS EXYNOS_CLKREG(0x08800) + +#define EXYNOS4_EPLL_LOCK EXYNOS_CLKREG(0x0C010) +#define EXYNOS4_VPLL_LOCK EXYNOS_CLKREG(0x0C020) + +#define EXYNOS4_EPLL_CON0 EXYNOS_CLKREG(0x0C110) +#define EXYNOS4_EPLL_CON1 EXYNOS_CLKREG(0x0C114) +#define EXYNOS4_VPLL_CON0 EXYNOS_CLKREG(0x0C120) +#define EXYNOS4_VPLL_CON1 EXYNOS_CLKREG(0x0C124) + +#define EXYNOS4_CLKSRC_TOP0 EXYNOS_CLKREG(0x0C210) +#define EXYNOS4_CLKSRC_TOP1 EXYNOS_CLKREG(0x0C214) +#define EXYNOS4_CLKSRC_CAM EXYNOS_CLKREG(0x0C220) +#define EXYNOS4_CLKSRC_TV EXYNOS_CLKREG(0x0C224) +#define EXYNOS4_CLKSRC_MFC EXYNOS_CLKREG(0x0C228) +#define EXYNOS4_CLKSRC_G3D EXYNOS_CLKREG(0x0C22C) +#define EXYNOS4_CLKSRC_IMAGE EXYNOS_CLKREG(0x0C230) +#define EXYNOS4_CLKSRC_LCD0 EXYNOS_CLKREG(0x0C234) +#define EXYNOS4_CLKSRC_MAUDIO EXYNOS_CLKREG(0x0C23C) +#define EXYNOS4_CLKSRC_FSYS EXYNOS_CLKREG(0x0C240) +#define EXYNOS4_CLKSRC_PERIL0 EXYNOS_CLKREG(0x0C250) +#define EXYNOS4_CLKSRC_PERIL1 EXYNOS_CLKREG(0x0C254) + +#define EXYNOS4_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x0C310) +#define EXYNOS4_CLKSRC_MASK_CAM EXYNOS_CLKREG(0x0C320) +#define EXYNOS4_CLKSRC_MASK_TV EXYNOS_CLKREG(0x0C324) +#define EXYNOS4_CLKSRC_MASK_LCD0 EXYNOS_CLKREG(0x0C334) +#define EXYNOS4_CLKSRC_MASK_MAUDIO EXYNOS_CLKREG(0x0C33C) +#define EXYNOS4_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x0C340) +#define EXYNOS4_CLKSRC_MASK_PERIL0 EXYNOS_CLKREG(0x0C350) +#define EXYNOS4_CLKSRC_MASK_PERIL1 EXYNOS_CLKREG(0x0C354) + +#define EXYNOS4_CLKDIV_TOP EXYNOS_CLKREG(0x0C510) +#define EXYNOS4_CLKDIV_CAM EXYNOS_CLKREG(0x0C520) +#define EXYNOS4_CLKDIV_TV EXYNOS_CLKREG(0x0C524) +#define EXYNOS4_CLKDIV_MFC EXYNOS_CLKREG(0x0C528) +#define EXYNOS4_CLKDIV_G3D EXYNOS_CLKREG(0x0C52C) +#define EXYNOS4_CLKDIV_IMAGE EXYNOS_CLKREG(0x0C530) +#define EXYNOS4_CLKDIV_LCD0 EXYNOS_CLKREG(0x0C534) +#define EXYNOS4_CLKDIV_MAUDIO EXYNOS_CLKREG(0x0C53C) +#define EXYNOS4_CLKDIV_FSYS0 EXYNOS_CLKREG(0x0C540) +#define EXYNOS4_CLKDIV_FSYS1 EXYNOS_CLKREG(0x0C544) +#define EXYNOS4_CLKDIV_FSYS2 EXYNOS_CLKREG(0x0C548) +#define EXYNOS4_CLKDIV_FSYS3 EXYNOS_CLKREG(0x0C54C) +#define EXYNOS4_CLKDIV_PERIL0 EXYNOS_CLKREG(0x0C550) +#define EXYNOS4_CLKDIV_PERIL1 EXYNOS_CLKREG(0x0C554) +#define EXYNOS4_CLKDIV_PERIL2 EXYNOS_CLKREG(0x0C558) +#define EXYNOS4_CLKDIV_PERIL3 EXYNOS_CLKREG(0x0C55C) +#define EXYNOS4_CLKDIV_PERIL4 EXYNOS_CLKREG(0x0C560) +#define EXYNOS4_CLKDIV_PERIL5 EXYNOS_CLKREG(0x0C564) +#define EXYNOS4_CLKDIV2_RATIO EXYNOS_CLKREG(0x0C580) + +#define EXYNOS4_CLKDIV_STAT_TOP EXYNOS_CLKREG(0x0C610) +#define EXYNOS4_CLKDIV_STAT_MFC EXYNOS_CLKREG(0x0C628) + +#define EXYNOS4_CLKGATE_SCLKCAM EXYNOS_CLKREG(0x0C820) +#define EXYNOS4_CLKGATE_IP_CAM EXYNOS_CLKREG(0x0C920) +#define EXYNOS4_CLKGATE_IP_TV EXYNOS_CLKREG(0x0C924) +#define EXYNOS4_CLKGATE_IP_MFC EXYNOS_CLKREG(0x0C928) +#define EXYNOS4_CLKGATE_IP_G3D EXYNOS_CLKREG(0x0C92C) +#define EXYNOS4_CLKGATE_IP_IMAGE (soc_is_exynos4210() ? \ + EXYNOS_CLKREG(0x0C930) : \ + EXYNOS_CLKREG(0x04930)) +#define EXYNOS4210_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x0C930) +#define EXYNOS4212_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x04930) +#define EXYNOS4_CLKGATE_IP_LCD0 EXYNOS_CLKREG(0x0C934) +#define EXYNOS4_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x0C940) +#define EXYNOS4_CLKGATE_IP_GPS EXYNOS_CLKREG(0x0C94C) +#define EXYNOS4_CLKGATE_IP_PERIL EXYNOS_CLKREG(0x0C950) +#define EXYNOS4_CLKGATE_IP_PERIR (soc_is_exynos4210() ? \ + EXYNOS_CLKREG(0x0C960) : \ + EXYNOS_CLKREG(0x08960)) +#define EXYNOS4210_CLKGATE_IP_PERIR EXYNOS_CLKREG(0x0C960) +#define EXYNOS4212_CLKGATE_IP_PERIR EXYNOS_CLKREG(0x08960) +#define EXYNOS4_CLKGATE_BLOCK EXYNOS_CLKREG(0x0C970) + +#define EXYNOS4_CLKSRC_MASK_DMC EXYNOS_CLKREG(0x10300) +#define EXYNOS4_CLKSRC_DMC EXYNOS_CLKREG(0x10200) +#define EXYNOS4_CLKDIV_DMC0 EXYNOS_CLKREG(0x10500) +#define EXYNOS4_CLKDIV_DMC1 EXYNOS_CLKREG(0x10504) +#define EXYNOS4_CLKDIV_STAT_DMC0 EXYNOS_CLKREG(0x10600) +#define EXYNOS4_CLKDIV_STAT_DMC1 EXYNOS_CLKREG(0x10604) +#define EXYNOS4_CLKGATE_IP_DMC EXYNOS_CLKREG(0x10900) + +#define EXYNOS4_DMC_PAUSE_CTRL EXYNOS_CLKREG(0x11094) +#define EXYNOS4_DMC_PAUSE_ENABLE (1 << 0) + +#define EXYNOS4_APLL_LOCK EXYNOS_CLKREG(0x14000) +#define EXYNOS4_MPLL_LOCK (soc_is_exynos4210() ? \ + EXYNOS_CLKREG(0x14004) : \ + EXYNOS_CLKREG(0x10008)) +#define EXYNOS4_APLL_CON0 EXYNOS_CLKREG(0x14100) +#define EXYNOS4_APLL_CON1 EXYNOS_CLKREG(0x14104) +#define EXYNOS4_MPLL_CON0 (soc_is_exynos4210() ? \ + EXYNOS_CLKREG(0x14108) : \ + EXYNOS_CLKREG(0x10108)) +#define EXYNOS4_MPLL_CON1 (soc_is_exynos4210() ? \ + EXYNOS_CLKREG(0x1410C) : \ + EXYNOS_CLKREG(0x1010C)) + +#define EXYNOS4_CLKSRC_CPU EXYNOS_CLKREG(0x14200) +#define EXYNOS4_CLKMUX_STATCPU EXYNOS_CLKREG(0x14400) + +#define EXYNOS4_CLKDIV_CPU EXYNOS_CLKREG(0x14500) +#define EXYNOS4_CLKDIV_CPU1 EXYNOS_CLKREG(0x14504) +#define EXYNOS4_CLKDIV_STATCPU EXYNOS_CLKREG(0x14600) +#define EXYNOS4_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x14604) + +#define EXYNOS4_CLKGATE_SCLKCPU EXYNOS_CLKREG(0x14800) +#define EXYNOS4_CLKGATE_IP_CPU EXYNOS_CLKREG(0x14900) + +#define EXYNOS4_APLL_LOCKTIME (0x1C20) /* 300us */ + +#define EXYNOS4_APLLCON0_ENABLE_SHIFT (31) +#define EXYNOS4_APLLCON0_LOCKED_SHIFT (29) +#define EXYNOS4_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1) +#define EXYNOS4_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1) + +#define EXYNOS4_EPLLCON0_ENABLE_SHIFT (31) +#define EXYNOS4_EPLLCON0_LOCKED_SHIFT (29) + +#define EXYNOS4_VPLLCON0_ENABLE_SHIFT (31) +#define EXYNOS4_VPLLCON0_LOCKED_SHIFT (29) + +#define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT (16) +#define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT) + +#define EXYNOS4_CLKDIV_CPU0_CORE_SHIFT (0) +#define EXYNOS4_CLKDIV_CPU0_CORE_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT) +#define EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT (4) +#define EXYNOS4_CLKDIV_CPU0_COREM0_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT) +#define EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT (8) +#define EXYNOS4_CLKDIV_CPU0_COREM1_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT) +#define EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT (12) +#define EXYNOS4_CLKDIV_CPU0_PERIPH_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT) +#define EXYNOS4_CLKDIV_CPU0_ATB_SHIFT (16) +#define EXYNOS4_CLKDIV_CPU0_ATB_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT) +#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT (20) +#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT) +#define EXYNOS4_CLKDIV_CPU0_APLL_SHIFT (24) +#define EXYNOS4_CLKDIV_CPU0_APLL_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT) +#define EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT 28 +#define EXYNOS4_CLKDIV_CPU0_CORE2_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT) + +#define EXYNOS4_CLKDIV_CPU1_COPY_SHIFT 0 +#define EXYNOS4_CLKDIV_CPU1_COPY_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT) +#define EXYNOS4_CLKDIV_CPU1_HPM_SHIFT 4 +#define EXYNOS4_CLKDIV_CPU1_HPM_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT) +#define EXYNOS4_CLKDIV_CPU1_CORES_SHIFT 8 +#define EXYNOS4_CLKDIV_CPU1_CORES_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_CORES_SHIFT) + +#define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT (0) +#define EXYNOS4_CLKDIV_DMC0_ACP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) +#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT (4) +#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT) +#define EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT (8) +#define EXYNOS4_CLKDIV_DMC0_DPHY_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT) +#define EXYNOS4_CLKDIV_DMC0_DMC_SHIFT (12) +#define EXYNOS4_CLKDIV_DMC0_DMC_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMC_SHIFT) +#define EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT (16) +#define EXYNOS4_CLKDIV_DMC0_DMCD_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT) +#define EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT (20) +#define EXYNOS4_CLKDIV_DMC0_DMCP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT) +#define EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT (24) +#define EXYNOS4_CLKDIV_DMC0_COPY2_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT) +#define EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT (28) +#define EXYNOS4_CLKDIV_DMC0_CORETI_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT) + +#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT (0) +#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK (0xf << EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT) +#define EXYNOS4_CLKDIV_DMC1_C2C_SHIFT (4) +#define EXYNOS4_CLKDIV_DMC1_C2C_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2C_SHIFT) +#define EXYNOS4_CLKDIV_DMC1_PWI_SHIFT (8) +#define EXYNOS4_CLKDIV_DMC1_PWI_MASK (0xf << EXYNOS4_CLKDIV_DMC1_PWI_SHIFT) +#define EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT (12) +#define EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT) +#define EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT (16) +#define EXYNOS4_CLKDIV_DMC1_DVSEM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT) +#define EXYNOS4_CLKDIV_DMC1_DPM_SHIFT (24) +#define EXYNOS4_CLKDIV_DMC1_DPM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DPM_SHIFT) + +#define EXYNOS4_CLKDIV_MFC_SHIFT (0) +#define EXYNOS4_CLKDIV_MFC_MASK (0x7 << EXYNOS4_CLKDIV_MFC_SHIFT) + +#define EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT (0) +#define EXYNOS4_CLKDIV_TOP_ACLK200_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT) +#define EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT (4) +#define EXYNOS4_CLKDIV_TOP_ACLK100_MASK (0xF << EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT) +#define EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT (8) +#define EXYNOS4_CLKDIV_TOP_ACLK160_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT) +#define EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT (12) +#define EXYNOS4_CLKDIV_TOP_ACLK133_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT) +#define EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT (16) +#define EXYNOS4_CLKDIV_TOP_ONENAND_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT) +#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT (20) +#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT) +#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT (24) +#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT) + +#define EXYNOS4_CLKDIV_BUS_GDLR_SHIFT (0) +#define EXYNOS4_CLKDIV_BUS_GDLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) +#define EXYNOS4_CLKDIV_BUS_GPLR_SHIFT (4) +#define EXYNOS4_CLKDIV_BUS_GPLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT) + +#define EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT (0) +#define EXYNOS4_CLKDIV_CAM_FIMC0_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT) +#define EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT (4) +#define EXYNOS4_CLKDIV_CAM_FIMC1_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT) +#define EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT (8) +#define EXYNOS4_CLKDIV_CAM_FIMC2_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT) +#define EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT (12) +#define EXYNOS4_CLKDIV_CAM_FIMC3_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT) /* Only for EXYNOS4210 */ -#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238) -#define S5P_CLKSRC_MASK_LCD1 S5P_CLKREG(0x0C338) -#define S5P_CLKDIV_LCD1 S5P_CLKREG(0x0C538) -#define S5P_CLKGATE_IP_LCD1 S5P_CLKREG(0x0C938) +#define EXYNOS4210_CLKSRC_LCD1 EXYNOS_CLKREG(0x0C238) +#define EXYNOS4210_CLKSRC_MASK_LCD1 EXYNOS_CLKREG(0x0C338) +#define EXYNOS4210_CLKDIV_LCD1 EXYNOS_CLKREG(0x0C538) +#define EXYNOS4210_CLKGATE_IP_LCD1 EXYNOS_CLKREG(0x0C938) + +/* Only for EXYNOS4212 */ + +#define EXYNOS4_CLKDIV_CAM1 EXYNOS_CLKREG(0x0C568) + +#define EXYNOS4_CLKDIV_STAT_CAM1 EXYNOS_CLKREG(0x0C668) + +#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0) +#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT) /* Compatibility defines and inclusion */ #include <mach/regs-pmu.h> -#define S5P_EPLL_CON S5P_EPLL_CON0 +#define S5P_EPLL_CON EXYNOS4_EPLL_CON0 #endif /* __ASM_ARCH_REGS_CLOCK_H */ diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c index 0679b8ad2d1e..3ec3ccf9f35c 100644 --- a/arch/arm/mach-exynos/mach-origen.c +++ b/arch/arm/mach-exynos/mach-origen.c @@ -412,7 +412,7 @@ static struct max8997_regulator_data __initdata origen_max8997_regulators[] = { { MAX8997_BUCK7, &max8997_buck7_data }, }; -struct max8997_platform_data __initdata origen_max8997_pdata = { +static struct max8997_platform_data __initdata origen_max8997_pdata = { .num_regulators = ARRAY_SIZE(origen_max8997_regulators), .regulators = origen_max8997_regulators, diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c index 38939956c34f..5ca91ec12642 100644 --- a/arch/arm/mach-exynos/mach-universal_c210.c +++ b/arch/arm/mach-exynos/mach-universal_c210.c @@ -999,7 +999,7 @@ static void __init universal_map_io(void) s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs)); } -void s5p_tv_setup(void) +static void s5p_tv_setup(void) { /* direct HPD to HDMI chip */ gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug"); diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index 481682745e7d..428cfeb57724 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -38,29 +38,29 @@ #include <mach/pmu.h> static struct sleep_save exynos4_set_clksrc[] = { - { .reg = S5P_CLKSRC_MASK_TOP , .val = 0x00000001, }, - { .reg = S5P_CLKSRC_MASK_CAM , .val = 0x11111111, }, - { .reg = S5P_CLKSRC_MASK_TV , .val = 0x00000111, }, - { .reg = S5P_CLKSRC_MASK_LCD0 , .val = 0x00001111, }, - { .reg = S5P_CLKSRC_MASK_MAUDIO , .val = 0x00000001, }, - { .reg = S5P_CLKSRC_MASK_FSYS , .val = 0x01011111, }, - { .reg = S5P_CLKSRC_MASK_PERIL0 , .val = 0x01111111, }, - { .reg = S5P_CLKSRC_MASK_PERIL1 , .val = 0x01110111, }, - { .reg = S5P_CLKSRC_MASK_DMC , .val = 0x00010000, }, + { .reg = EXYNOS4_CLKSRC_MASK_TOP , .val = 0x00000001, }, + { .reg = EXYNOS4_CLKSRC_MASK_CAM , .val = 0x11111111, }, + { .reg = EXYNOS4_CLKSRC_MASK_TV , .val = 0x00000111, }, + { .reg = EXYNOS4_CLKSRC_MASK_LCD0 , .val = 0x00001111, }, + { .reg = EXYNOS4_CLKSRC_MASK_MAUDIO , .val = 0x00000001, }, + { .reg = EXYNOS4_CLKSRC_MASK_FSYS , .val = 0x01011111, }, + { .reg = EXYNOS4_CLKSRC_MASK_PERIL0 , .val = 0x01111111, }, + { .reg = EXYNOS4_CLKSRC_MASK_PERIL1 , .val = 0x01110111, }, + { .reg = EXYNOS4_CLKSRC_MASK_DMC , .val = 0x00010000, }, }; static struct sleep_save exynos4210_set_clksrc[] = { - { .reg = S5P_CLKSRC_MASK_LCD1 , .val = 0x00001111, }, + { .reg = EXYNOS4210_CLKSRC_MASK_LCD1 , .val = 0x00001111, }, }; static struct sleep_save exynos4_epll_save[] = { - SAVE_ITEM(S5P_EPLL_CON0), - SAVE_ITEM(S5P_EPLL_CON1), + SAVE_ITEM(EXYNOS4_EPLL_CON0), + SAVE_ITEM(EXYNOS4_EPLL_CON1), }; static struct sleep_save exynos4_vpll_save[] = { - SAVE_ITEM(S5P_VPLL_CON0), - SAVE_ITEM(S5P_VPLL_CON1), + SAVE_ITEM(EXYNOS4_VPLL_CON0), + SAVE_ITEM(EXYNOS4_VPLL_CON1), }; static struct sleep_save exynos4_core_save[] = { @@ -231,7 +231,7 @@ static void exynos4_restore_pll(void) locktime = (3000 / pll_in_rate) * p_div; lockcnt = locktime * 10000 / (10000 / pll_in_rate); - __raw_writel(lockcnt, S5P_EPLL_LOCK); + __raw_writel(lockcnt, EXYNOS4_EPLL_LOCK); s3c_pm_do_restore_core(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save)); @@ -249,7 +249,7 @@ static void exynos4_restore_pll(void) locktime = 750; lockcnt = locktime * 10000 / (10000 / pll_in_rate); - __raw_writel(lockcnt, S5P_VPLL_LOCK); + __raw_writel(lockcnt, EXYNOS4_VPLL_LOCK); s3c_pm_do_restore_core(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save)); @@ -260,14 +260,14 @@ static void exynos4_restore_pll(void) do { if (epll_wait) { - pll_con = __raw_readl(S5P_EPLL_CON0); - if (pll_con & (1 << S5P_EPLLCON0_LOCKED_SHIFT)) + pll_con = __raw_readl(EXYNOS4_EPLL_CON0); + if (pll_con & (1 << EXYNOS4_EPLLCON0_LOCKED_SHIFT)) epll_wait = 0; } if (vpll_wait) { - pll_con = __raw_readl(S5P_VPLL_CON0); - if (pll_con & (1 << S5P_VPLLCON0_LOCKED_SHIFT)) + pll_con = __raw_readl(EXYNOS4_VPLL_CON0); + if (pll_con & (1 << EXYNOS4_VPLLCON0_LOCKED_SHIFT)) vpll_wait = 0; } } while (epll_wait || vpll_wait); diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c index 41245a603981..6b21ba107eab 100644 --- a/arch/arm/mach-s3c2410/mach-h1940.c +++ b/arch/arm/mach-s3c2410/mach-h1940.c @@ -162,7 +162,7 @@ static int h1940_gpiolib_latch_get(struct gpio_chip *chip, return (latch_state >> (offset + 16)) & 1; } -struct gpio_chip h1940_latch_gpiochip = { +static struct gpio_chip h1940_latch_gpiochip = { .base = H1940_LATCH_GPIO(0), .owner = THIS_MODULE, .label = "H1940_LATCH", @@ -304,7 +304,7 @@ static const struct s3c_adc_bat_thresh bat_lut_acin[] = { { .volt = 3841, .cur = 0, .level = 0}, }; -int h1940_bat_init(void) +static int h1940_bat_init(void) { int ret; @@ -317,17 +317,17 @@ int h1940_bat_init(void) } -void h1940_bat_exit(void) +static void h1940_bat_exit(void) { gpio_free(H1940_LATCH_SM803_ENABLE); } -void h1940_enable_charger(void) +static void h1940_enable_charger(void) { gpio_set_value(H1940_LATCH_SM803_ENABLE, 1); } -void h1940_disable_charger(void) +static void h1940_disable_charger(void) { gpio_set_value(H1940_LATCH_SM803_ENABLE, 0); } @@ -364,7 +364,7 @@ static struct platform_device h1940_battery = { }, }; -DEFINE_SPINLOCK(h1940_blink_spin); +static DEFINE_SPINLOCK(h1940_blink_spin); int h1940_led_blink_set(unsigned gpio, int state, unsigned long *delay_on, unsigned long *delay_off) diff --git a/arch/arm/mach-s3c2416/clock.c b/arch/arm/mach-s3c2416/clock.c index 59f54d1d7f8b..e01490db0993 100644 --- a/arch/arm/mach-s3c2416/clock.c +++ b/arch/arm/mach-s3c2416/clock.c @@ -132,12 +132,6 @@ static struct clk hsmmc0_clk = { .ctrlbit = S3C2416_HCLKCON_HSMMC0, }; -void __init_or_cpufreq s3c2416_setup_clocks(void) -{ - s3c2443_common_setup_clocks(s3c2416_get_pll); -} - - static struct clksrc_clk *clksrcs[] __initdata = { &hsspi_eplldiv, &hsspi_mux, diff --git a/arch/arm/mach-s3c2416/mach-smdk2416.c b/arch/arm/mach-s3c2416/mach-smdk2416.c index eebe1e72b93e..30a44f806e01 100644 --- a/arch/arm/mach-s3c2416/mach-smdk2416.c +++ b/arch/arm/mach-s3c2416/mach-smdk2416.c @@ -125,7 +125,7 @@ static struct s3c2410_uartcfg smdk2416_uartcfgs[] __initdata = { } }; -void smdk2416_hsudc_gpio_init(void) +static void smdk2416_hsudc_gpio_init(void) { s3c_gpio_setpull(S3C2410_GPH(14), S3C_GPIO_PULL_UP); s3c_gpio_setpull(S3C2410_GPF(2), S3C_GPIO_PULL_NONE); @@ -133,20 +133,20 @@ void smdk2416_hsudc_gpio_init(void) s3c2410_modify_misccr(S3C2416_MISCCR_SEL_SUSPND, 0); } -void smdk2416_hsudc_gpio_uninit(void) +static void smdk2416_hsudc_gpio_uninit(void) { s3c2410_modify_misccr(S3C2416_MISCCR_SEL_SUSPND, 1); s3c_gpio_setpull(S3C2410_GPH(14), S3C_GPIO_PULL_NONE); s3c_gpio_cfgpin(S3C2410_GPH(14), S3C_GPIO_SFN(0)); } -struct s3c24xx_hsudc_platdata smdk2416_hsudc_platdata = { +static struct s3c24xx_hsudc_platdata smdk2416_hsudc_platdata = { .epnum = 9, .gpio_init = smdk2416_hsudc_gpio_init, .gpio_uninit = smdk2416_hsudc_gpio_uninit, }; -struct s3c_fb_pd_win smdk2416_fb_win[] = { +static struct s3c_fb_pd_win smdk2416_fb_win[] = { [0] = { /* think this is the same as the smdk6410 */ .win_mode = { diff --git a/arch/arm/mach-s3c2440/mach-gta02.c b/arch/arm/mach-s3c2440/mach-gta02.c index 9a4a5bc008e6..cfd20202e944 100644 --- a/arch/arm/mach-s3c2440/mach-gta02.c +++ b/arch/arm/mach-s3c2440/mach-gta02.c @@ -258,7 +258,7 @@ static struct pcf50633_bl_platform_data gta02_backlight_data = { .ramp_time = 5, }; -struct pcf50633_platform_data gta02_pcf_pdata = { +static struct pcf50633_platform_data gta02_pcf_pdata = { .resumers = { [0] = PCF50633_INT1_USBINS | PCF50633_INT1_USBREM | @@ -404,7 +404,7 @@ static struct platform_device gta02_nor_flash = { }; -struct platform_device s3c24xx_pwm_device = { +static struct platform_device s3c24xx_pwm_device = { .name = "s3c24xx_pwm", .num_resources = 0, }; diff --git a/arch/arm/mach-s3c2440/mach-rx1950.c b/arch/arm/mach-s3c2440/mach-rx1950.c index 6f68abf44fab..200debb4c72d 100644 --- a/arch/arm/mach-s3c2440/mach-rx1950.c +++ b/arch/arm/mach-s3c2440/mach-rx1950.c @@ -217,7 +217,7 @@ static const struct s3c_adc_bat_thresh bat_lut_acin[] = { { .volt = 3820, .cur = 0, .level = 0}, }; -int rx1950_bat_init(void) +static int rx1950_bat_init(void) { int ret; @@ -236,25 +236,25 @@ err_gpio1: return ret; } -void rx1950_bat_exit(void) +static void rx1950_bat_exit(void) { gpio_free(S3C2410_GPJ(2)); gpio_free(S3C2410_GPJ(3)); } -void rx1950_enable_charger(void) +static void rx1950_enable_charger(void) { gpio_direction_output(S3C2410_GPJ(2), 1); gpio_direction_output(S3C2410_GPJ(3), 1); } -void rx1950_disable_charger(void) +static void rx1950_disable_charger(void) { gpio_direction_output(S3C2410_GPJ(2), 0); gpio_direction_output(S3C2410_GPJ(3), 0); } -DEFINE_SPINLOCK(rx1950_blink_spin); +static DEFINE_SPINLOCK(rx1950_blink_spin); static int rx1950_led_blink_set(unsigned gpio, int state, unsigned long *delay_on, unsigned long *delay_off) @@ -382,7 +382,7 @@ static struct s3c2410fb_mach_info rx1950_lcd_cfg = { static struct pwm_device *lcd_pwm; -void rx1950_lcd_power(int enable) +static void rx1950_lcd_power(int enable) { int i; static int enabled; diff --git a/arch/arm/mach-s3c64xx/common.h b/arch/arm/mach-s3c64xx/common.h index 5eb9c9a7d73b..7a10be629aba 100644 --- a/arch/arm/mach-s3c64xx/common.h +++ b/arch/arm/mach-s3c64xx/common.h @@ -25,8 +25,6 @@ void s3c64xx_setup_clocks(void); void s3c64xx_restart(char mode, const char *cmd); -extern struct syscore_ops s3c64xx_irq_syscore_ops; - #ifdef CONFIG_CPU_S3C6400 extern int s3c6400_init(void); diff --git a/arch/arm/mach-s3c64xx/irq-pm.c b/arch/arm/mach-s3c64xx/irq-pm.c index 8bec61e242c7..0c7e1d960ca4 100644 --- a/arch/arm/mach-s3c64xx/irq-pm.c +++ b/arch/arm/mach-s3c64xx/irq-pm.c @@ -96,7 +96,7 @@ static void s3c64xx_irq_pm_resume(void) S3C_PMDBG("%s: IRQ configuration restored\n", __func__); } -struct syscore_ops s3c64xx_irq_syscore_ops = { +static struct syscore_ops s3c64xx_irq_syscore_ops = { .suspend = s3c64xx_irq_pm_suspend, .resume = s3c64xx_irq_pm_resume, }; diff --git a/arch/arm/mach-s5p64x0/clock.c b/arch/arm/mach-s5p64x0/clock.c index 241d0e645c85..57e718957ef3 100644 --- a/arch/arm/mach-s5p64x0/clock.c +++ b/arch/arm/mach-s5p64x0/clock.c @@ -73,7 +73,7 @@ static const u32 clock_table[][3] = { {L2 * 1000, (3 << ARM_DIV_RATIO_SHIFT), (0 << S5P64X0_CLKDIV0_HCLK_SHIFT)}, }; -unsigned long s5p64x0_armclk_get_rate(struct clk *clk) +static unsigned long s5p64x0_armclk_get_rate(struct clk *clk) { unsigned long rate = clk_get_rate(clk->parent); u32 clkdiv; @@ -84,7 +84,8 @@ unsigned long s5p64x0_armclk_get_rate(struct clk *clk) return rate / (clkdiv + 1); } -unsigned long s5p64x0_armclk_round_rate(struct clk *clk, unsigned long rate) +static unsigned long s5p64x0_armclk_round_rate(struct clk *clk, + unsigned long rate) { u32 iter; @@ -96,7 +97,7 @@ unsigned long s5p64x0_armclk_round_rate(struct clk *clk, unsigned long rate) return clock_table[ARRAY_SIZE(clock_table) - 1][0]; } -int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate) +static int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate) { u32 round_tmp; u32 iter; @@ -148,7 +149,7 @@ int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate) return 0; } -struct clk_ops s5p64x0_clkarm_ops = { +static struct clk_ops s5p64x0_clkarm_ops = { .get_rate = s5p64x0_armclk_get_rate, .set_rate = s5p64x0_armclk_set_rate, .round_rate = s5p64x0_armclk_round_rate, @@ -173,7 +174,7 @@ struct clksrc_clk clk_dout_mpll = { .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 4, .size = 1 }, }; -struct clk *clkset_hclk_low_list[] = { +static struct clk *clkset_hclk_low_list[] = { &clk_mout_apll.clk, &clk_mout_mpll.clk, }; diff --git a/arch/arm/mach-s5p64x0/dma.c b/arch/arm/mach-s5p64x0/dma.c index f7f68ad77910..2ee5dc069b37 100644 --- a/arch/arm/mach-s5p64x0/dma.c +++ b/arch/arm/mach-s5p64x0/dma.c @@ -38,7 +38,7 @@ static u64 dma_dmamask = DMA_BIT_MASK(32); -u8 s5p6440_pdma_peri[] = { +static u8 s5p6440_pdma_peri[] = { DMACH_UART0_RX, DMACH_UART0_TX, DMACH_UART1_RX, @@ -63,12 +63,12 @@ u8 s5p6440_pdma_peri[] = { DMACH_SPI1_RX, }; -struct dma_pl330_platdata s5p6440_pdma_pdata = { +static struct dma_pl330_platdata s5p6440_pdma_pdata = { .nr_valid_peri = ARRAY_SIZE(s5p6440_pdma_peri), .peri_id = s5p6440_pdma_peri, }; -u8 s5p6450_pdma_peri[] = { +static u8 s5p6450_pdma_peri[] = { DMACH_UART0_RX, DMACH_UART0_TX, DMACH_UART1_RX, @@ -103,13 +103,13 @@ u8 s5p6450_pdma_peri[] = { DMACH_UART5_TX, }; -struct dma_pl330_platdata s5p6450_pdma_pdata = { +static struct dma_pl330_platdata s5p6450_pdma_pdata = { .nr_valid_peri = ARRAY_SIZE(s5p6450_pdma_peri), .peri_id = s5p6450_pdma_peri, }; -AMBA_AHB_DEVICE(s5p64x0_pdma, "dma-pl330", 0x00041330, S5P64X0_PA_PDMA, - {IRQ_DMA0}, NULL); +static AMBA_AHB_DEVICE(s5p64x0_pdma, "dma-pl330", 0x00041330, + S5P64X0_PA_PDMA, {IRQ_DMA0}, NULL); static int __init s5p64x0_dma_init(void) { diff --git a/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h b/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h index ff85b4b6e8d9..0ef47d1b7670 100644 --- a/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h +++ b/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h @@ -22,16 +22,9 @@ extern struct clksrc_clk clk_mout_epll; extern int s5p64x0_epll_enable(struct clk *clk, int enable); extern unsigned long s5p64x0_epll_get_rate(struct clk *clk); -extern unsigned long s5p64x0_armclk_get_rate(struct clk *clk); -extern unsigned long s5p64x0_armclk_round_rate(struct clk *clk, unsigned long rate); -extern int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate); - -extern struct clk_ops s5p64x0_clkarm_ops; - extern struct clksrc_clk clk_armclk; extern struct clksrc_clk clk_dout_mpll; -extern struct clk *clkset_hclk_low_list[]; extern struct clksrc_sources clkset_hclk_low; extern int s5p64x0_pclk_ctrl(struct clk *clk, int enable); diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c index 247194dd366c..16eca4ea2010 100644 --- a/arch/arm/mach-s5pc100/clock.c +++ b/arch/arm/mach-s5pc100/clock.c @@ -170,7 +170,7 @@ static struct clk *clk_src_mout_am_list[] = { [1] = &clk_div_apll2.clk, }; -struct clksrc_sources clk_src_mout_am = { +static struct clksrc_sources clk_src_mout_am = { .sources = clk_src_mout_am_list, .nr_sources = ARRAY_SIZE(clk_src_mout_am_list), }; @@ -212,7 +212,7 @@ static struct clk *clk_src_mout_onenand_list[] = { [1] = &clk_div_d1_bus.clk, }; -struct clksrc_sources clk_src_mout_onenand = { +static struct clksrc_sources clk_src_mout_onenand = { .sources = clk_src_mout_onenand_list, .nr_sources = ARRAY_SIZE(clk_src_mout_onenand_list), }; @@ -756,7 +756,7 @@ static struct clk *clk_src_group1_list[] = { [3] = &clk_mout_hpll.clk, }; -struct clksrc_sources clk_src_group1 = { +static struct clksrc_sources clk_src_group1 = { .sources = clk_src_group1_list, .nr_sources = ARRAY_SIZE(clk_src_group1_list), }; @@ -766,7 +766,7 @@ static struct clk *clk_src_group2_list[] = { [1] = &clk_div_mpll.clk, }; -struct clksrc_sources clk_src_group2 = { +static struct clksrc_sources clk_src_group2 = { .sources = clk_src_group2_list, .nr_sources = ARRAY_SIZE(clk_src_group2_list), }; @@ -780,7 +780,7 @@ static struct clk *clk_src_group3_list[] = { [5] = &clk_mout_hpll.clk, }; -struct clksrc_sources clk_src_group3 = { +static struct clksrc_sources clk_src_group3 = { .sources = clk_src_group3_list, .nr_sources = ARRAY_SIZE(clk_src_group3_list), }; @@ -806,7 +806,7 @@ static struct clk *clk_src_group4_list[] = { [5] = &clk_mout_hpll.clk, }; -struct clksrc_sources clk_src_group4 = { +static struct clksrc_sources clk_src_group4 = { .sources = clk_src_group4_list, .nr_sources = ARRAY_SIZE(clk_src_group4_list), }; @@ -831,7 +831,7 @@ static struct clk *clk_src_group5_list[] = { [4] = &clk_mout_hpll.clk, }; -struct clksrc_sources clk_src_group5 = { +static struct clksrc_sources clk_src_group5 = { .sources = clk_src_group5_list, .nr_sources = ARRAY_SIZE(clk_src_group5_list), }; @@ -854,7 +854,7 @@ static struct clk *clk_src_group6_list[] = { [2] = &clk_div_hdmi.clk, }; -struct clksrc_sources clk_src_group6 = { +static struct clksrc_sources clk_src_group6 = { .sources = clk_src_group6_list, .nr_sources = ARRAY_SIZE(clk_src_group6_list), }; @@ -866,7 +866,7 @@ static struct clk *clk_src_group7_list[] = { [3] = &clk_vclk54m, }; -struct clksrc_sources clk_src_group7 = { +static struct clksrc_sources clk_src_group7 = { .sources = clk_src_group7_list, .nr_sources = ARRAY_SIZE(clk_src_group7_list), }; @@ -877,7 +877,7 @@ static struct clk *clk_src_mmc0_list[] = { [2] = &clk_fin_epll, }; -struct clksrc_sources clk_src_mmc0 = { +static struct clksrc_sources clk_src_mmc0 = { .sources = clk_src_mmc0_list, .nr_sources = ARRAY_SIZE(clk_src_mmc0_list), }; @@ -889,7 +889,7 @@ static struct clk *clk_src_mmc12_list[] = { [3] = &clk_mout_hpll.clk, }; -struct clksrc_sources clk_src_mmc12 = { +static struct clksrc_sources clk_src_mmc12 = { .sources = clk_src_mmc12_list, .nr_sources = ARRAY_SIZE(clk_src_mmc12_list), }; @@ -901,7 +901,7 @@ static struct clk *clk_src_irda_usb_list[] = { [3] = &clk_mout_hpll.clk, }; -struct clksrc_sources clk_src_irda_usb = { +static struct clksrc_sources clk_src_irda_usb = { .sources = clk_src_irda_usb_list, .nr_sources = ARRAY_SIZE(clk_src_irda_usb_list), }; @@ -912,7 +912,7 @@ static struct clk *clk_src_pwi_list[] = { [2] = &clk_div_mpll.clk, }; -struct clksrc_sources clk_src_pwi = { +static struct clksrc_sources clk_src_pwi = { .sources = clk_src_pwi_list, .nr_sources = ARRAY_SIZE(clk_src_pwi_list), }; @@ -923,7 +923,7 @@ static struct clk *clk_sclk_spdif_list[] = { [2] = &clk_sclk_audio2.clk, }; -struct clksrc_sources clk_src_sclk_spdif = { +static struct clksrc_sources clk_src_sclk_spdif = { .sources = clk_sclk_spdif_list, .nr_sources = ARRAY_SIZE(clk_sclk_spdif_list), }; diff --git a/arch/arm/mach-s5pc100/dma.c b/arch/arm/mach-s5pc100/dma.c index 96b1ab3dcd48..afd8db2d5991 100644 --- a/arch/arm/mach-s5pc100/dma.c +++ b/arch/arm/mach-s5pc100/dma.c @@ -35,7 +35,7 @@ static u64 dma_dmamask = DMA_BIT_MASK(32); -u8 pdma0_peri[] = { +static u8 pdma0_peri[] = { DMACH_UART0_RX, DMACH_UART0_TX, DMACH_UART1_RX, @@ -68,15 +68,15 @@ u8 pdma0_peri[] = { DMACH_HSI_TX, }; -struct dma_pl330_platdata s5pc100_pdma0_pdata = { +static struct dma_pl330_platdata s5pc100_pdma0_pdata = { .nr_valid_peri = ARRAY_SIZE(pdma0_peri), .peri_id = pdma0_peri, }; -AMBA_AHB_DEVICE(s5pc100_pdma0, "dma-pl330.0", 0x00041330, S5PC100_PA_PDMA0, - {IRQ_PDMA0}, &s5pc100_pdma0_pdata); +static AMBA_AHB_DEVICE(s5pc100_pdma0, "dma-pl330.0", 0x00041330, + S5PC100_PA_PDMA0, {IRQ_PDMA0}, &s5pc100_pdma0_pdata); -u8 pdma1_peri[] = { +static u8 pdma1_peri[] = { DMACH_UART0_RX, DMACH_UART0_TX, DMACH_UART1_RX, @@ -109,13 +109,13 @@ u8 pdma1_peri[] = { DMACH_MSM_REQ3, }; -struct dma_pl330_platdata s5pc100_pdma1_pdata = { +static struct dma_pl330_platdata s5pc100_pdma1_pdata = { .nr_valid_peri = ARRAY_SIZE(pdma1_peri), .peri_id = pdma1_peri, }; -AMBA_AHB_DEVICE(s5pc100_pdma1, "dma-pl330.1", 0x00041330, S5PC100_PA_PDMA1, - {IRQ_PDMA1}, &s5pc100_pdma1_pdata); +static AMBA_AHB_DEVICE(s5pc100_pdma1, "dma-pl330.1", 0x00041330, + S5PC100_PA_PDMA1, {IRQ_PDMA1}, &s5pc100_pdma1_pdata); static int __init s5pc100_dma_init(void) { diff --git a/arch/arm/mach-s5pv210/dma.c b/arch/arm/mach-s5pv210/dma.c index f6885d247d14..86ce62f66190 100644 --- a/arch/arm/mach-s5pv210/dma.c +++ b/arch/arm/mach-s5pv210/dma.c @@ -35,7 +35,7 @@ static u64 dma_dmamask = DMA_BIT_MASK(32); -u8 pdma0_peri[] = { +static u8 pdma0_peri[] = { DMACH_UART0_RX, DMACH_UART0_TX, DMACH_UART1_RX, @@ -66,15 +66,15 @@ u8 pdma0_peri[] = { DMACH_SPDIF, }; -struct dma_pl330_platdata s5pv210_pdma0_pdata = { +static struct dma_pl330_platdata s5pv210_pdma0_pdata = { .nr_valid_peri = ARRAY_SIZE(pdma0_peri), .peri_id = pdma0_peri, }; -AMBA_AHB_DEVICE(s5pv210_pdma0, "dma-pl330.0", 0x00041330, S5PV210_PA_PDMA0, - {IRQ_PDMA0}, &s5pv210_pdma0_pdata); +static AMBA_AHB_DEVICE(s5pv210_pdma0, "dma-pl330.0", 0x00041330, + S5PV210_PA_PDMA0, {IRQ_PDMA0}, &s5pv210_pdma0_pdata); -u8 pdma1_peri[] = { +static u8 pdma1_peri[] = { DMACH_UART0_RX, DMACH_UART0_TX, DMACH_UART1_RX, @@ -109,13 +109,13 @@ u8 pdma1_peri[] = { DMACH_PCM2_TX, }; -struct dma_pl330_platdata s5pv210_pdma1_pdata = { +static struct dma_pl330_platdata s5pv210_pdma1_pdata = { .nr_valid_peri = ARRAY_SIZE(pdma1_peri), .peri_id = pdma1_peri, }; -AMBA_AHB_DEVICE(s5pv210_pdma1, "dma-pl330.1", 0x00041330, S5PV210_PA_PDMA1, - {IRQ_PDMA1}, &s5pv210_pdma1_pdata); +static AMBA_AHB_DEVICE(s5pv210_pdma1, "dma-pl330.1", 0x00041330, + S5PV210_PA_PDMA1, {IRQ_PDMA1}, &s5pv210_pdma1_pdata); static int __init s5pv210_dma_init(void) { diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c index ff9152610439..2cf5ed75f390 100644 --- a/arch/arm/mach-s5pv210/mach-goni.c +++ b/arch/arm/mach-s5pv210/mach-goni.c @@ -844,7 +844,7 @@ static struct s5p_fimc_isp_info goni_camera_sensors[] = { }, }; -struct s5p_platform_fimc goni_fimc_md_platdata __initdata = { +static struct s5p_platform_fimc goni_fimc_md_platdata __initdata = { .isp_info = goni_camera_sensors, .num_clients = ARRAY_SIZE(goni_camera_sensors), }; diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c index dff9ea7b5bba..0933c8e1eb7b 100644 --- a/arch/arm/mach-s5pv210/mach-smdkv210.c +++ b/arch/arm/mach-s5pv210/mach-smdkv210.c @@ -140,7 +140,7 @@ static struct dm9000_plat_data smdkv210_dm9000_platdata = { .dev_addr = { 0x00, 0x09, 0xc0, 0xff, 0xec, 0x48 }, }; -struct platform_device smdkv210_dm9000 = { +static struct platform_device smdkv210_dm9000 = { .name = "dm9000", .id = -1, .num_resources = ARRAY_SIZE(smdkv210_dm9000_resources), diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c index 95e68190d593..037b448992af 100644 --- a/arch/arm/plat-s3c24xx/s3c2443-clock.c +++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c @@ -53,7 +53,7 @@ int s3c2443_clkcon_enable_s(struct clk *clk, int enable) * elided as the EPLL can be either sourced by the XTAL or EXTCLK and as * such directly equating the two source clocks is impossible. */ -struct clk clk_mpllref = { +static struct clk clk_mpllref = { .name = "mpllref", .parent = &clk_xtal, }; diff --git a/arch/arm/plat-s5p/irq-eint.c b/arch/arm/plat-s5p/irq-eint.c index c496b359c371..139c050918c5 100644 --- a/arch/arm/plat-s5p/irq-eint.c +++ b/arch/arm/plat-s5p/irq-eint.c @@ -200,7 +200,7 @@ static struct irq_chip s5p_irq_vic_eint = { #endif }; -int __init s5p_init_irq_eint(void) +static int __init s5p_init_irq_eint(void) { int irq; diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-s5p/irq-gpioint.c index 1fdfaa4599ce..82c7311017a2 100644 --- a/arch/arm/plat-s5p/irq-gpioint.c +++ b/arch/arm/plat-s5p/irq-gpioint.c @@ -41,7 +41,7 @@ struct s5p_gpioint_bank { void (*handler)(unsigned int, struct irq_desc *); }; -LIST_HEAD(banks); +static LIST_HEAD(banks); static int s5p_gpioint_set_type(struct irq_data *d, unsigned int type) { diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c index 45d8e5c53ea5..8b928f9bc1c3 100644 --- a/arch/arm/plat-samsung/devs.c +++ b/arch/arm/plat-samsung/devs.c @@ -791,17 +791,6 @@ struct platform_device s3c_device_iis = { }; #endif /* CONFIG_PLAT_S3C24XX */ -#ifdef CONFIG_CPU_S3C2440 -struct platform_device s3c2412_device_iis = { - .name = "s3c2412-iis", - .id = -1, - .dev = { - .dma_mask = &samsung_device_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - } -}; -#endif /* CONFIG_CPU_S3C2440 */ - /* IDE CFCON */ #ifdef CONFIG_SAMSUNG_DEV_IDE @@ -1125,7 +1114,7 @@ static struct resource s5p_pmu_resource[] = { DEFINE_RES_IRQ(IRQ_PMU) }; -struct platform_device s5p_device_pmu = { +static struct platform_device s5p_device_pmu = { .name = "arm-pmu", .id = ARM_PMU_DEVICE_CPU, .num_resources = ARRAY_SIZE(s5p_pmu_resource), diff --git a/arch/arm/plat-samsung/dma-ops.c b/arch/arm/plat-samsung/dma-ops.c index 0747c77a2fd5..301d9c319d0b 100644 --- a/arch/arm/plat-samsung/dma-ops.c +++ b/arch/arm/plat-samsung/dma-ops.c @@ -116,7 +116,7 @@ static inline int samsung_dmadev_flush(unsigned ch) return dmaengine_terminate_all((struct dma_chan *)ch); } -struct samsung_dma_ops dmadev_ops = { +static struct samsung_dma_ops dmadev_ops = { .request = samsung_dmadev_request, .release = samsung_dmadev_release, .prepare = samsung_dmadev_prepare, |
