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-rw-r--r--arch/sh/mm/tlb-pteaex.c66
1 files changed, 0 insertions, 66 deletions
diff --git a/arch/sh/mm/tlb-pteaex.c b/arch/sh/mm/tlb-pteaex.c
index 88c8bb05e16d..409b7c2b4b9d 100644
--- a/arch/sh/mm/tlb-pteaex.c
+++ b/arch/sh/mm/tlb-pteaex.c
@@ -76,69 +76,3 @@ void __uses_jump_to_uncached local_flush_tlb_one(unsigned long asid,
__raw_writel(asid, MMU_UTLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT);
back_to_cached();
}
-
-/*
- * Load the entry for 'addr' into the TLB and wire the entry.
- */
-void tlb_wire_entry(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
-{
- unsigned long status, flags;
- int urb;
-
- local_irq_save(flags);
-
- /* Load the entry into the TLB */
- __update_tlb(vma, addr, pte);
-
- /* ... and wire it up. */
- status = ctrl_inl(MMUCR);
- urb = (status & MMUCR_URB) >> MMUCR_URB_SHIFT;
- status &= ~MMUCR_URB;
-
- /*
- * Make sure we're not trying to wire the last TLB entry slot.
- */
- BUG_ON(!--urb);
-
- urb = urb % MMUCR_URB_NENTRIES;
-
- status |= (urb << MMUCR_URB_SHIFT);
- ctrl_outl(status, MMUCR);
- ctrl_barrier();
-
- local_irq_restore(flags);
-}
-
-/*
- * Unwire the last wired TLB entry.
- *
- * It should also be noted that it is not possible to wire and unwire
- * TLB entries in an arbitrary order. If you wire TLB entry N, followed
- * by entry N+1, you must unwire entry N+1 first, then entry N. In this
- * respect, it works like a stack or LIFO queue.
- */
-void tlb_unwire_entry(void)
-{
- unsigned long status, flags;
- int urb;
-
- local_irq_save(flags);
-
- status = ctrl_inl(MMUCR);
- urb = (status & MMUCR_URB) >> MMUCR_URB_SHIFT;
- status &= ~MMUCR_URB;
-
- /*
- * Make sure we're not trying to unwire a TLB entry when none
- * have been wired.
- */
- BUG_ON(urb++ == MMUCR_URB_NENTRIES);
-
- urb = urb % MMUCR_URB_NENTRIES;
-
- status |= (urb << MMUCR_URB_SHIFT);
- ctrl_outl(status, MMUCR);
- ctrl_barrier();
-
- local_irq_restore(flags);
-}
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