diff options
Diffstat (limited to 'arch/arm/mach-s5pv310/mach-smdkc210.c')
| -rw-r--r-- | arch/arm/mach-s5pv310/mach-smdkc210.c | 202 |
1 files changed, 202 insertions, 0 deletions
diff --git a/arch/arm/mach-s5pv310/mach-smdkc210.c b/arch/arm/mach-s5pv310/mach-smdkc210.c new file mode 100644 index 000000000000..2b8d4fc52d7c --- /dev/null +++ b/arch/arm/mach-s5pv310/mach-smdkc210.c @@ -0,0 +1,202 @@ +/* linux/arch/arm/mach-s5pv310/mach-smdkc210.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/serial_core.h> +#include <linux/gpio.h> +#include <linux/mmc/host.h> +#include <linux/platform_device.h> +#include <linux/smsc911x.h> +#include <linux/io.h> + +#include <asm/mach/arch.h> +#include <asm/mach-types.h> + +#include <plat/regs-serial.h> +#include <plat/s5pv310.h> +#include <plat/cpu.h> +#include <plat/devs.h> +#include <plat/sdhci.h> + +#include <mach/map.h> +#include <mach/regs-srom.h> + +/* Following are default values for UCON, ULCON and UFCON UART registers */ +#define SMDKC210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ + S3C2410_UCON_RXILEVEL | \ + S3C2410_UCON_TXIRQMODE | \ + S3C2410_UCON_RXIRQMODE | \ + S3C2410_UCON_RXFIFO_TOI | \ + S3C2443_UCON_RXERR_IRQEN) + +#define SMDKC210_ULCON_DEFAULT S3C2410_LCON_CS8 + +#define SMDKC210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ + S5PV210_UFCON_TXTRIG4 | \ + S5PV210_UFCON_RXTRIG4) + +static struct s3c2410_uartcfg smdkc210_uartcfgs[] __initdata = { + [0] = { + .hwport = 0, + .flags = 0, + .ucon = SMDKC210_UCON_DEFAULT, + .ulcon = SMDKC210_ULCON_DEFAULT, + .ufcon = SMDKC210_UFCON_DEFAULT, + }, + [1] = { + .hwport = 1, + .flags = 0, + .ucon = SMDKC210_UCON_DEFAULT, + .ulcon = SMDKC210_ULCON_DEFAULT, + .ufcon = SMDKC210_UFCON_DEFAULT, + }, + [2] = { + .hwport = 2, + .flags = 0, + .ucon = SMDKC210_UCON_DEFAULT, + .ulcon = SMDKC210_ULCON_DEFAULT, + .ufcon = SMDKC210_UFCON_DEFAULT, + }, + [3] = { + .hwport = 3, + .flags = 0, + .ucon = SMDKC210_UCON_DEFAULT, + .ulcon = SMDKC210_ULCON_DEFAULT, + .ufcon = SMDKC210_UFCON_DEFAULT, + }, +}; + +static struct s3c_sdhci_platdata smdkc210_hsmmc0_pdata __initdata = { + .cd_type = S3C_SDHCI_CD_GPIO, + .ext_cd_gpio = S5PV310_GPK0(2), + .ext_cd_gpio_invert = 1, + .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, +#ifdef CONFIG_S5PV310_SDHCI_CH0_8BIT + .max_width = 8, + .host_caps = MMC_CAP_8_BIT_DATA, +#endif +}; + +static struct s3c_sdhci_platdata smdkc210_hsmmc1_pdata __initdata = { + .cd_type = S3C_SDHCI_CD_GPIO, + .ext_cd_gpio = S5PV310_GPK0(2), + .ext_cd_gpio_invert = 1, + .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, +}; + +static struct s3c_sdhci_platdata smdkc210_hsmmc2_pdata __initdata = { + .cd_type = S3C_SDHCI_CD_GPIO, + .ext_cd_gpio = S5PV310_GPK2(2), + .ext_cd_gpio_invert = 1, + .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, +#ifdef CONFIG_S5PV310_SDHCI_CH2_8BIT + .max_width = 8, + .host_caps = MMC_CAP_8_BIT_DATA, +#endif +}; + +static struct s3c_sdhci_platdata smdkc210_hsmmc3_pdata __initdata = { + .cd_type = S3C_SDHCI_CD_GPIO, + .ext_cd_gpio = S5PV310_GPK2(2), + .ext_cd_gpio_invert = 1, + .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, +}; + +static struct resource smdkc210_smsc911x_resources[] = { + [0] = { + .start = S5PV310_PA_SROM_BANK(1), + .end = S5PV310_PA_SROM_BANK(1) + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_EINT(5), + .end = IRQ_EINT(5), + .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, + }, +}; + +static struct smsc911x_platform_config smsc9215_config = { + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH, + .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, + .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY, + .phy_interface = PHY_INTERFACE_MODE_MII, + .mac = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67}, +}; + +static struct platform_device smdkc210_smsc911x = { + .name = "smsc911x", + .id = -1, + .num_resources = ARRAY_SIZE(smdkc210_smsc911x_resources), + .resource = smdkc210_smsc911x_resources, + .dev = { + .platform_data = &smsc9215_config, + }, +}; + +static struct platform_device *smdkc210_devices[] __initdata = { + &s3c_device_hsmmc0, + &s3c_device_hsmmc1, + &s3c_device_hsmmc2, + &s3c_device_hsmmc3, + &s3c_device_rtc, + &s3c_device_wdt, + &smdkc210_smsc911x, +}; + +static void __init smdkc210_smsc911x_init(void) +{ + u32 cs1; + + /* configure nCS1 width to 16 bits */ + cs1 = __raw_readl(S5PV310_SROM_BW) & + ~(S5PV310_SROM_BW__CS_MASK << + S5PV310_SROM_BW__NCS1__SHIFT); + cs1 |= ((1 << S5PV310_SROM_BW__DATAWIDTH__SHIFT) | + (1 << S5PV310_SROM_BW__WAITENABLE__SHIFT) | + (1 << S5PV310_SROM_BW__BYTEENABLE__SHIFT)) << + S5PV310_SROM_BW__NCS1__SHIFT; + __raw_writel(cs1, S5PV310_SROM_BW); + + /* set timing for nCS1 suitable for ethernet chip */ + __raw_writel((0x1 << S5PV310_SROM_BCX__PMC__SHIFT) | + (0x9 << S5PV310_SROM_BCX__TACP__SHIFT) | + (0xc << S5PV310_SROM_BCX__TCAH__SHIFT) | + (0x1 << S5PV310_SROM_BCX__TCOH__SHIFT) | + (0x6 << S5PV310_SROM_BCX__TACC__SHIFT) | + (0x1 << S5PV310_SROM_BCX__TCOS__SHIFT) | + (0x1 << S5PV310_SROM_BCX__TACS__SHIFT), S5PV310_SROM_BC1); +} + +static void __init smdkc210_map_io(void) +{ + s5p_init_io(NULL, 0, S5P_VA_CHIPID); + s3c24xx_init_clocks(24000000); + s3c24xx_init_uarts(smdkc210_uartcfgs, ARRAY_SIZE(smdkc210_uartcfgs)); +} + +static void __init smdkc210_machine_init(void) +{ + smdkc210_smsc911x_init(); + + s3c_sdhci0_set_platdata(&smdkc210_hsmmc0_pdata); + s3c_sdhci1_set_platdata(&smdkc210_hsmmc1_pdata); + s3c_sdhci2_set_platdata(&smdkc210_hsmmc2_pdata); + s3c_sdhci3_set_platdata(&smdkc210_hsmmc3_pdata); + + platform_add_devices(smdkc210_devices, ARRAY_SIZE(smdkc210_devices)); +} + +MACHINE_START(SMDKC210, "SMDKC210") + /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ + .boot_params = S5P_PA_SDRAM + 0x100, + .init_irq = s5pv310_init_irq, + .map_io = smdkc210_map_io, + .init_machine = smdkc210_machine_init, + .timer = &s5pv310_timer, +MACHINE_END |
