diff options
| author | Peter Ujfalusi <peter.ujfalusi@ti.com> | 2014-10-29 13:55:44 +0200 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2014-10-29 12:31:38 +0000 |
| commit | 36bcecd0a73eb4a11c9748bc96c2d254d5364d12 (patch) | |
| tree | 8bd9be21f9c04249f53387928610230171cd754f /sound/soc/davinci/davinci-mcasp.c | |
| parent | f114040e3ea6e07372334ade75d1ee0775c355e1 (diff) | |
| download | blackbird-op-linux-36bcecd0a73eb4a11c9748bc96c2d254d5364d12.tar.gz blackbird-op-linux-36bcecd0a73eb4a11c9748bc96c2d254d5364d12.zip | |
ASoC: davinci-mcasp: Correct TX start sequence
Follow the sequence described in the TRMs when starting TX. This sequence
will make sure that we are not facing with initial channel swap caused by
no data available in McASP for transmit.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/davinci/davinci-mcasp.c')
| -rw-r--r-- | sound/soc/davinci/davinci-mcasp.c | 25 |
1 files changed, 9 insertions, 16 deletions
diff --git a/sound/soc/davinci/davinci-mcasp.c b/sound/soc/davinci/davinci-mcasp.c index 0eed9b1b24e1..e1c1f40dd77f 100644 --- a/sound/soc/davinci/davinci-mcasp.c +++ b/sound/soc/davinci/davinci-mcasp.c @@ -183,31 +183,24 @@ static void mcasp_start_rx(struct davinci_mcasp *mcasp) static void mcasp_start_tx(struct davinci_mcasp *mcasp) { - u8 offset = 0, i; u32 cnt; + /* Start clocks */ mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); + /* Activate serializer(s) */ mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR); - mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0); - mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST); - mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); - mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0); - for (i = 0; i < mcasp->num_serializer; i++) { - if (mcasp->serial_dir[i] == TX_MODE) { - offset = i; - break; - } - } - - /* wait for TX ready */ + /* wait for XDATA to be cleared */ cnt = 0; - while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(offset)) & - TXSTATE) && (cnt < 100000)) + while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & + ~XRDATA) && (cnt < 100000)) cnt++; - mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0); + /* Release TX state machine */ + mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST); + /* Release Frame Sync generator */ + mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); } static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream) |
