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authorXing Zheng <zhengxing@rock-chips.com>2016-05-25 16:51:56 +0800
committerHeiko Stuebner <heiko@sntech.de>2016-05-30 09:44:26 +0200
commit26e0ee1c62a08ee7dd39e9c38f53b5bcfe8b70b7 (patch)
treead65f1b369d44458f3e8900a6e8a3255dfd67d56 /scripts/Lindent
parent1a695a905c18548062509178b98bc91e67510864 (diff)
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clk: rockchip: add a dummy clock for the watchdog pclk on rk3399
Like rk3288, the pclk supplying the watchdog is controlled via the SGRF register area. Additionally the SGRF isn't even writable in every boot mode. But still the clock control is available and in the future someone might want to use it. Therefore define a simple clock for the time being so that the watchdog driver can read its rate. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Reviewed-by: Stephen Barber <smbarber@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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