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| author | Takashi Iwai <tiwai@suse.de> | 2017-03-29 08:39:19 +0200 |
|---|---|---|
| committer | Takashi Iwai <tiwai@suse.de> | 2017-04-03 08:43:07 +0200 |
| commit | 70eafad849f8af3a83e139eda36712d3c1da5b6a (patch) | |
| tree | bec5663408a923e12d0fa9562127e12e14ab17c5 /include/sound/hda_register.h | |
| parent | 2c1f81381eadc6dd3c288ec4477b2fe572cf86dc (diff) | |
| download | blackbird-op-linux-70eafad849f8af3a83e139eda36712d3c1da5b6a.tar.gz blackbird-op-linux-70eafad849f8af3a83e139eda36712d3c1da5b6a.zip | |
ALSA: hda - Move SKL+ vendor specific register definitions to hda_register.h
They may be used by both legacy and ASoC drivers.
Acked-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
Diffstat (limited to 'include/sound/hda_register.h')
| -rw-r--r-- | include/sound/hda_register.h | 22 |
1 files changed, 20 insertions, 2 deletions
diff --git a/include/sound/hda_register.h b/include/sound/hda_register.h index 0013063db7f2..1251ff41c9d3 100644 --- a/include/sound/hda_register.h +++ b/include/sound/hda_register.h @@ -106,8 +106,26 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; #define AZX_REG_HSW_EM4 0x100c #define AZX_REG_HSW_EM5 0x1010 -/* Skylake/Broxton display HD-A controller Extended Mode registers */ -#define AZX_REG_SKL_EM4L 0x1040 +/* Skylake/Broxton vendor-specific registers */ +#define AZX_REG_VS_EM1 0x1000 +#define AZX_REG_VS_INRC 0x1004 +#define AZX_REG_VS_OUTRC 0x1008 +#define AZX_REG_VS_FIFOTRK 0x100C +#define AZX_REG_VS_FIFOTRK2 0x1010 +#define AZX_REG_VS_EM2 0x1030 +#define AZX_REG_VS_EM3L 0x1038 +#define AZX_REG_VS_EM3U 0x103C +#define AZX_REG_VS_EM4L 0x1040 +#define AZX_REG_VS_EM4U 0x1044 +#define AZX_REG_VS_LTRC 0x1048 +#define AZX_REG_VS_D0I3C 0x104A +#define AZX_REG_VS_PCE 0x104B +#define AZX_REG_VS_L2MAGC 0x1050 +#define AZX_REG_VS_L2LAHPT 0x1054 +#define AZX_REG_VS_SDXDPIB_XBASE 0x1084 +#define AZX_REG_VS_SDXDPIB_XINTERVAL 0x20 +#define AZX_REG_VS_SDXEFIFOS_XBASE 0x1094 +#define AZX_REG_VS_SDXEFIFOS_XINTERVAL 0x20 /* PCI space */ #define AZX_PCIREG_TCSEL 0x44 |
