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authorShannon Zhao <shannon.zhao@linaro.org>2015-09-08 15:15:56 +0800
committerMarc Zyngier <marc.zyngier@arm.com>2016-02-29 18:34:21 +0000
commitd692b8ad6ec4814ddd9a37ce5c9c9d971e741088 (patch)
tree1162196e1dde3244581e90b669681b062731921b /include/kvm
parent76993739cd6f5b42e881fe3332b9f8eb98cd6907 (diff)
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arm64: KVM: Add access handler for PMUSERENR register
This register resets as unknown in 64bit mode while it resets as zero in 32bit mode. Here we choose to reset it as zero for consistency. PMUSERENR_EL0 holds some bits which decide whether PMU registers can be accessed from EL0. Add some check helpers to handle the access from EL0. When these bits are zero, only reading PMUSERENR will trap to EL2 and writing PMUSERENR or reading/writing other PMU registers will trap to EL1 other than EL2 when HCR.TGE==0. To current KVM configuration (HCR.TGE==0) there is no way to get these traps. Here we write 0xf to physical PMUSERENR register on VM entry, so that it will trap PMU access from EL0 to EL2. Within the register access handler we check the real value of guest PMUSERENR register to decide whether this access is allowed. If not allowed, return false to inject UND to guest. Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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