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authorHiroshi DOYU <Hiroshi.DOYU@nokia.com>2009-09-24 16:23:10 -0700
committerTony Lindgren <tony@atomide.com>2009-09-24 16:23:10 -0700
commit8828880d09e4466ad6b357a31fdd242594c7b111 (patch)
tree6ed4e5babf1b5501cd2a3fe51dd119a878d06b44 /fs/dlm
parent1ffe627dcfce820b316ee520c58fca54550a18ee (diff)
downloadblackbird-op-linux-8828880d09e4466ad6b357a31fdd242594c7b111.tar.gz
blackbird-op-linux-8828880d09e4466ad6b357a31fdd242594c7b111.zip
omap: mailbox: Flush posted write when acking mailbox irq
The only way to flush posted write to L4 bus is to do a read back of the same register right after the write. This seems to be mostly needed in interrupt handlers to avoid causing spurious interrupts. The earlier fix has been to mark the L4 bus as strongly ordered memory, which solves the problem, but causes performance penalties. Similar to the fix, 03803a71041e3bc3c077f4e7b92f6ceaa9426df3 Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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