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authorLaurent Pinchart <laurent.pinchart@ideasonboard.com>2014-02-09 17:31:47 -0300
committerMauro Carvalho Chehab <m.chehab@samsung.com>2014-02-24 13:12:36 -0300
commita970449e40789a0056424668da5b56f57569ea73 (patch)
treeea77264963dd3c5c9ce814d215f9fbefe944c9e8 /drivers/uwb/est.c
parente8e45593c920a05b1f4b9d94738a84039b9b4f22 (diff)
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[media] mt9p031: Add support for PLL bypass
When the input clock frequency is out of bounds for the PLL, bypass the PLL and just divide the input clock to achieve the requested output frequency. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
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