diff options
| author | Andrew Miller <amiller@amilx.com> | 2012-03-09 22:51:01 -0300 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab@redhat.com> | 2012-03-19 15:44:00 -0300 |
| commit | 23bfb5be9f4c14937d70ed09f24a19d86df1951b (patch) | |
| tree | 58409d80c281366b1a450994932d1522c24f9ee0 /drivers/staging | |
| parent | 68a6bb546575a2ba62baddbde710fac42ff04f19 (diff) | |
| download | blackbird-op-linux-23bfb5be9f4c14937d70ed09f24a19d86df1951b.tar.gz blackbird-op-linux-23bfb5be9f4c14937d70ed09f24a19d86df1951b.zip | |
[media] Staging: media: solo6x10: core.c Fix some coding style issue
Replaced spaces with tabs
Signed-off-by: Andrew Miller <amiller@amilx.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/staging')
| -rw-r--r-- | drivers/staging/media/solo6x10/core.c | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/drivers/staging/media/solo6x10/core.c b/drivers/staging/media/solo6x10/core.c index f974f6412ad7..d2fd842e37cf 100644 --- a/drivers/staging/media/solo6x10/core.c +++ b/drivers/staging/media/solo6x10/core.c @@ -195,28 +195,28 @@ static int __devinit solo_pci_probe(struct pci_dev *pdev, SOLO6010_SYS_CFG_OUTDIV(3); solo_reg_write(solo_dev, SOLO_SYS_CFG, reg); - if (solo_dev->flags & FLAGS_6110) { - u32 sys_clock_MHz = SOLO_CLOCK_MHZ; - u32 pll_DIVQ; - u32 pll_DIVF; - - if (sys_clock_MHz < 125) { - pll_DIVQ = 3; - pll_DIVF = (sys_clock_MHz * 4) / 3; - } else { - pll_DIVQ = 2; - pll_DIVF = (sys_clock_MHz * 2) / 3; - } - - solo_reg_write(solo_dev, SOLO6110_PLL_CONFIG, + if (solo_dev->flags & FLAGS_6110) { + u32 sys_clock_MHz = SOLO_CLOCK_MHZ; + u32 pll_DIVQ; + u32 pll_DIVF; + + if (sys_clock_MHz < 125) { + pll_DIVQ = 3; + pll_DIVF = (sys_clock_MHz * 4) / 3; + } else { + pll_DIVQ = 2; + pll_DIVF = (sys_clock_MHz * 2) / 3; + } + + solo_reg_write(solo_dev, SOLO6110_PLL_CONFIG, SOLO6110_PLL_RANGE_5_10MHZ | SOLO6110_PLL_DIVR(9) | SOLO6110_PLL_DIVQ_EXP(pll_DIVQ) | SOLO6110_PLL_DIVF(pll_DIVF) | SOLO6110_PLL_FSEN); - mdelay(1); // PLL Locking time (1ms) + mdelay(1); /* PLL Locking time (1ms) */ solo_reg_write(solo_dev, SOLO_DMA_CTRL1, 3 << 8); /* ? */ - } else + } else solo_reg_write(solo_dev, SOLO_DMA_CTRL1, 1 << 8); /* ? */ solo_reg_write(solo_dev, SOLO_TIMER_CLOCK_NUM, SOLO_CLOCK_MHZ - 1); |
