diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2016-05-20 22:20:48 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2016-05-20 22:20:48 -0700 |
| commit | 2f37dd131c5d3a2eac21cd5baf80658b1b02a8ac (patch) | |
| tree | e0f191b15865268e694c02f1f02cbc26a168ddf9 /drivers/staging/comedi | |
| parent | 3aa2fc1667acdd9cca816a2bc9529f494bd61b05 (diff) | |
| parent | ffc83a79b44e02995ab5e93af07e26f6c7243c53 (diff) | |
| download | blackbird-op-linux-2f37dd131c5d3a2eac21cd5baf80658b1b02a8ac.tar.gz blackbird-op-linux-2f37dd131c5d3a2eac21cd5baf80658b1b02a8ac.zip | |
Merge tag 'staging-4.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging
Pull staging and IIO driver updates from Greg KH:
"Here's the big staging and iio driver update for 4.7-rc1.
I think we almost broke even with this release, only adding a few more
lines than we removed, which isn't bad overall given that there's a
bunch of new iio drivers added.
The Lustre developers seem to have woken up from their sleep and have
been doing a great job in cleaning up the code and pruning unused or
old cruft, the filesystem is almost readable :)
Other than that, just a lot of basic coding style cleanups in the
churn. All have been in linux-next for a while with no reported
issues"
* tag 'staging-4.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging: (938 commits)
Staging: emxx_udc: emxx_udc: fixed coding style issue
staging/gdm724x: fix "alignment should match open parenthesis" issues
staging/gdm724x: Fix avoid CamelCase
staging: unisys: rename misleading var ii with frag
staging: unisys: visorhba: switch success handling to error handling
staging: unisys: visorhba: main path needs to flow down the left margin
staging: unisys: visorinput: handle_locking_key() simplifications
staging: unisys: visorhba: fail gracefully for thread creation failures
staging: unisys: visornic: comment restructuring and removing bad diction
staging: unisys: fix format string %Lx to %llx for u64
staging: unisys: remove unused struct members
staging: unisys: visorchannel: correct variable misspelling
staging: unisys: visorhba: replace functionlike macro with function
staging: dgnc: Need to check for NULL of ch
staging: dgnc: remove redundant condition check
staging: dgnc: fix 'line over 80 characters'
staging: dgnc: clean up the dgnc_get_modem_info()
staging: lustre: lnet: enable configuration per NI interface
staging: lustre: o2iblnd: properly set ibr_why
staging: lustre: o2iblnd: remove last of kiblnd_tunables_fini
...
Diffstat (limited to 'drivers/staging/comedi')
34 files changed, 3616 insertions, 4040 deletions
diff --git a/drivers/staging/comedi/comedi_buf.c b/drivers/staging/comedi/comedi_buf.c index 90c28016c6c1..c7d7682b1412 100644 --- a/drivers/staging/comedi/comedi_buf.c +++ b/drivers/staging/comedi/comedi_buf.c @@ -80,14 +80,14 @@ static void __comedi_buf_free(struct comedi_device *dev, static void __comedi_buf_alloc(struct comedi_device *dev, struct comedi_subdevice *s, - unsigned n_pages) + unsigned int n_pages) { struct comedi_async *async = s->async; struct page **pages = NULL; struct comedi_buf_map *bm; struct comedi_buf_page *buf; unsigned long flags; - unsigned i; + unsigned int i; if (!IS_ENABLED(CONFIG_HAS_DMA) && s->async_dma_dir != DMA_NONE) { dev_err(dev->class_dev, @@ -208,7 +208,7 @@ int comedi_buf_alloc(struct comedi_device *dev, struct comedi_subdevice *s, /* allocate new buffer */ if (new_size) { - unsigned n_pages = new_size >> PAGE_SHIFT; + unsigned int n_pages = new_size >> PAGE_SHIFT; __comedi_buf_alloc(dev, s, n_pages); @@ -302,7 +302,7 @@ static unsigned int comedi_buf_munge(struct comedi_subdevice *s, { struct comedi_async *async = s->async; unsigned int count = 0; - const unsigned num_sample_bytes = comedi_bytes_per_sample(s); + const unsigned int num_sample_bytes = comedi_bytes_per_sample(s); if (!s->munge || (async->cmd.flags & CMDF_RAWDATA)) { async->munge_count += num_bytes; @@ -395,7 +395,7 @@ EXPORT_SYMBOL_GPL(comedi_buf_write_free); unsigned int comedi_buf_read_n_available(struct comedi_subdevice *s) { struct comedi_async *async = s->async; - unsigned num_bytes; + unsigned int num_bytes; if (!async) return 0; diff --git a/drivers/staging/comedi/comedi_fops.c b/drivers/staging/comedi/comedi_fops.c index 7c7b477b0f28..629080f39db0 100644 --- a/drivers/staging/comedi/comedi_fops.c +++ b/drivers/staging/comedi/comedi_fops.c @@ -186,7 +186,7 @@ static bool comedi_clear_board_dev(struct comedi_device *dev) return cleared; } -static struct comedi_device *comedi_clear_board_minor(unsigned minor) +static struct comedi_device *comedi_clear_board_minor(unsigned int minor) { struct comedi_device *dev; @@ -209,8 +209,8 @@ static void comedi_free_board_dev(struct comedi_device *dev) } } -static struct comedi_subdevice -*comedi_subdevice_from_minor(const struct comedi_device *dev, unsigned minor) +static struct comedi_subdevice * +comedi_subdevice_from_minor(const struct comedi_device *dev, unsigned int minor) { struct comedi_subdevice *s; unsigned int i = minor - COMEDI_NUM_BOARD_MINORS; @@ -223,7 +223,7 @@ static struct comedi_subdevice return s; } -static struct comedi_device *comedi_dev_get_from_board_minor(unsigned minor) +static struct comedi_device *comedi_dev_get_from_board_minor(unsigned int minor) { struct comedi_device *dev; @@ -233,7 +233,8 @@ static struct comedi_device *comedi_dev_get_from_board_minor(unsigned minor) return dev; } -static struct comedi_device *comedi_dev_get_from_subdevice_minor(unsigned minor) +static struct comedi_device * +comedi_dev_get_from_subdevice_minor(unsigned int minor) { struct comedi_device *dev; struct comedi_subdevice *s; @@ -258,7 +259,7 @@ static struct comedi_device *comedi_dev_get_from_subdevice_minor(unsigned minor) * reference incremented. Return NULL if no COMEDI device exists with the * specified minor device number. */ -struct comedi_device *comedi_dev_get_from_minor(unsigned minor) +struct comedi_device *comedi_dev_get_from_minor(unsigned int minor) { if (minor < COMEDI_NUM_BOARD_MINORS) return comedi_dev_get_from_board_minor(minor); @@ -342,7 +343,8 @@ static struct comedi_subdevice *comedi_file_write_subdevice(struct file *file) } static int resize_async_buffer(struct comedi_device *dev, - struct comedi_subdevice *s, unsigned new_size) + struct comedi_subdevice *s, + unsigned int new_size) { struct comedi_async *async = s->async; int retval; @@ -616,19 +618,20 @@ static struct attribute *comedi_dev_attrs[] = { ATTRIBUTE_GROUPS(comedi_dev); static void __comedi_clear_subdevice_runflags(struct comedi_subdevice *s, - unsigned bits) + unsigned int bits) { s->runflags &= ~bits; } static void __comedi_set_subdevice_runflags(struct comedi_subdevice *s, - unsigned bits) + unsigned int bits) { s->runflags |= bits; } static void comedi_update_subdevice_runflags(struct comedi_subdevice *s, - unsigned mask, unsigned bits) + unsigned int mask, + unsigned int bits) { unsigned long flags; @@ -638,15 +641,15 @@ static void comedi_update_subdevice_runflags(struct comedi_subdevice *s, spin_unlock_irqrestore(&s->spin_lock, flags); } -static unsigned __comedi_get_subdevice_runflags(struct comedi_subdevice *s) +static unsigned int __comedi_get_subdevice_runflags(struct comedi_subdevice *s) { return s->runflags; } -static unsigned comedi_get_subdevice_runflags(struct comedi_subdevice *s) +static unsigned int comedi_get_subdevice_runflags(struct comedi_subdevice *s) { unsigned long flags; - unsigned runflags; + unsigned int runflags; spin_lock_irqsave(&s->spin_lock, flags); runflags = __comedi_get_subdevice_runflags(s); @@ -654,12 +657,12 @@ static unsigned comedi_get_subdevice_runflags(struct comedi_subdevice *s) return runflags; } -static bool comedi_is_runflags_running(unsigned runflags) +static bool comedi_is_runflags_running(unsigned int runflags) { return runflags & COMEDI_SRF_RUNNING; } -static bool comedi_is_runflags_in_error(unsigned runflags) +static bool comedi_is_runflags_in_error(unsigned int runflags) { return runflags & COMEDI_SRF_ERROR; } @@ -673,7 +676,7 @@ static bool comedi_is_runflags_in_error(unsigned runflags) */ bool comedi_is_subdevice_running(struct comedi_subdevice *s) { - unsigned runflags = comedi_get_subdevice_runflags(s); + unsigned int runflags = comedi_get_subdevice_runflags(s); return comedi_is_runflags_running(runflags); } @@ -681,14 +684,14 @@ EXPORT_SYMBOL_GPL(comedi_is_subdevice_running); static bool __comedi_is_subdevice_running(struct comedi_subdevice *s) { - unsigned runflags = __comedi_get_subdevice_runflags(s); + unsigned int runflags = __comedi_get_subdevice_runflags(s); return comedi_is_runflags_running(runflags); } bool comedi_can_auto_free_spriv(struct comedi_subdevice *s) { - unsigned runflags = __comedi_get_subdevice_runflags(s); + unsigned int runflags = __comedi_get_subdevice_runflags(s); return runflags & COMEDI_SRF_FREE_SPRIV; } @@ -2038,7 +2041,7 @@ static int do_setwsubd_ioctl(struct comedi_device *dev, unsigned long arg, static long comedi_unlocked_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { - unsigned minor = iminor(file_inode(file)); + unsigned int minor = iminor(file_inode(file)); struct comedi_file *cfp = file->private_data; struct comedi_device *dev = cfp->dev; int rc; @@ -2342,7 +2345,7 @@ static ssize_t comedi_write(struct file *file, const char __user *buf, add_wait_queue(&async->wait_head, &wait); while (count == 0 && !retval) { - unsigned runflags; + unsigned int runflags; unsigned int wp, n1, n2; set_current_state(TASK_INTERRUPTIBLE); @@ -2485,7 +2488,8 @@ static ssize_t comedi_read(struct file *file, char __user *buf, size_t nbytes, n = min_t(size_t, m, nbytes); if (n == 0) { - unsigned runflags = comedi_get_subdevice_runflags(s); + unsigned int runflags = + comedi_get_subdevice_runflags(s); if (!comedi_is_runflags_running(runflags)) { if (comedi_is_runflags_in_error(runflags)) @@ -2573,7 +2577,7 @@ out: static int comedi_open(struct inode *inode, struct file *file) { - const unsigned minor = iminor(inode); + const unsigned int minor = iminor(inode); struct comedi_file *cfp; struct comedi_device *dev = comedi_dev_get_from_minor(minor); int rc; @@ -2733,7 +2737,7 @@ struct comedi_device *comedi_alloc_board_minor(struct device *hardware_device) { struct comedi_device *dev; struct device *csdev; - unsigned i; + unsigned int i; dev = kzalloc(sizeof(*dev), GFP_KERNEL); if (!dev) @@ -2791,7 +2795,7 @@ int comedi_alloc_subdevice_minor(struct comedi_subdevice *s) { struct comedi_device *dev = s->device; struct device *csdev; - unsigned i; + unsigned int i; mutex_lock(&comedi_subdevice_minor_table_lock); for (i = 0; i < COMEDI_NUM_SUBDEVICE_MINORS; ++i) { @@ -2841,7 +2845,7 @@ void comedi_free_subdevice_minor(struct comedi_subdevice *s) static void comedi_cleanup_board_minors(void) { struct comedi_device *dev; - unsigned i; + unsigned int i; for (i = 0; i < COMEDI_NUM_BOARD_MINORS; i++) { dev = comedi_clear_board_minor(i); diff --git a/drivers/staging/comedi/comedidev.h b/drivers/staging/comedi/comedidev.h index 115807215484..dcb637665eb7 100644 --- a/drivers/staging/comedi/comedidev.h +++ b/drivers/staging/comedi/comedidev.h @@ -173,7 +173,7 @@ struct comedi_subdevice { void *lock; void *busy; - unsigned runflags; + unsigned int runflags; spinlock_t spin_lock; /* generic spin-lock for COMEDI and drivers */ unsigned int io_bits; @@ -566,7 +566,7 @@ struct comedi_device { void comedi_event(struct comedi_device *dev, struct comedi_subdevice *s); -struct comedi_device *comedi_dev_get_from_minor(unsigned minor); +struct comedi_device *comedi_dev_get_from_minor(unsigned int minor); int comedi_dev_put(struct comedi_device *dev); bool comedi_is_subdevice_running(struct comedi_subdevice *s); diff --git a/drivers/staging/comedi/drivers.c b/drivers/staging/comedi/drivers.c index b63dd2ef78b5..44511d729450 100644 --- a/drivers/staging/comedi/drivers.c +++ b/drivers/staging/comedi/drivers.c @@ -564,7 +564,7 @@ unsigned int comedi_handle_events(struct comedi_device *dev, if (events == 0) return events; - if (events & COMEDI_CB_CANCEL_MASK) + if ((events & COMEDI_CB_CANCEL_MASK) && s->cancel) s->cancel(dev, s); comedi_event(dev, s); @@ -575,38 +575,35 @@ EXPORT_SYMBOL_GPL(comedi_handle_events); static int insn_rw_emulate_bits(struct comedi_device *dev, struct comedi_subdevice *s, - struct comedi_insn *insn, unsigned int *data) + struct comedi_insn *insn, + unsigned int *data) { - struct comedi_insn new_insn; + struct comedi_insn _insn; + unsigned int chan = CR_CHAN(insn->chanspec); + unsigned int base_chan = (chan < 32) ? 0 : chan; + unsigned int _data[2]; int ret; - static const unsigned channels_per_bitfield = 32; - - unsigned chan = CR_CHAN(insn->chanspec); - const unsigned base_bitfield_channel = - (chan < channels_per_bitfield) ? 0 : chan; - unsigned int new_data[2]; - memset(new_data, 0, sizeof(new_data)); - memset(&new_insn, 0, sizeof(new_insn)); - new_insn.insn = INSN_BITS; - new_insn.chanspec = base_bitfield_channel; - new_insn.n = 2; - new_insn.subdev = insn->subdev; + memset(_data, 0, sizeof(_data)); + memset(&_insn, 0, sizeof(_insn)); + _insn.insn = INSN_BITS; + _insn.chanspec = base_chan; + _insn.n = 2; + _insn.subdev = insn->subdev; if (insn->insn == INSN_WRITE) { if (!(s->subdev_flags & SDF_WRITABLE)) return -EINVAL; - new_data[0] = 1 << (chan - base_bitfield_channel); /* mask */ - new_data[1] = data[0] ? (1 << (chan - base_bitfield_channel)) - : 0; /* bits */ + _data[0] = 1 << (chan - base_chan); /* mask */ + _data[1] = data[0] ? (1 << (chan - base_chan)) : 0; /* bits */ } - ret = s->insn_bits(dev, s, &new_insn, new_data); + ret = s->insn_bits(dev, s, &_insn, _data); if (ret < 0) return ret; if (insn->insn == INSN_READ) - data[0] = (new_data[1] >> (chan - base_bitfield_channel)) & 1; + data[0] = (_data[1] >> (chan - base_chan)) & 1; return 1; } @@ -628,6 +625,9 @@ static int __comedi_device_postconfig_async(struct comedi_device *dev, "async subdevices must have a do_cmdtest() function\n"); return -EINVAL; } + if (!s->cancel) + dev_warn(dev->class_dev, + "async subdevices should have a cancel() function\n"); async = kzalloc(sizeof(*async), GFP_KERNEL); if (!async) diff --git a/drivers/staging/comedi/drivers/amcc_s5933.h b/drivers/staging/comedi/drivers/amcc_s5933.h index d4b8c0195bd3..f03e4c8c2021 100644 --- a/drivers/staging/comedi/drivers/amcc_s5933.h +++ b/drivers/staging/comedi/drivers/amcc_s5933.h @@ -1,16 +1,14 @@ /* - comedi/drivers/amcc_s5933.h - - Stuff for AMCC S5933 PCI Controller - - Author: Michal Dobes <dobes@tesnet.cz> - - Inspirated from general-purpose AMCC S5933 PCI Matchmaker driver - made by Andrea Cisternino <acister@pcape1.pi.infn.it> - and as result of espionage from MITE code made by David A. Schleef. - Thanks to AMCC for their on-line documentation and bus master DMA - example. -*/ + * Stuff for AMCC S5933 PCI Controller + * + * Author: Michal Dobes <dobes@tesnet.cz> + * + * Inspirated from general-purpose AMCC S5933 PCI Matchmaker driver + * made by Andrea Cisternino <acister@pcape1.pi.infn.it> + * and as result of espionage from MITE code made by David A. Schleef. + * Thanks to AMCC for their on-line documentation and bus master DMA + * example. + */ #ifndef _AMCC_S5933_H_ #define _AMCC_S5933_H_ @@ -58,7 +56,7 @@ #define INTCSR_INTR_ASSERTED 0x800000 /****************************************************************************/ -/* AMCC - PCI non-volatile ram command register (byte 3 of master control/status register) */ +/* AMCC - PCI non-volatile ram command register (byte 3 of AMCC_OP_REG_MCSR) */ /****************************************************************************/ #define MCSR_NV_LOAD_LOW_ADDR 0x0 #define MCSR_NV_LOAD_HIGH_ADDR 0x20 diff --git a/drivers/staging/comedi/drivers/amplc_dio200_common.c b/drivers/staging/comedi/drivers/amplc_dio200_common.c index d1539e798ffd..f6e4e984235d 100644 --- a/drivers/staging/comedi/drivers/amplc_dio200_common.c +++ b/drivers/staging/comedi/drivers/amplc_dio200_common.c @@ -101,7 +101,7 @@ struct dio200_subdev_8255 { }; struct dio200_subdev_intr { - spinlock_t spinlock; + spinlock_t spinlock; /* protects the 'active' flag */ unsigned int ofs; unsigned int valid_isns; unsigned int enabled_isns; @@ -221,7 +221,7 @@ static void dio200_start_intr(struct comedi_device *dev, struct dio200_subdev_intr *subpriv = s->private; struct comedi_cmd *cmd = &s->async->cmd; unsigned int n; - unsigned isn_bits; + unsigned int isn_bits; /* Determine interrupt sources to enable. */ isn_bits = 0; @@ -284,9 +284,9 @@ static int dio200_handle_read_intr(struct comedi_device *dev, { const struct dio200_board *board = dev->board_ptr; struct dio200_subdev_intr *subpriv = s->private; - unsigned triggered; - unsigned intstat; - unsigned cur_enabled; + unsigned int triggered; + unsigned int intstat; + unsigned int cur_enabled; unsigned long flags; triggered = 0; @@ -439,7 +439,7 @@ static int dio200_subdev_intr_cmd(struct comedi_device *dev, static int dio200_subdev_intr_init(struct comedi_device *dev, struct comedi_subdevice *s, unsigned int offset, - unsigned valid_isns) + unsigned int valid_isns) { const struct dio200_board *board = dev->board_ptr; struct dio200_subdev_intr *subpriv; diff --git a/drivers/staging/comedi/drivers/amplc_pc263.c b/drivers/staging/comedi/drivers/amplc_pc263.c index b1946ce6ecc1..58b0b6b1a693 100644 --- a/drivers/staging/comedi/drivers/amplc_pc263.c +++ b/drivers/staging/comedi/drivers/amplc_pc263.c @@ -1,46 +1,44 @@ /* - comedi/drivers/amplc_pc263.c - Driver for Amplicon PC263 and PCI263 relay boards. - - Copyright (C) 2002 MEV Ltd. <http://www.mev.co.uk/> - - COMEDI - Linux Control and Measurement Device Interface - Copyright (C) 2000 David A. Schleef <ds@schleef.org> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. + * Driver for Amplicon PC263 relay board. + * + * Copyright (C) 2002 MEV Ltd. <http://www.mev.co.uk/> + * + * COMEDI - Linux Control and Measurement Device Interface + * Copyright (C) 2000 David A. Schleef <ds@schleef.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*/ /* -Driver: amplc_pc263 -Description: Amplicon PC263 -Author: Ian Abbott <abbotti@mev.co.uk> -Devices: [Amplicon] PC263 (pc263) -Updated: Fri, 12 Apr 2013 15:19:36 +0100 -Status: works - -Configuration options: - [0] - I/O port base address - -The board appears as one subdevice, with 16 digital outputs, each -connected to a reed-relay. Relay contacts are closed when output is 1. -The state of the outputs can be read. -*/ + * Driver: amplc_pc263 + * Description: Amplicon PC263 + * Author: Ian Abbott <abbotti@mev.co.uk> + * Devices: [Amplicon] PC263 (pc263) + * Updated: Fri, 12 Apr 2013 15:19:36 +0100 + * Status: works + * + * Configuration options: + * [0] - I/O port base address + * + * The board appears as one subdevice, with 16 digital outputs, each + * connected to a reed-relay. Relay contacts are closed when output is 1. + * The state of the outputs can be read. + */ #include <linux/module.h> #include "../comedidev.h" /* PC263 registers */ - -/* - * Board descriptions for Amplicon PC263. - */ +#define PC263_DO_0_7_REG 0x00 +#define PC263_DO_8_15_REG 0x01 struct pc263_board { const char *name; @@ -58,8 +56,8 @@ static int pc263_do_insn_bits(struct comedi_device *dev, unsigned int *data) { if (comedi_dio_update_state(s, data)) { - outb(s->state & 0xff, dev->iobase); - outb((s->state >> 8) & 0xff, dev->iobase + 1); + outb(s->state & 0xff, dev->iobase + PC263_DO_0_7_REG); + outb((s->state >> 8) & 0xff, dev->iobase + PC263_DO_8_15_REG); } data[1] = s->state; @@ -80,28 +78,30 @@ static int pc263_attach(struct comedi_device *dev, struct comedi_devconfig *it) if (ret) return ret; + /* Digital Output subdevice */ s = &dev->subdevices[0]; - /* digital output subdevice */ - s->type = COMEDI_SUBD_DO; - s->subdev_flags = SDF_WRITABLE; - s->n_chan = 16; - s->maxdata = 1; - s->range_table = &range_digital; - s->insn_bits = pc263_do_insn_bits; + s->type = COMEDI_SUBD_DO; + s->subdev_flags = SDF_WRITABLE; + s->n_chan = 16; + s->maxdata = 1; + s->range_table = &range_digital; + s->insn_bits = pc263_do_insn_bits; + /* read initial relay state */ - s->state = inb(dev->iobase) | (inb(dev->iobase + 1) << 8); + s->state = inb(dev->iobase + PC263_DO_0_7_REG) | + (inb(dev->iobase + PC263_DO_8_15_REG) << 8); return 0; } static struct comedi_driver amplc_pc263_driver = { - .driver_name = "amplc_pc263", - .module = THIS_MODULE, - .attach = pc263_attach, - .detach = comedi_legacy_detach, - .board_name = &pc263_boards[0].name, - .offset = sizeof(struct pc263_board), - .num_names = ARRAY_SIZE(pc263_boards), + .driver_name = "amplc_pc263", + .module = THIS_MODULE, + .attach = pc263_attach, + .detach = comedi_legacy_detach, + .board_name = &pc263_boards[0].name, + .offset = sizeof(struct pc263_board), + .num_names = ARRAY_SIZE(pc263_boards), }; module_comedi_driver(amplc_pc263_driver); diff --git a/drivers/staging/comedi/drivers/amplc_pci224.c b/drivers/staging/comedi/drivers/amplc_pci224.c index cac011fdd375..2e6decf1b69d 100644 --- a/drivers/staging/comedi/drivers/amplc_pci224.c +++ b/drivers/staging/comedi/drivers/amplc_pci224.c @@ -132,48 +132,53 @@ * DACCON values. */ /* (r/w) Scan trigger. */ -#define PCI224_DACCON_TRIG_MASK (7 << 0) -#define PCI224_DACCON_TRIG_NONE (0 << 0) /* none */ -#define PCI224_DACCON_TRIG_SW (1 << 0) /* software trig */ -#define PCI224_DACCON_TRIG_EXTP (2 << 0) /* ext +ve edge */ -#define PCI224_DACCON_TRIG_EXTN (3 << 0) /* ext -ve edge */ -#define PCI224_DACCON_TRIG_Z2CT0 (4 << 0) /* Z2 CT0 out */ -#define PCI224_DACCON_TRIG_Z2CT1 (5 << 0) /* Z2 CT1 out */ -#define PCI224_DACCON_TRIG_Z2CT2 (6 << 0) /* Z2 CT2 out */ +#define PCI224_DACCON_TRIG(x) (((x) & 0x7) << 0) +#define PCI224_DACCON_TRIG_MASK PCI224_DACCON_TRIG(7) +#define PCI224_DACCON_TRIG_NONE PCI224_DACCON_TRIG(0) /* none */ +#define PCI224_DACCON_TRIG_SW PCI224_DACCON_TRIG(1) /* soft trig */ +#define PCI224_DACCON_TRIG_EXTP PCI224_DACCON_TRIG(2) /* ext + edge */ +#define PCI224_DACCON_TRIG_EXTN PCI224_DACCON_TRIG(3) /* ext - edge */ +#define PCI224_DACCON_TRIG_Z2CT0 PCI224_DACCON_TRIG(4) /* Z2 CT0 out */ +#define PCI224_DACCON_TRIG_Z2CT1 PCI224_DACCON_TRIG(5) /* Z2 CT1 out */ +#define PCI224_DACCON_TRIG_Z2CT2 PCI224_DACCON_TRIG(6) /* Z2 CT2 out */ /* (r/w) Polarity (PCI224 only, PCI234 always bipolar!). */ -#define PCI224_DACCON_POLAR_MASK (1 << 3) -#define PCI224_DACCON_POLAR_UNI (0 << 3) /* range [0,Vref] */ -#define PCI224_DACCON_POLAR_BI (1 << 3) /* range [-Vref,Vref] */ +#define PCI224_DACCON_POLAR(x) (((x) & 0x1) << 3) +#define PCI224_DACCON_POLAR_MASK PCI224_DACCON_POLAR(1) +#define PCI224_DACCON_POLAR_UNI PCI224_DACCON_POLAR(0) /* [0,+V] */ +#define PCI224_DACCON_POLAR_BI PCI224_DACCON_POLAR(1) /* [-V,+V] */ /* (r/w) Internal Vref (PCI224 only, when LK1 in position 1-2). */ -#define PCI224_DACCON_VREF_MASK (3 << 4) -#define PCI224_DACCON_VREF_1_25 (0 << 4) /* Vref = 1.25V */ -#define PCI224_DACCON_VREF_2_5 (1 << 4) /* Vref = 2.5V */ -#define PCI224_DACCON_VREF_5 (2 << 4) /* Vref = 5V */ -#define PCI224_DACCON_VREF_10 (3 << 4) /* Vref = 10V */ +#define PCI224_DACCON_VREF(x) (((x) & 0x3) << 4) +#define PCI224_DACCON_VREF_MASK PCI224_DACCON_VREF(3) +#define PCI224_DACCON_VREF_1_25 PCI224_DACCON_VREF(0) /* 1.25V */ +#define PCI224_DACCON_VREF_2_5 PCI224_DACCON_VREF(1) /* 2.5V */ +#define PCI224_DACCON_VREF_5 PCI224_DACCON_VREF(2) /* 5V */ +#define PCI224_DACCON_VREF_10 PCI224_DACCON_VREF(3) /* 10V */ /* (r/w) Wraparound mode enable (to play back stored waveform). */ -#define PCI224_DACCON_FIFOWRAP (1 << 7) +#define PCI224_DACCON_FIFOWRAP BIT(7) /* (r/w) FIFO enable. It MUST be set! */ -#define PCI224_DACCON_FIFOENAB (1 << 8) +#define PCI224_DACCON_FIFOENAB BIT(8) /* (r/w) FIFO interrupt trigger level (most values are not very useful). */ -#define PCI224_DACCON_FIFOINTR_MASK (7 << 9) -#define PCI224_DACCON_FIFOINTR_EMPTY (0 << 9) /* when empty */ -#define PCI224_DACCON_FIFOINTR_NEMPTY (1 << 9) /* when not empty */ -#define PCI224_DACCON_FIFOINTR_NHALF (2 << 9) /* when not half full */ -#define PCI224_DACCON_FIFOINTR_HALF (3 << 9) /* when half full */ -#define PCI224_DACCON_FIFOINTR_NFULL (4 << 9) /* when not full */ -#define PCI224_DACCON_FIFOINTR_FULL (5 << 9) /* when full */ +#define PCI224_DACCON_FIFOINTR(x) (((x) & 0x7) << 9) +#define PCI224_DACCON_FIFOINTR_MASK PCI224_DACCON_FIFOINTR(7) +#define PCI224_DACCON_FIFOINTR_EMPTY PCI224_DACCON_FIFOINTR(0) /* empty */ +#define PCI224_DACCON_FIFOINTR_NEMPTY PCI224_DACCON_FIFOINTR(1) /* !empty */ +#define PCI224_DACCON_FIFOINTR_NHALF PCI224_DACCON_FIFOINTR(2) /* !half */ +#define PCI224_DACCON_FIFOINTR_HALF PCI224_DACCON_FIFOINTR(3) /* half */ +#define PCI224_DACCON_FIFOINTR_NFULL PCI224_DACCON_FIFOINTR(4) /* !full */ +#define PCI224_DACCON_FIFOINTR_FULL PCI224_DACCON_FIFOINTR(5) /* full */ /* (r-o) FIFO fill level. */ -#define PCI224_DACCON_FIFOFL_MASK (7 << 12) -#define PCI224_DACCON_FIFOFL_EMPTY (1 << 12) /* 0 */ -#define PCI224_DACCON_FIFOFL_ONETOHALF (0 << 12) /* [1,2048] */ -#define PCI224_DACCON_FIFOFL_HALFTOFULL (4 << 12) /* [2049,4095] */ -#define PCI224_DACCON_FIFOFL_FULL (6 << 12) /* 4096 */ +#define PCI224_DACCON_FIFOFL(x) (((x) & 0x7) << 12) +#define PCI224_DACCON_FIFOFL_MASK PCI224_DACCON_FIFOFL(7) +#define PCI224_DACCON_FIFOFL_EMPTY PCI224_DACCON_FIFOFL(1) /* 0 */ +#define PCI224_DACCON_FIFOFL_ONETOHALF PCI224_DACCON_FIFOFL(0) /* 1-2048 */ +#define PCI224_DACCON_FIFOFL_HALFTOFULL PCI224_DACCON_FIFOFL(4) /* 2049-4095 */ +#define PCI224_DACCON_FIFOFL_FULL PCI224_DACCON_FIFOFL(6) /* 4096 */ /* (r-o) DAC busy flag. */ -#define PCI224_DACCON_BUSY (1 << 15) +#define PCI224_DACCON_BUSY BIT(15) /* (w-o) FIFO reset. */ -#define PCI224_DACCON_FIFORESET (1 << 12) +#define PCI224_DACCON_FIFORESET BIT(12) /* (w-o) Global reset (not sure what it does). */ -#define PCI224_DACCON_GLOBALRESET (1 << 13) +#define PCI224_DACCON_GLOBALRESET BIT(13) /* * DAC FIFO size. diff --git a/drivers/staging/comedi/drivers/amplc_pci230.c b/drivers/staging/comedi/drivers/amplc_pci230.c index 907c39cc89d7..42945de31fe2 100644 --- a/drivers/staging/comedi/drivers/amplc_pci230.c +++ b/drivers/staging/comedi/drivers/amplc_pci230.c @@ -237,47 +237,50 @@ /* * DACCON read-write values. */ -#define PCI230_DAC_OR_UNI (0 << 0) /* Output range unipolar */ -#define PCI230_DAC_OR_BIP (1 << 0) /* Output range bipolar */ -#define PCI230_DAC_OR_MASK (1 << 0) +#define PCI230_DAC_OR(x) (((x) & 0x1) << 0) +#define PCI230_DAC_OR_UNI PCI230_DAC_OR(0) /* Output unipolar */ +#define PCI230_DAC_OR_BIP PCI230_DAC_OR(1) /* Output bipolar */ +#define PCI230_DAC_OR_MASK PCI230_DAC_OR(1) /* * The following applies only if DAC FIFO support is enabled in the EXTFUNC * register (and only for PCI230+ hardware version 2 onwards). */ -#define PCI230P2_DAC_FIFO_EN (1 << 8) /* FIFO enable */ +#define PCI230P2_DAC_FIFO_EN BIT(8) /* FIFO enable */ /* * The following apply only if the DAC FIFO is enabled (and only for PCI230+ * hardware version 2 onwards). */ -#define PCI230P2_DAC_TRIG_NONE (0 << 2) /* No trigger */ -#define PCI230P2_DAC_TRIG_SW (1 << 2) /* Software trigger trigger */ -#define PCI230P2_DAC_TRIG_EXTP (2 << 2) /* EXTTRIG +ve edge trigger */ -#define PCI230P2_DAC_TRIG_EXTN (3 << 2) /* EXTTRIG -ve edge trigger */ -#define PCI230P2_DAC_TRIG_Z2CT0 (4 << 2) /* CT0-OUT +ve edge trigger */ -#define PCI230P2_DAC_TRIG_Z2CT1 (5 << 2) /* CT1-OUT +ve edge trigger */ -#define PCI230P2_DAC_TRIG_Z2CT2 (6 << 2) /* CT2-OUT +ve edge trigger */ -#define PCI230P2_DAC_TRIG_MASK (7 << 2) -#define PCI230P2_DAC_FIFO_WRAP (1 << 7) /* FIFO wraparound mode */ -#define PCI230P2_DAC_INT_FIFO_EMPTY (0 << 9) /* FIFO interrupt empty */ -#define PCI230P2_DAC_INT_FIFO_NEMPTY (1 << 9) -#define PCI230P2_DAC_INT_FIFO_NHALF (2 << 9) /* FIFO intr not half full */ -#define PCI230P2_DAC_INT_FIFO_HALF (3 << 9) -#define PCI230P2_DAC_INT_FIFO_NFULL (4 << 9) /* FIFO interrupt not full */ -#define PCI230P2_DAC_INT_FIFO_FULL (5 << 9) -#define PCI230P2_DAC_INT_FIFO_MASK (7 << 9) +#define PCI230P2_DAC_TRIG(x) (((x) & 0x7) << 2) +#define PCI230P2_DAC_TRIG_NONE PCI230P2_DAC_TRIG(0) /* none */ +#define PCI230P2_DAC_TRIG_SW PCI230P2_DAC_TRIG(1) /* soft trig */ +#define PCI230P2_DAC_TRIG_EXTP PCI230P2_DAC_TRIG(2) /* ext + edge */ +#define PCI230P2_DAC_TRIG_EXTN PCI230P2_DAC_TRIG(3) /* ext - edge */ +#define PCI230P2_DAC_TRIG_Z2CT0 PCI230P2_DAC_TRIG(4) /* Z2 CT0 out */ +#define PCI230P2_DAC_TRIG_Z2CT1 PCI230P2_DAC_TRIG(5) /* Z2 CT1 out */ +#define PCI230P2_DAC_TRIG_Z2CT2 PCI230P2_DAC_TRIG(6) /* Z2 CT2 out */ +#define PCI230P2_DAC_TRIG_MASK PCI230P2_DAC_TRIG(7) +#define PCI230P2_DAC_FIFO_WRAP BIT(7) /* FIFO wraparound mode */ +#define PCI230P2_DAC_INT_FIFO(x) (((x) & 7) << 9) +#define PCI230P2_DAC_INT_FIFO_EMPTY PCI230P2_DAC_INT_FIFO(0) /* empty */ +#define PCI230P2_DAC_INT_FIFO_NEMPTY PCI230P2_DAC_INT_FIFO(1) /* !empty */ +#define PCI230P2_DAC_INT_FIFO_NHALF PCI230P2_DAC_INT_FIFO(2) /* !half */ +#define PCI230P2_DAC_INT_FIFO_HALF PCI230P2_DAC_INT_FIFO(3) /* half */ +#define PCI230P2_DAC_INT_FIFO_NFULL PCI230P2_DAC_INT_FIFO(4) /* !full */ +#define PCI230P2_DAC_INT_FIFO_FULL PCI230P2_DAC_INT_FIFO(5) /* full */ +#define PCI230P2_DAC_INT_FIFO_MASK PCI230P2_DAC_INT_FIFO(7) /* * DACCON read-only values. */ -#define PCI230_DAC_BUSY (1 << 1) /* DAC busy. */ +#define PCI230_DAC_BUSY BIT(1) /* DAC busy. */ /* * The following apply only if the DAC FIFO is enabled (and only for PCI230+ * hardware version 2 onwards). */ -#define PCI230P2_DAC_FIFO_UNDERRUN_LATCHED (1 << 5) /* Underrun error */ -#define PCI230P2_DAC_FIFO_EMPTY (1 << 13) /* FIFO empty */ -#define PCI230P2_DAC_FIFO_FULL (1 << 14) /* FIFO full */ -#define PCI230P2_DAC_FIFO_HALF (1 << 15) /* FIFO half full */ +#define PCI230P2_DAC_FIFO_UNDERRUN_LATCHED BIT(5) /* Underrun error */ +#define PCI230P2_DAC_FIFO_EMPTY BIT(13) /* FIFO empty */ +#define PCI230P2_DAC_FIFO_FULL BIT(14) /* FIFO full */ +#define PCI230P2_DAC_FIFO_HALF BIT(15) /* FIFO half full */ /* * DACCON write-only, transient values. @@ -286,8 +289,8 @@ * The following apply only if the DAC FIFO is enabled (and only for PCI230+ * hardware version 2 onwards). */ -#define PCI230P2_DAC_FIFO_UNDERRUN_CLEAR (1 << 5) /* Clear underrun */ -#define PCI230P2_DAC_FIFO_RESET (1 << 12) /* FIFO reset */ +#define PCI230P2_DAC_FIFO_UNDERRUN_CLEAR BIT(5) /* Clear underrun */ +#define PCI230P2_DAC_FIFO_RESET BIT(12) /* FIFO reset */ /* * PCI230+ hardware version 2 DAC FIFO levels. @@ -304,44 +307,48 @@ /* * ADCCON read/write values. */ -#define PCI230_ADC_TRIG_NONE (0 << 0) /* No trigger */ -#define PCI230_ADC_TRIG_SW (1 << 0) /* Software trigger trigger */ -#define PCI230_ADC_TRIG_EXTP (2 << 0) /* EXTTRIG +ve edge trigger */ -#define PCI230_ADC_TRIG_EXTN (3 << 0) /* EXTTRIG -ve edge trigger */ -#define PCI230_ADC_TRIG_Z2CT0 (4 << 0) /* CT0-OUT +ve edge trigger */ -#define PCI230_ADC_TRIG_Z2CT1 (5 << 0) /* CT1-OUT +ve edge trigger */ -#define PCI230_ADC_TRIG_Z2CT2 (6 << 0) /* CT2-OUT +ve edge trigger */ -#define PCI230_ADC_TRIG_MASK (7 << 0) -#define PCI230_ADC_IR_UNI (0 << 3) /* Input range unipolar */ -#define PCI230_ADC_IR_BIP (1 << 3) /* Input range bipolar */ -#define PCI230_ADC_IR_MASK (1 << 3) -#define PCI230_ADC_IM_SE (0 << 4) /* Input mode single ended */ -#define PCI230_ADC_IM_DIF (1 << 4) /* Input mode differential */ -#define PCI230_ADC_IM_MASK (1 << 4) -#define PCI230_ADC_FIFO_EN (1 << 8) /* FIFO enable */ -#define PCI230_ADC_INT_FIFO_EMPTY (0 << 9) -#define PCI230_ADC_INT_FIFO_NEMPTY (1 << 9) /* FIFO interrupt not empty */ -#define PCI230_ADC_INT_FIFO_NHALF (2 << 9) -#define PCI230_ADC_INT_FIFO_HALF (3 << 9) /* FIFO interrupt half full */ -#define PCI230_ADC_INT_FIFO_NFULL (4 << 9) -#define PCI230_ADC_INT_FIFO_FULL (5 << 9) /* FIFO interrupt full */ -#define PCI230P_ADC_INT_FIFO_THRESH (7 << 9) /* FIFO interrupt threshold */ -#define PCI230_ADC_INT_FIFO_MASK (7 << 9) +#define PCI230_ADC_TRIG(x) (((x) & 0x7) << 0) +#define PCI230_ADC_TRIG_NONE PCI230_ADC_TRIG(0) /* none */ +#define PCI230_ADC_TRIG_SW PCI230_ADC_TRIG(1) /* soft trig */ +#define PCI230_ADC_TRIG_EXTP PCI230_ADC_TRIG(2) /* ext + edge */ +#define PCI230_ADC_TRIG_EXTN PCI230_ADC_TRIG(3) /* ext - edge */ +#define PCI230_ADC_TRIG_Z2CT0 PCI230_ADC_TRIG(4) /* Z2 CT0 out*/ +#define PCI230_ADC_TRIG_Z2CT1 PCI230_ADC_TRIG(5) /* Z2 CT1 out */ +#define PCI230_ADC_TRIG_Z2CT2 PCI230_ADC_TRIG(6) /* Z2 CT2 out */ +#define PCI230_ADC_TRIG_MASK PCI230_ADC_TRIG(7) +#define PCI230_ADC_IR(x) (((x) & 0x1) << 3) +#define PCI230_ADC_IR_UNI PCI230_ADC_IR(0) /* Input unipolar */ +#define PCI230_ADC_IR_BIP PCI230_ADC_IR(1) /* Input bipolar */ +#define PCI230_ADC_IR_MASK PCI230_ADC_IR(1) +#define PCI230_ADC_IM(x) (((x) & 0x1) << 4) +#define PCI230_ADC_IM_SE PCI230_ADC_IM(0) /* single ended */ +#define PCI230_ADC_IM_DIF PCI230_ADC_IM(1) /* differential */ +#define PCI230_ADC_IM_MASK PCI230_ADC_IM(1) +#define PCI230_ADC_FIFO_EN BIT(8) /* FIFO enable */ +#define PCI230_ADC_INT_FIFO(x) (((x) & 0x7) << 9) +#define PCI230_ADC_INT_FIFO_EMPTY PCI230_ADC_INT_FIFO(0) /* empty */ +#define PCI230_ADC_INT_FIFO_NEMPTY PCI230_ADC_INT_FIFO(1) /* !empty */ +#define PCI230_ADC_INT_FIFO_NHALF PCI230_ADC_INT_FIFO(2) /* !half */ +#define PCI230_ADC_INT_FIFO_HALF PCI230_ADC_INT_FIFO(3) /* half */ +#define PCI230_ADC_INT_FIFO_NFULL PCI230_ADC_INT_FIFO(4) /* !full */ +#define PCI230_ADC_INT_FIFO_FULL PCI230_ADC_INT_FIFO(5) /* full */ +#define PCI230P_ADC_INT_FIFO_THRESH PCI230_ADC_INT_FIFO(7) /* threshold */ +#define PCI230_ADC_INT_FIFO_MASK PCI230_ADC_INT_FIFO(7) /* * ADCCON write-only, transient values. */ -#define PCI230_ADC_FIFO_RESET (1 << 12) /* FIFO reset */ -#define PCI230_ADC_GLOB_RESET (1 << 13) /* Global reset */ +#define PCI230_ADC_FIFO_RESET BIT(12) /* FIFO reset */ +#define PCI230_ADC_GLOB_RESET BIT(13) /* Global reset */ /* * ADCCON read-only values. */ -#define PCI230_ADC_BUSY (1 << 15) /* ADC busy */ -#define PCI230_ADC_FIFO_EMPTY (1 << 12) /* FIFO empty */ -#define PCI230_ADC_FIFO_FULL (1 << 13) /* FIFO full */ -#define PCI230_ADC_FIFO_HALF (1 << 14) /* FIFO half full */ -#define PCI230_ADC_FIFO_FULL_LATCHED (1 << 5) /* FIFO overrun occurred */ +#define PCI230_ADC_BUSY BIT(15) /* ADC busy */ +#define PCI230_ADC_FIFO_EMPTY BIT(12) /* FIFO empty */ +#define PCI230_ADC_FIFO_FULL BIT(13) /* FIFO full */ +#define PCI230_ADC_FIFO_HALF BIT(14) /* FIFO half full */ +#define PCI230_ADC_FIFO_FULL_LATCHED BIT(5) /* FIFO overrun occurred */ /* * PCI230 ADC FIFO levels. @@ -353,10 +360,10 @@ * PCI230+ EXTFUNC values. */ /* Route EXTTRIG pin to external gate inputs. */ -#define PCI230P_EXTFUNC_GAT_EXTTRIG (1 << 0) +#define PCI230P_EXTFUNC_GAT_EXTTRIG BIT(0) /* PCI230+ hardware version 2 values. */ /* Allow DAC FIFO to be enabled. */ -#define PCI230P2_EXTFUNC_DACFIFO (1 << 1) +#define PCI230P2_EXTFUNC_DACFIFO BIT(1) /* * Counter/timer clock input configuration sources. @@ -379,8 +386,12 @@ #define GAT_GND 1 /* GND (i.e. disabled) */ #define GAT_EXT 2 /* external gate input (PPCn on PCI230) */ #define GAT_NOUTNM2 3 /* inverted output of channel-2 modulo total */ -/* Macro to construct gate input configuration register value. */ -#define GAT_CONFIG(chan, src) ((((chan) & 3) << 3) | ((src) & 7)) + +static inline unsigned int pci230_gat_config(unsigned int chan, + unsigned int src) +{ + return ((chan & 3) << 3) | (src & 7); +} /* * Summary of CLK_OUTNM1 and GAT_NOUTNM2 connections for PCI230 and PCI260: @@ -398,20 +409,20 @@ * Interrupt enables/status register values. */ #define PCI230_INT_DISABLE 0 -#define PCI230_INT_PPI_C0 (1 << 0) -#define PCI230_INT_PPI_C3 (1 << 1) -#define PCI230_INT_ADC (1 << 2) -#define PCI230_INT_ZCLK_CT1 (1 << 5) +#define PCI230_INT_PPI_C0 BIT(0) +#define PCI230_INT_PPI_C3 BIT(1) +#define PCI230_INT_ADC BIT(2) +#define PCI230_INT_ZCLK_CT1 BIT(5) /* For PCI230+ hardware version 2 when DAC FIFO enabled. */ -#define PCI230P2_INT_DAC (1 << 4) +#define PCI230P2_INT_DAC BIT(4) /* * (Potentially) shared resources and their owners */ enum { - RES_Z2CT0 = (1U << 0), /* Z2-CT0 */ - RES_Z2CT1 = (1U << 1), /* Z2-CT1 */ - RES_Z2CT2 = (1U << 2) /* Z2-CT2 */ + RES_Z2CT0 = BIT(0), /* Z2-CT0 */ + RES_Z2CT1 = BIT(1), /* Z2-CT1 */ + RES_Z2CT2 = BIT(2) /* Z2-CT2 */ }; enum { @@ -626,10 +637,10 @@ static void pci230_release_all_resources(struct comedi_device *dev, pci230_release_shared(dev, (unsigned char)~0, owner); } -static unsigned int pci230_divide_ns(uint64_t ns, unsigned int timebase, +static unsigned int pci230_divide_ns(u64 ns, unsigned int timebase, unsigned int flags) { - uint64_t div; + u64 div; unsigned int rem; div = ns; @@ -652,7 +663,7 @@ static unsigned int pci230_divide_ns(uint64_t ns, unsigned int timebase, * Given desired period in ns, returns the required internal clock source * and gets the initial count. */ -static unsigned int pci230_choose_clk_count(uint64_t ns, unsigned int *count, +static unsigned int pci230_choose_clk_count(u64 ns, unsigned int *count, unsigned int flags) { unsigned int clk_src, cnt; @@ -676,7 +687,7 @@ static void pci230_ns_to_single_timer(unsigned int *ns, unsigned int flags) } static void pci230_ct_setup_ns_mode(struct comedi_device *dev, unsigned int ct, - unsigned int mode, uint64_t ns, + unsigned int mode, u64 ns, unsigned int flags) { unsigned int clk_src; @@ -1263,7 +1274,8 @@ static void pci230_ao_start(struct comedi_device *dev, irqflags); } /* Set CT1 gate high to start counting. */ - outb(GAT_CONFIG(1, GAT_VCC), dev->iobase + PCI230_ZGAT_SCE); + outb(pci230_gat_config(1, GAT_VCC), + dev->iobase + PCI230_ZGAT_SCE); break; case TRIG_INT: async->inttrig = pci230_ao_inttrig_scan_begin; @@ -1351,7 +1363,8 @@ static int pci230_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s) * cmd->scan_begin_arg is sampling period in ns. * Gate it off for now. */ - outb(GAT_CONFIG(1, GAT_GND), dev->iobase + PCI230_ZGAT_SCE); + outb(pci230_gat_config(1, GAT_GND), + dev->iobase + PCI230_ZGAT_SCE); pci230_ct_setup_ns_mode(dev, 1, I8254_MODE3, cmd->scan_begin_arg, cmd->flags); @@ -1792,9 +1805,9 @@ static int pci230_ai_inttrig_scan_begin(struct comedi_device *dev, spin_lock_irqsave(&devpriv->ai_stop_spinlock, irqflags); if (devpriv->ai_cmd_started) { /* Trigger scan by waggling CT0 gate source. */ - zgat = GAT_CONFIG(0, GAT_GND); + zgat = pci230_gat_config(0, GAT_GND); outb(zgat, dev->iobase + PCI230_ZGAT_SCE); - zgat = GAT_CONFIG(0, GAT_VCC); + zgat = pci230_gat_config(0, GAT_VCC); outb(zgat, dev->iobase + PCI230_ZGAT_SCE); } spin_unlock_irqrestore(&devpriv->ai_stop_spinlock, irqflags); @@ -1926,20 +1939,20 @@ static void pci230_ai_start(struct comedi_device *dev, * Conversion timer CT2 needs to be gated by * inverted output of monostable CT2. */ - zgat = GAT_CONFIG(2, GAT_NOUTNM2); + zgat = pci230_gat_config(2, GAT_NOUTNM2); } else { /* * Conversion timer CT2 needs to be gated on * continuously. */ - zgat = GAT_CONFIG(2, GAT_VCC); + zgat = pci230_gat_config(2, GAT_VCC); } outb(zgat, dev->iobase + PCI230_ZGAT_SCE); if (cmd->scan_begin_src != TRIG_FOLLOW) { /* Set monostable CT0 trigger source. */ switch (cmd->scan_begin_src) { default: - zgat = GAT_CONFIG(0, GAT_VCC); + zgat = pci230_gat_config(0, GAT_VCC); break; case TRIG_EXT: /* @@ -1950,21 +1963,21 @@ static void pci230_ai_start(struct comedi_device *dev, * input in order to use it as an external scan * trigger. */ - zgat = GAT_CONFIG(0, GAT_EXT); + zgat = pci230_gat_config(0, GAT_EXT); break; case TRIG_TIMER: /* * Monostable CT0 triggered by rising edge on * inverted output of CT1 (falling edge on CT1). */ - zgat = GAT_CONFIG(0, GAT_NOUTNM2); + zgat = pci230_gat_config(0, GAT_NOUTNM2); break; case TRIG_INT: /* * Monostable CT0 is triggered by inttrig * function waggling the CT0 gate source. */ - zgat = GAT_CONFIG(0, GAT_VCC); + zgat = pci230_gat_config(0, GAT_VCC); break; } outb(zgat, dev->iobase + PCI230_ZGAT_SCE); @@ -1974,7 +1987,7 @@ static void pci230_ai_start(struct comedi_device *dev, * Scan period timer CT1 needs to be * gated on to start counting. */ - zgat = GAT_CONFIG(1, GAT_VCC); + zgat = pci230_gat_config(1, GAT_VCC); outb(zgat, dev->iobase + PCI230_ZGAT_SCE); break; case TRIG_INT: @@ -2216,7 +2229,7 @@ static int pci230_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) * Note, counter/timer output 2 can be monitored on the * connector: PCI230 pin 21, PCI260 pin 18. */ - zgat = GAT_CONFIG(2, GAT_GND); + zgat = pci230_gat_config(2, GAT_GND); outb(zgat, dev->iobase + PCI230_ZGAT_SCE); /* Set counter/timer 2 to the specified conversion period. */ pci230_ct_setup_ns_mode(dev, 2, I8254_MODE3, cmd->convert_arg, @@ -2234,10 +2247,10 @@ static int pci230_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) * monostable to stop it triggering. The trigger * source will be changed later. */ - zgat = GAT_CONFIG(0, GAT_VCC); + zgat = pci230_gat_config(0, GAT_VCC); outb(zgat, dev->iobase + PCI230_ZGAT_SCE); pci230_ct_setup_ns_mode(dev, 0, I8254_MODE1, - ((uint64_t)cmd->convert_arg * + ((u64)cmd->convert_arg * cmd->scan_end_arg), CMDF_ROUND_UP); if (cmd->scan_begin_src == TRIG_TIMER) { @@ -2247,7 +2260,7 @@ static int pci230_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) * * Set up CT1 but gate it off for now. */ - zgat = GAT_CONFIG(1, GAT_GND); + zgat = pci230_gat_config(1, GAT_GND); outb(zgat, dev->iobase + PCI230_ZGAT_SCE); pci230_ct_setup_ns_mode(dev, 1, I8254_MODE3, cmd->scan_begin_arg, diff --git a/drivers/staging/comedi/drivers/amplc_pci263.c b/drivers/staging/comedi/drivers/amplc_pci263.c index b6768aa90547..8d4069bc5716 100644 --- a/drivers/staging/comedi/drivers/amplc_pci263.c +++ b/drivers/staging/comedi/drivers/amplc_pci263.c @@ -1,49 +1,53 @@ /* - comedi/drivers/amplc_pci263.c - Driver for Amplicon PCI263 relay board. + * Driver for Amplicon PCI263 relay board. + * + * Copyright (C) 2002 MEV Ltd. <http://www.mev.co.uk/> + * + * COMEDI - Linux Control and Measurement Device Interface + * Copyright (C) 2000 David A. Schleef <ds@schleef.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ - Copyright (C) 2002 MEV Ltd. <http://www.mev.co.uk/> - - COMEDI - Linux Control and Measurement Device Interface - Copyright (C) 2000 David A. Schleef <ds@schleef.org> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*/ /* -Driver: amplc_pci263 -Description: Amplicon PCI263 -Author: Ian Abbott <abbotti@mev.co.uk> -Devices: [Amplicon] PCI263 (amplc_pci263) -Updated: Fri, 12 Apr 2013 15:19:36 +0100 -Status: works - -Configuration options: not applicable, uses PCI auto config - -The board appears as one subdevice, with 16 digital outputs, each -connected to a reed-relay. Relay contacts are closed when output is 1. -The state of the outputs can be read. -*/ + * Driver: amplc_pci263 + * Description: Amplicon PCI263 + * Author: Ian Abbott <abbotti@mev.co.uk> + * Devices: [Amplicon] PCI263 (amplc_pci263) + * Updated: Fri, 12 Apr 2013 15:19:36 +0100 + * Status: works + * + * Configuration options: not applicable, uses PCI auto config + * + * The board appears as one subdevice, with 16 digital outputs, each + * connected to a reed-relay. Relay contacts are closed when output is 1. + * The state of the outputs can be read. + */ #include <linux/module.h> #include "../comedi_pci.h" +/* PCI263 registers */ +#define PCI263_DO_0_7_REG 0x00 +#define PCI263_DO_8_15_REG 0x01 + static int pci263_do_insn_bits(struct comedi_device *dev, struct comedi_subdevice *s, struct comedi_insn *insn, unsigned int *data) { if (comedi_dio_update_state(s, data)) { - outb(s->state & 0xff, dev->iobase); - outb((s->state >> 8) & 0xff, dev->iobase + 1); + outb(s->state & 0xff, dev->iobase + PCI263_DO_0_7_REG); + outb((s->state >> 8) & 0xff, dev->iobase + PCI263_DO_8_15_REG); } data[1] = s->state; @@ -67,16 +71,18 @@ static int pci263_auto_attach(struct comedi_device *dev, if (ret) return ret; + /* Digital Output subdevice */ s = &dev->subdevices[0]; - /* digital output subdevice */ - s->type = COMEDI_SUBD_DO; - s->subdev_flags = SDF_WRITABLE; - s->n_chan = 16; - s->maxdata = 1; - s->range_table = &range_digital; - s->insn_bits = pci263_do_insn_bits; + s->type = COMEDI_SUBD_DO; + s->subdev_flags = SDF_WRITABLE; + s->n_chan = 16; + s->maxdata = 1; + s->range_table = &range_digital; + s->insn_bits = pci263_do_insn_bits; + /* read initial relay state */ - s->state = inb(dev->iobase) | (inb(dev->iobase + 1) << 8); + s->state = inb(dev->iobase + PCI263_DO_0_7_REG) | + (inb(dev->iobase + PCI263_DO_8_15_REG) << 8); return 0; } diff --git a/drivers/staging/comedi/drivers/c6xdigio.c b/drivers/staging/comedi/drivers/c6xdigio.c index 1a109e30d8ff..8ee732571588 100644 --- a/drivers/staging/comedi/drivers/c6xdigio.c +++ b/drivers/staging/comedi/drivers/c6xdigio.c @@ -47,8 +47,8 @@ */ #define C6XDIGIO_DATA_REG 0x00 #define C6XDIGIO_DATA_CHAN(x) (((x) + 1) << 4) -#define C6XDIGIO_DATA_PWM (1 << 5) -#define C6XDIGIO_DATA_ENCODER (1 << 6) +#define C6XDIGIO_DATA_PWM BIT(5) +#define C6XDIGIO_DATA_ENCODER BIT(6) #define C6XDIGIO_STATUS_REG 0x01 #define C6XDIGIO_CTRL_REG 0x02 diff --git a/drivers/staging/comedi/drivers/comedi_8254.h b/drivers/staging/comedi/drivers/comedi_8254.h index f4610ead6172..a12c29455d9d 100644 --- a/drivers/staging/comedi/drivers/comedi_8254.h +++ b/drivers/staging/comedi/drivers/comedi_8254.h @@ -53,13 +53,15 @@ struct comedi_subdevice; #define I8254_COUNTER2_REG 0x02 #define I8254_CTRL_REG 0x03 #define I8254_CTRL_SEL_CTR(x) ((x) << 6) -#define I8254_CTRL_READBACK_COUNT ((3 << 6) | (1 << 4)) -#define I8254_CTRL_READBACK_STATUS ((3 << 6) | (1 << 5)) +#define I8254_CTRL_READBACK(x) (I8254_CTRL_SEL_CTR(3) | BIT(x)) +#define I8254_CTRL_READBACK_COUNT I8254_CTRL_READBACK(4) +#define I8254_CTRL_READBACK_STATUS I8254_CTRL_READBACK(5) #define I8254_CTRL_READBACK_SEL_CTR(x) (2 << (x)) -#define I8254_CTRL_LATCH (0 << 4) -#define I8254_CTRL_LSB_ONLY (1 << 4) -#define I8254_CTRL_MSB_ONLY (2 << 4) -#define I8254_CTRL_LSB_MSB (3 << 4) +#define I8254_CTRL_RW(x) (((x) & 0x3) << 4) +#define I8254_CTRL_LATCH I8254_CTRL_RW(0) +#define I8254_CTRL_LSB_ONLY I8254_CTRL_RW(1) +#define I8254_CTRL_MSB_ONLY I8254_CTRL_RW(2) +#define I8254_CTRL_LSB_MSB I8254_CTRL_RW(3) /* counter maps zero to 0x10000 */ #define I8254_MAX_COUNT 0x10000 diff --git a/drivers/staging/comedi/drivers/das1800.c b/drivers/staging/comedi/drivers/das1800.c index 940781183fac..e0a34c2687a8 100644 --- a/drivers/staging/comedi/drivers/das1800.c +++ b/drivers/staging/comedi/drivers/das1800.c @@ -1,98 +1,82 @@ /* - comedi/drivers/das1800.c - Driver for Keitley das1700/das1800 series boards - Copyright (C) 2000 Frank Mori Hess <fmhess@users.sourceforge.net> - - COMEDI - Linux Control and Measurement Device Interface - Copyright (C) 2000 David A. Schleef <ds@schleef.org> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*/ -/* -Driver: das1800 -Description: Keithley Metrabyte DAS1800 (& compatibles) -Author: Frank Mori Hess <fmhess@users.sourceforge.net> -Devices: [Keithley Metrabyte] DAS-1701ST (das-1701st), - DAS-1701ST-DA (das-1701st-da), DAS-1701/AO (das-1701ao), - DAS-1702ST (das-1702st), DAS-1702ST-DA (das-1702st-da), - DAS-1702HR (das-1702hr), DAS-1702HR-DA (das-1702hr-da), - DAS-1702/AO (das-1702ao), DAS-1801ST (das-1801st), - DAS-1801ST-DA (das-1801st-da), DAS-1801HC (das-1801hc), - DAS-1801AO (das-1801ao), DAS-1802ST (das-1802st), - DAS-1802ST-DA (das-1802st-da), DAS-1802HR (das-1802hr), - DAS-1802HR-DA (das-1802hr-da), DAS-1802HC (das-1802hc), - DAS-1802AO (das-1802ao) -Status: works - -The waveform analog output on the 'ao' cards is not supported. -If you need it, send me (Frank Hess) an email. - -Configuration options: - [0] - I/O port base address - [1] - IRQ (optional, required for timed or externally triggered conversions) - [2] - DMA0 (optional, requires irq) - [3] - DMA1 (optional, requires irq and dma0) -*/ -/* + * Comedi driver for Keithley DAS-1700/DAS-1800 series boards + * Copyright (C) 2000 Frank Mori Hess <fmhess@users.sourceforge.net> + * + * COMEDI - Linux Control and Measurement Device Interface + * Copyright (C) 2000 David A. Schleef <ds@schleef.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ -This driver supports the following Keithley boards: - -das-1701st -das-1701st-da -das-1701ao -das-1702st -das-1702st-da -das-1702hr -das-1702hr-da -das-1702ao -das-1801st -das-1801st-da -das-1801hc -das-1801ao -das-1802st -das-1802st-da -das-1802hr -das-1802hr-da -das-1802hc -das-1802ao - -Options: - [0] - base io address - [1] - irq (optional, required for timed or externally triggered conversions) - [2] - dma0 (optional, requires irq) - [3] - dma1 (optional, requires irq and dma0) - -irq can be omitted, although the cmd interface will not work without it. - -analog input cmd triggers supported: - start_src: TRIG_NOW | TRIG_EXT - scan_begin_src: TRIG_FOLLOW | TRIG_TIMER | TRIG_EXT - scan_end_src: TRIG_COUNT - convert_src: TRIG_TIMER | TRIG_EXT (TRIG_EXT requires scan_begin_src == TRIG_FOLLOW) - stop_src: TRIG_COUNT | TRIG_EXT | TRIG_NONE - -scan_begin_src triggers TRIG_TIMER and TRIG_EXT use the card's -'burst mode' which limits the valid conversion time to 64 microseconds -(convert_arg <= 64000). This limitation does not apply if scan_begin_src -is TRIG_FOLLOW. - -NOTES: -Only the DAS-1801ST has been tested by me. -Unipolar and bipolar ranges cannot be mixed in the channel/gain list. - -TODO: - Make it automatically allocate irq and dma channels if they are not specified - Add support for analog out on 'ao' cards - read insn for analog out -*/ +/* + * Driver: das1800 + * Description: Keithley Metrabyte DAS1800 (& compatibles) + * Author: Frank Mori Hess <fmhess@users.sourceforge.net> + * Devices: [Keithley Metrabyte] DAS-1701ST (das-1701st), + * DAS-1701ST-DA (das-1701st-da), DAS-1701/AO (das-1701ao), + * DAS-1702ST (das-1702st), DAS-1702ST-DA (das-1702st-da), + * DAS-1702HR (das-1702hr), DAS-1702HR-DA (das-1702hr-da), + * DAS-1702/AO (das-1702ao), DAS-1801ST (das-1801st), + * DAS-1801ST-DA (das-1801st-da), DAS-1801HC (das-1801hc), + * DAS-1801AO (das-1801ao), DAS-1802ST (das-1802st), + * DAS-1802ST-DA (das-1802st-da), DAS-1802HR (das-1802hr), + * DAS-1802HR-DA (das-1802hr-da), DAS-1802HC (das-1802hc), + * DAS-1802AO (das-1802ao) + * Status: works + * + * Configuration options: + * [0] - I/O port base address + * [1] - IRQ (optional, required for analog input cmd support) + * [2] - DMA0 (optional, requires irq) + * [3] - DMA1 (optional, requires irq and dma0) + * + * analog input cmd triggers supported: + * + * start_src TRIG_NOW command starts immediately + * TRIG_EXT command starts on external pin TGIN + * + * scan_begin_src TRIG_FOLLOW paced/external scans start immediately + * TRIG_TIMER burst scans start periodically + * TRIG_EXT burst scans start on external pin XPCLK + * + * scan_end_src TRIG_COUNT scan ends after last channel + * + * convert_src TRIG_TIMER paced/burst conversions are timed + * TRIG_EXT conversions on external pin XPCLK + * (requires scan_begin_src == TRIG_FOLLOW) + * + * stop_src TRIG_COUNT command stops after stop_arg scans + * TRIG_EXT command stops on external pin TGIN + * TRIG_NONE command runs until canceled + * + * If TRIG_EXT is used for both the start_src and stop_src, the first TGIN + * trigger starts the command, and the second trigger will stop it. If only + * one is TRIG_EXT, the first trigger will either stop or start the command. + * The external pin TGIN is normally set for negative edge triggering. It + * can be set to positive edge with the CR_INVERT flag. If TRIG_EXT is used + * for both the start_src and stop_src they must have the same polarity. + * + * Minimum conversion speed is limited to 64 microseconds (convert_arg <= 64000) + * for 'burst' scans. This limitation does not apply for 'paced' scans. The + * maximum conversion speed is limited by the board (convert_arg >= ai_speed). + * Maximum conversion speeds are not always achievable depending on the + * board setup (see user manual). + * + * NOTES: + * Only the DAS-1801ST has been tested by me. + * Unipolar and bipolar ranges cannot be mixed in the channel/gain list. + * + * The waveform analog output on the 'ao' cards is not supported. + * If you need it, send me (Frank Hess) an email. + */ #include <linux/module.h> #include <linux/interrupt.h> @@ -107,7 +91,6 @@ TODO: /* misc. defines */ #define DAS1800_SIZE 16 /* uses 16 io addresses */ #define FIFO_SIZE 1024 /* 1024 sample fifo */ -#define UNIPOLAR 0x4 /* bit that determines whether input range is uni/bipolar */ #define DMA_BUF_SIZE 0x1ff00 /* size in bytes of dma buffers */ /* Registers for the das1800 */ @@ -125,6 +108,7 @@ TODO: #define CGSL 0x8 #define TGEN 0x10 #define TGSL 0x20 +#define TGPL 0x40 #define ATEN 0x80 #define DAS1800_CONTROL_B 0x5 #define DMA_CH5 0x1 @@ -133,7 +117,7 @@ TODO: #define DMA_CH5_CH6 0x5 #define DMA_CH6_CH7 0x6 #define DMA_CH7_CH5 0x7 -#define DMA_ENABLED 0x3 /* mask used to determine if dma is enabled */ +#define DMA_ENABLED 0x3 #define DMA_DUAL 0x4 #define IRQ3 0x8 #define IRQ5 0x10 @@ -151,319 +135,214 @@ TODO: #define SD 0x40 #define UB 0x80 #define DAS1800_STATUS 0x7 -/* bits that prevent interrupt status bits (and CVEN) from being cleared on write */ -#define CLEAR_INTR_MASK (CVEN_MASK | 0x1f) #define INT 0x1 #define DMATC 0x2 #define CT0TC 0x8 #define OVF 0x10 #define FHF 0x20 #define FNE 0x40 -#define CVEN_MASK 0x40 /* masks CVEN on write */ #define CVEN 0x80 +#define CVEN_MASK 0x40 +#define CLEAR_INTR_MASK (CVEN_MASK | 0x1f) #define DAS1800_BURST_LENGTH 0x8 #define DAS1800_BURST_RATE 0x9 #define DAS1800_QRAM_ADDRESS 0xa #define DAS1800_COUNTER 0xc -#define IOBASE2 0x400 /* offset of additional ioports used on 'ao' cards */ +#define IOBASE2 0x400 -enum { - das1701st, das1701st_da, das1702st, das1702st_da, das1702hr, - das1702hr_da, - das1701ao, das1702ao, das1801st, das1801st_da, das1802st, das1802st_da, - das1802hr, das1802hr_da, das1801hc, das1802hc, das1801ao, das1802ao -}; - -/* analog input ranges */ -static const struct comedi_lrange range_ai_das1801 = { +static const struct comedi_lrange das1801_ai_range = { 8, { - BIP_RANGE(5), - BIP_RANGE(1), - BIP_RANGE(0.1), - BIP_RANGE(0.02), - UNI_RANGE(5), - UNI_RANGE(1), - UNI_RANGE(0.1), - UNI_RANGE(0.02) + BIP_RANGE(5), /* bipolar gain = 1 */ + BIP_RANGE(1), /* bipolar gain = 10 */ + BIP_RANGE(0.1), /* bipolar gain = 50 */ + BIP_RANGE(0.02), /* bipolar gain = 250 */ + UNI_RANGE(5), /* unipolar gain = 1 */ + UNI_RANGE(1), /* unipolar gain = 10 */ + UNI_RANGE(0.1), /* unipolar gain = 50 */ + UNI_RANGE(0.02) /* unipolar gain = 250 */ } }; -static const struct comedi_lrange range_ai_das1802 = { +static const struct comedi_lrange das1802_ai_range = { 8, { - BIP_RANGE(10), - BIP_RANGE(5), - BIP_RANGE(2.5), - BIP_RANGE(1.25), - UNI_RANGE(10), - UNI_RANGE(5), - UNI_RANGE(2.5), - UNI_RANGE(1.25) + BIP_RANGE(10), /* bipolar gain = 1 */ + BIP_RANGE(5), /* bipolar gain = 2 */ + BIP_RANGE(2.5), /* bipolar gain = 4 */ + BIP_RANGE(1.25), /* bipolar gain = 8 */ + UNI_RANGE(10), /* unipolar gain = 1 */ + UNI_RANGE(5), /* unipolar gain = 2 */ + UNI_RANGE(2.5), /* unipolar gain = 4 */ + UNI_RANGE(1.25) /* unipolar gain = 8 */ } }; +/* + * The waveform analog outputs on the 'ao' boards are not currently + * supported. They have a comedi_lrange of: + * { 2, { BIP_RANGE(10), BIP_RANGE(5) } } + */ + +enum das1800_boardid { + BOARD_DAS1701ST, + BOARD_DAS1701ST_DA, + BOARD_DAS1702ST, + BOARD_DAS1702ST_DA, + BOARD_DAS1702HR, + BOARD_DAS1702HR_DA, + BOARD_DAS1701AO, + BOARD_DAS1702AO, + BOARD_DAS1801ST, + BOARD_DAS1801ST_DA, + BOARD_DAS1802ST, + BOARD_DAS1802ST_DA, + BOARD_DAS1802HR, + BOARD_DAS1802HR_DA, + BOARD_DAS1801HC, + BOARD_DAS1802HC, + BOARD_DAS1801AO, + BOARD_DAS1802AO +}; + +/* board probe id values (hi byte of the digital input register) */ +#define DAS1800_ID_ST_DA 0x3 +#define DAS1800_ID_HR_DA 0x4 +#define DAS1800_ID_AO 0x5 +#define DAS1800_ID_HR 0x6 +#define DAS1800_ID_ST 0x7 +#define DAS1800_ID_HC 0x8 + struct das1800_board { const char *name; - int ai_speed; /* max conversion period in nanoseconds */ - int resolution; /* bits of ai resolution */ - int qram_len; /* length of card's channel / gain queue */ - int common; /* supports AREF_COMMON flag */ - int do_n_chan; /* number of digital output channels */ - int ao_ability; /* 0 == no analog out, 1 == basic analog out, 2 == waveform analog out */ - int ao_n_chan; /* number of analog out channels */ - const struct comedi_lrange *range_ai; /* available input ranges */ + unsigned char id; + unsigned int ai_speed; + unsigned int is_01_series:1; }; -/* Warning: the maximum conversion speeds listed below are - * not always achievable depending on board setup (see - * user manual.) - */ static const struct das1800_board das1800_boards[] = { - { - .name = "das-1701st", - .ai_speed = 6250, - .resolution = 12, - .qram_len = 256, - .common = 1, - .do_n_chan = 4, - .ao_ability = 0, - .ao_n_chan = 0, - .range_ai = &range_ai_das1801, - }, - { - .name = "das-1701st-da", - .ai_speed = 6250, - .resolution = 12, - .qram_len = 256, - .common = 1, - .do_n_chan = 4, - .ao_ability = 1, - .ao_n_chan = 4, - .range_ai = &range_ai_das1801, - }, - { - .name = "das-1702st", - .ai_speed = 6250, - .resolution = 12, - .qram_len = 256, - .common = 1, - .do_n_chan = 4, - .ao_ability = 0, - .ao_n_chan = 0, - .range_ai = &range_ai_das1802, - }, - { - .name = "das-1702st-da", - .ai_speed = 6250, - .resolution = 12, - .qram_len = 256, - .common = 1, - .do_n_chan = 4, - .ao_ability = 1, - .ao_n_chan = 4, - .range_ai = &range_ai_das1802, - }, - { - .name = "das-1702hr", - .ai_speed = 20000, - .resolution = 16, - .qram_len = 256, - .common = 1, - .do_n_chan = 4, - .ao_ability = 0, - .ao_n_chan = 0, - .range_ai = &range_ai_das1802, - }, - { - .name = "das-1702hr-da", - .ai_speed = 20000, - .resolution = 16, - .qram_len = 256, - .common = 1, - .do_n_chan = 4, - .ao_ability = 1, - .ao_n_chan = 2, - .range_ai = &range_ai_das1802, - }, - { - .name = "das-1701ao", - .ai_speed = 6250, - .resolution = 12, - .qram_len = 256, - .common = 1, - .do_n_chan = 4, - .ao_ability = 2, - .ao_n_chan = 2, - .range_ai = &range_ai_das1801, - }, - { - .name = "das-1702ao", - .ai_speed = 6250, - .resolution = 12, - .qram_len = 256, - .common = 1, - .do_n_chan = 4, - .ao_ability = 2, - .ao_n_chan = 2, - .range_ai = &range_ai_das1802, - }, - { - .name = "das-1801st", - .ai_speed = 3000, - .resolution = 12, - .qram_len = 256, - .common = 1, - .do_n_chan = 4, - .ao_ability = 0, - .ao_n_chan = 0, - .range_ai = &range_ai_das1801, - }, - { - .name = "das-1801st-da", - .ai_speed = 3000, - .resolution = 12, - .qram_len = 256, - .common = 1, - .do_n_chan = 4, - .ao_ability = 0, - .ao_n_chan = 4, - .range_ai = &range_ai_das1801, - }, - { - .name = "das-1802st", - .ai_speed = 3000, - .resolution = 12, - .qram_len = 256, - .common = 1, - .do_n_chan = 4, - .ao_ability = 0, - .ao_n_chan = 0, - .range_ai = &range_ai_das1802, - }, - { - .name = "das-1802st-da", - .ai_speed = 3000, - .resolution = 12, - .qram_len = 256, - .common = 1, - .do_n_chan = 4, - .ao_ability = 1, - .ao_n_chan = 4, - .range_ai = &range_ai_das1802, - }, - { - .name = "das-1802hr", - .ai_speed = 10000, - .resolution = 16, - .qram_len = 256, - .common = 1, - .do_n_chan = 4, - .ao_ability = 0, - .ao_n_chan = 0, - .range_ai = &range_ai_das1802, - }, - { - .name = "das-1802hr-da", - .ai_speed = 10000, - .resolution = 16, - .qram_len = 256, - .common = 1, - .do_n_chan = 4, - .ao_ability = 1, - .ao_n_chan = 2, - .range_ai = &range_ai_das1802, - }, - { - .name = "das-1801hc", - .ai_speed = 3000, - .resolution = 12, - .qram_len = 64, - .common = 0, - .do_n_chan = 8, - .ao_ability = 1, - .ao_n_chan = 2, - .range_ai = &range_ai_das1801, - }, - { - .name = "das-1802hc", - .ai_speed = 3000, - .resolution = 12, - .qram_len = 64, - .common = 0, - .do_n_chan = 8, - .ao_ability = 1, - .ao_n_chan = 2, - .range_ai = &range_ai_das1802, - }, - { - .name = "das-1801ao", - .ai_speed = 3000, - .resolution = 12, - .qram_len = 256, - .common = 1, - .do_n_chan = 4, - .ao_ability = 2, - .ao_n_chan = 2, - .range_ai = &range_ai_das1801, - }, - { - .name = "das-1802ao", - .ai_speed = 3000, - .resolution = 12, - .qram_len = 256, - .common = 1, - .do_n_chan = 4, - .ao_ability = 2, - .ao_n_chan = 2, - .range_ai = &range_ai_das1802, - }, + [BOARD_DAS1701ST] = { + .name = "das-1701st", + .id = DAS1800_ID_ST, + .ai_speed = 6250, + .is_01_series = 1, + }, + [BOARD_DAS1701ST_DA] = { + .name = "das-1701st-da", + .id = DAS1800_ID_ST_DA, + .ai_speed = 6250, + .is_01_series = 1, + }, + [BOARD_DAS1702ST] = { + .name = "das-1702st", + .id = DAS1800_ID_ST, + .ai_speed = 6250, + }, + [BOARD_DAS1702ST_DA] = { + .name = "das-1702st-da", + .id = DAS1800_ID_ST_DA, + .ai_speed = 6250, + }, + [BOARD_DAS1702HR] = { + .name = "das-1702hr", + .id = DAS1800_ID_HR, + .ai_speed = 20000, + }, + [BOARD_DAS1702HR_DA] = { + .name = "das-1702hr-da", + .id = DAS1800_ID_HR_DA, + .ai_speed = 20000, + }, + [BOARD_DAS1701AO] = { + .name = "das-1701ao", + .id = DAS1800_ID_AO, + .ai_speed = 6250, + .is_01_series = 1, + }, + [BOARD_DAS1702AO] = { + .name = "das-1702ao", + .id = DAS1800_ID_AO, + .ai_speed = 6250, + }, + [BOARD_DAS1801ST] = { + .name = "das-1801st", + .id = DAS1800_ID_ST, + .ai_speed = 3000, + .is_01_series = 1, + }, + [BOARD_DAS1801ST_DA] = { + .name = "das-1801st-da", + .id = DAS1800_ID_ST_DA, + .ai_speed = 3000, + .is_01_series = 1, + }, + [BOARD_DAS1802ST] = { + .name = "das-1802st", + .id = DAS1800_ID_ST, + .ai_speed = 3000, + }, + [BOARD_DAS1802ST_DA] = { + .name = "das-1802st-da", + .id = DAS1800_ID_ST_DA, + .ai_speed = 3000, + }, + [BOARD_DAS1802HR] = { + .name = "das-1802hr", + .id = DAS1800_ID_HR, + .ai_speed = 10000, + }, + [BOARD_DAS1802HR_DA] = { + .name = "das-1802hr-da", + .id = DAS1800_ID_HR_DA, + .ai_speed = 10000, + }, + [BOARD_DAS1801HC] = { + .name = "das-1801hc", + .id = DAS1800_ID_HC, + .ai_speed = 3000, + .is_01_series = 1, + }, + [BOARD_DAS1802HC] = { + .name = "das-1802hc", + .id = DAS1800_ID_HC, + .ai_speed = 3000, + }, + [BOARD_DAS1801AO] = { + .name = "das-1801ao", + .id = DAS1800_ID_AO, + .ai_speed = 3000, + .is_01_series = 1, + }, + [BOARD_DAS1802AO] = { + .name = "das-1802ao", + .id = DAS1800_ID_AO, + .ai_speed = 3000, + }, }; struct das1800_private { struct comedi_isadma *dma; - int irq_dma_bits; /* bits for control register b */ - /* dma bits for control register b, stored so that dma can be - * turned on and off */ + int irq_dma_bits; int dma_bits; - uint16_t *fifo_buf; /* bounce buffer for analog input FIFO */ - unsigned long iobase2; /* secondary io address used for analog out on 'ao' boards */ - unsigned short ao_update_bits; /* remembers the last write to the - * 'update' dac */ -}; - -/* analog out range for 'ao' boards */ -/* -static const struct comedi_lrange range_ao_2 = { - 2, { - BIP_RANGE(10), - BIP_RANGE(5) - } + unsigned short *fifo_buf; + unsigned long iobase2; + bool ai_is_unipolar; }; -*/ - -static inline uint16_t munge_bipolar_sample(const struct comedi_device *dev, - uint16_t sample) -{ - const struct das1800_board *board = dev->board_ptr; - - sample += 1 << (board->resolution - 1); - return sample; -} -static void munge_data(struct comedi_device *dev, uint16_t *array, - unsigned int num_elements) +static void das1800_ai_munge(struct comedi_device *dev, + struct comedi_subdevice *s, + void *data, unsigned int num_bytes, + unsigned int start_chan_index) { + struct das1800_private *devpriv = dev->private; + unsigned short *array = data; + unsigned int num_samples = comedi_bytes_to_samples(s, num_bytes); unsigned int i; - int unipolar; - /* see if card is using a unipolar or bipolar range so we can munge data correctly */ - unipolar = inb(dev->iobase + DAS1800_CONTROL_C) & UB; + if (devpriv->ai_is_unipolar) + return; - /* convert to unsigned type if we are in a bipolar mode */ - if (!unipolar) { - for (i = 0; i < num_elements; i++) - array[i] = munge_bipolar_sample(dev, array[i]); - } + for (i = 0; i < num_samples; i++) + array[i] = comedi_offset_munge(s, array[i]); } static void das1800_handle_fifo_half_full(struct comedi_device *dev, @@ -473,7 +352,6 @@ static void das1800_handle_fifo_half_full(struct comedi_device *dev, unsigned int nsamples = comedi_nsamples_left(s, FIFO_SIZE / 2); insw(dev->iobase + DAS1800_FIFO, devpriv->fifo_buf, nsamples); - munge_data(dev, devpriv->fifo_buf, nsamples); comedi_buf_write_samples(s, devpriv->fifo_buf, nsamples); } @@ -482,14 +360,9 @@ static void das1800_handle_fifo_not_empty(struct comedi_device *dev, { struct comedi_cmd *cmd = &s->async->cmd; unsigned short dpnt; - int unipolar; - - unipolar = inb(dev->iobase + DAS1800_CONTROL_C) & UB; while (inb(dev->iobase + DAS1800_STATUS) & FNE) { dpnt = inw(dev->iobase + DAS1800_FIFO); - /* convert to unsigned type */ - dpnt = munge_bipolar_sample(dev, dpnt); comedi_buf_write_samples(s, &dpnt, 1); if (cmd->stop_src == TRIG_COUNT && @@ -498,7 +371,6 @@ static void das1800_handle_fifo_not_empty(struct comedi_device *dev, } } -/* Utility function used by das1800_flush_dma() and das1800_handle_dma() */ static void das1800_flush_dma_channel(struct comedi_device *dev, struct comedi_subdevice *s, struct comedi_isadma_desc *desc) @@ -511,12 +383,9 @@ static void das1800_flush_dma_channel(struct comedi_device *dev, nsamples = comedi_bytes_to_samples(s, nbytes); nsamples = comedi_nsamples_left(s, nsamples); - munge_data(dev, desc->virt_addr, nsamples); comedi_buf_write_samples(s, desc->virt_addr, nsamples); } -/* flushes remaining data from board when external trigger has stopped acquisition - * and we are using dma transfers */ static void das1800_flush_dma(struct comedi_device *dev, struct comedi_subdevice *s) { @@ -560,27 +429,30 @@ static void das1800_handle_dma(struct comedi_device *dev, } } -static int das1800_cancel(struct comedi_device *dev, struct comedi_subdevice *s) +static int das1800_ai_cancel(struct comedi_device *dev, + struct comedi_subdevice *s) { struct das1800_private *devpriv = dev->private; struct comedi_isadma *dma = devpriv->dma; struct comedi_isadma_desc *desc; int i; - outb(0x0, dev->iobase + DAS1800_STATUS); /* disable conversions */ - outb(0x0, dev->iobase + DAS1800_CONTROL_B); /* disable interrupts and dma */ - outb(0x0, dev->iobase + DAS1800_CONTROL_A); /* disable and clear fifo and stop triggering */ + /* disable and stop conversions */ + outb(0x0, dev->iobase + DAS1800_STATUS); + outb(0x0, dev->iobase + DAS1800_CONTROL_B); + outb(0x0, dev->iobase + DAS1800_CONTROL_A); - for (i = 0; i < 2; i++) { - desc = &dma->desc[i]; - if (desc->chan) - comedi_isadma_disable(desc->chan); + if (dma) { + for (i = 0; i < 2; i++) { + desc = &dma->desc[i]; + if (desc->chan) + comedi_isadma_disable(desc->chan); + } } return 0; } -/* the guts of the interrupt handler, that is shared with das1800_ai_poll */ static void das1800_ai_handler(struct comedi_device *dev) { struct das1800_private *devpriv = dev->private; @@ -589,17 +461,16 @@ static void das1800_ai_handler(struct comedi_device *dev) struct comedi_cmd *cmd = &async->cmd; unsigned int status = inb(dev->iobase + DAS1800_STATUS); - /* select adc for base address + 0 */ + /* select adc register (spinlock is already held) */ outb(ADC, dev->iobase + DAS1800_SELECT); - /* dma buffer full */ - if (devpriv->irq_dma_bits & DMA_ENABLED) { - /* look for data from dma transfer even if dma terminal count hasn't happened yet */ + + /* get samples with dma, fifo, or polled as necessary */ + if (devpriv->irq_dma_bits & DMA_ENABLED) das1800_handle_dma(dev, s, status); - } else if (status & FHF) { /* if fifo half full */ + else if (status & FHF) das1800_handle_fifo_half_full(dev, s); - } else if (status & FNE) { /* if fifo not empty */ + else if (status & FNE) das1800_handle_fifo_not_empty(dev, s); - } /* if the card's fifo has overflowed */ if (status & OVF) { @@ -615,7 +486,7 @@ static void das1800_ai_handler(struct comedi_device *dev) if (status & CT0TC) { /* clear CT0TC interrupt bit */ outb(CLEAR_INTR_MASK & ~CT0TC, dev->iobase + DAS1800_STATUS); - /* make sure we get all remaining data from board before quitting */ + /* get all remaining samples before quitting */ if (devpriv->irq_dma_bits & DMA_ENABLED) das1800_flush_dma(dev, s); else @@ -634,9 +505,14 @@ static int das1800_ai_poll(struct comedi_device *dev, { unsigned long flags; - /* prevent race with interrupt handler */ + /* + * Protects the indirect addressing selected by DAS1800_SELECT + * in das1800_ai_handler() also prevents race with das1800_interrupt(). + */ spin_lock_irqsave(&dev->spinlock, flags); + das1800_ai_handler(dev); + spin_unlock_irqrestore(&dev->spinlock, flags); return comedi_buf_n_bytes_ready(s); @@ -652,9 +528,12 @@ static irqreturn_t das1800_interrupt(int irq, void *d) return IRQ_HANDLED; } - /* Prevent race with das1800_ai_poll() on multi processor systems. - * Also protects indirect addressing in das1800_ai_handler */ + /* + * Protects the indirect addressing selected by DAS1800_SELECT + * in das1800_ai_handler() also prevents race with das1800_ai_poll(). + */ spin_lock(&dev->spinlock); + status = inb(dev->iobase + DAS1800_STATUS); /* if interrupt was not caused by das-1800 */ @@ -671,46 +550,87 @@ static irqreturn_t das1800_interrupt(int irq, void *d) return IRQ_HANDLED; } -/* converts requested conversion timing to timing compatible with - * hardware, used only when card is in 'burst mode' - */ -static unsigned int burst_convert_arg(unsigned int convert_arg, int flags) +static int das1800_ai_fixup_paced_timing(struct comedi_device *dev, + struct comedi_cmd *cmd) +{ + unsigned int arg = cmd->convert_arg; + + /* + * Paced mode: + * scan_begin_src is TRIG_FOLLOW + * convert_src is TRIG_TIMER + * + * The convert_arg sets the pacer sample acquisition time. + * The max acquisition speed is limited to the boards + * 'ai_speed' (this was already verified). The min speed is + * limited by the cascaded 8254 timer. + */ + comedi_8254_cascade_ns_to_timer(dev->pacer, &arg, cmd->flags); + return comedi_check_trigger_arg_is(&cmd->convert_arg, arg); +} + +static int das1800_ai_fixup_burst_timing(struct comedi_device *dev, + struct comedi_cmd *cmd) { - unsigned int micro_sec; + unsigned int arg = cmd->convert_arg; + int err = 0; - /* in burst mode, the maximum conversion time is 64 microseconds */ - if (convert_arg > 64000) - convert_arg = 64000; + /* + * Burst mode: + * scan_begin_src is TRIG_TIMER or TRIG_EXT + * convert_src is TRIG_TIMER + * + * The convert_arg sets burst sample acquisition time. + * The max acquisition speed is limited to the boards + * 'ai_speed' (this was already verified). The min speed is + * limiited to 64 microseconds, + */ + err |= comedi_check_trigger_arg_max(&arg, 64000); - /* the conversion time must be an integral number of microseconds */ - switch (flags & CMDF_ROUND_MASK) { + /* round to microseconds then verify */ + switch (cmd->flags & CMDF_ROUND_MASK) { case CMDF_ROUND_NEAREST: default: - micro_sec = (convert_arg + 500) / 1000; + arg = DIV_ROUND_CLOSEST(arg, 1000); break; case CMDF_ROUND_DOWN: - micro_sec = convert_arg / 1000; + arg = arg / 1000; break; case CMDF_ROUND_UP: - micro_sec = (convert_arg - 1) / 1000 + 1; + arg = DIV_ROUND_UP(arg, 1000); break; } + err |= comedi_check_trigger_arg_is(&cmd->convert_arg, arg * 1000); - /* return number of nanoseconds */ - return micro_sec * 1000; + /* + * The pacer can be used to set the scan sample rate. The max scan + * speed is limited by the conversion speed and the number of channels + * to convert. The min speed is limited by the cascaded 8254 timer. + */ + if (cmd->scan_begin_src == TRIG_TIMER) { + arg = cmd->convert_arg * cmd->chanlist_len; + err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg, arg); + + arg = cmd->scan_begin_arg; + comedi_8254_cascade_ns_to_timer(dev->pacer, &arg, cmd->flags); + err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, arg); + } + + return err; } static int das1800_ai_check_chanlist(struct comedi_device *dev, struct comedi_subdevice *s, struct comedi_cmd *cmd) { - unsigned int unipolar0 = CR_RANGE(cmd->chanlist[0]) & UNIPOLAR; + unsigned int range = CR_RANGE(cmd->chanlist[0]); + bool unipolar0 = comedi_range_is_unipolar(s, range); int i; for (i = 1; i < cmd->chanlist_len; i++) { - unsigned int unipolar = CR_RANGE(cmd->chanlist[i]) & UNIPOLAR; + range = CR_RANGE(cmd->chanlist[i]); - if (unipolar != unipolar0) { + if (unipolar0 != comedi_range_is_unipolar(s, range)) { dev_dbg(dev->class_dev, "unipolar and bipolar ranges cannot be mixed in the chanlist\n"); return -EINVAL; @@ -720,14 +640,12 @@ static int das1800_ai_check_chanlist(struct comedi_device *dev, return 0; } -/* test analog input cmd */ -static int das1800_ai_do_cmdtest(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_cmd *cmd) +static int das1800_ai_cmdtest(struct comedi_device *dev, + struct comedi_subdevice *s, + struct comedi_cmd *cmd) { const struct das1800_board *board = dev->board_ptr; int err = 0; - unsigned int arg; /* Step 1 : check if triggers are trivially valid */ @@ -752,16 +670,23 @@ static int das1800_ai_do_cmdtest(struct comedi_device *dev, /* Step 2b : and mutually compatible */ + /* burst scans must use timed conversions */ if (cmd->scan_begin_src != TRIG_FOLLOW && cmd->convert_src != TRIG_TIMER) err |= -EINVAL; + /* the external pin TGIN must use the same polarity */ + if (cmd->start_src == TRIG_EXT && cmd->stop_src == TRIG_EXT) + err |= comedi_check_trigger_arg_is(&cmd->start_arg, + cmd->stop_arg); + if (err) return 2; /* Step 3: check if arguments are trivially valid */ - err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0); + if (cmd->start_arg == TRIG_NOW) + err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0); if (cmd->convert_src == TRIG_TIMER) { err |= comedi_check_trigger_arg_min(&cmd->convert_arg, @@ -786,31 +711,13 @@ static int das1800_ai_do_cmdtest(struct comedi_device *dev, if (err) return 3; - /* step 4: fix up any arguments */ + /* Step 4: fix up any arguments */ - if (cmd->scan_begin_src == TRIG_FOLLOW && - cmd->convert_src == TRIG_TIMER) { - /* we are not in burst mode */ - arg = cmd->convert_arg; - comedi_8254_cascade_ns_to_timer(dev->pacer, &arg, cmd->flags); - err |= comedi_check_trigger_arg_is(&cmd->convert_arg, arg); - } else if (cmd->convert_src == TRIG_TIMER) { - /* we are in burst mode */ - arg = burst_convert_arg(cmd->convert_arg, cmd->flags); - err |= comedi_check_trigger_arg_is(&cmd->convert_arg, arg); - - if (cmd->scan_begin_src == TRIG_TIMER) { - arg = cmd->convert_arg * cmd->chanlist_len; - err |= comedi_check_trigger_arg_max(&cmd-> - scan_begin_arg, - arg); - - arg = cmd->scan_begin_arg; - comedi_8254_cascade_ns_to_timer(dev->pacer, &arg, - cmd->flags); - err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, - arg); - } + if (cmd->convert_src == TRIG_TIMER) { + if (cmd->scan_begin_src == TRIG_FOLLOW) + err |= das1800_ai_fixup_paced_timing(dev, cmd); + else /* TRIG_TIMER or TRIG_EXT */ + err |= das1800_ai_fixup_burst_timing(dev, cmd); } if (err) @@ -826,74 +733,22 @@ static int das1800_ai_do_cmdtest(struct comedi_device *dev, return 0; } -/* returns appropriate bits for control register a, depending on command */ -static int control_a_bits(const struct comedi_cmd *cmd) -{ - int control_a; - - control_a = FFEN; /* enable fifo */ - if (cmd->stop_src == TRIG_EXT) - control_a |= ATEN; - switch (cmd->start_src) { - case TRIG_EXT: - control_a |= TGEN | CGSL; - break; - case TRIG_NOW: - control_a |= CGEN; - break; - default: - break; - } - - return control_a; -} - -/* returns appropriate bits for control register c, depending on command */ -static int control_c_bits(const struct comedi_cmd *cmd) +static unsigned char das1800_ai_chanspec_bits(struct comedi_subdevice *s, + unsigned int chanspec) { - int control_c; - int aref; + unsigned int range = CR_RANGE(chanspec); + unsigned int aref = CR_AREF(chanspec); + unsigned char bits; - /* set clock source to internal or external, select analog reference, - * select unipolar / bipolar - */ - aref = CR_AREF(cmd->chanlist[0]); - control_c = UQEN; /* enable upper qram addresses */ + bits = UQEN; if (aref != AREF_DIFF) - control_c |= SD; + bits |= SD; if (aref == AREF_COMMON) - control_c |= CMEN; - /* if a unipolar range was selected */ - if (CR_RANGE(cmd->chanlist[0]) & UNIPOLAR) - control_c |= UB; - switch (cmd->scan_begin_src) { - case TRIG_FOLLOW: /* not in burst mode */ - switch (cmd->convert_src) { - case TRIG_TIMER: - /* trig on cascaded counters */ - control_c |= IPCLK; - break; - case TRIG_EXT: - /* trig on falling edge of external trigger */ - control_c |= XPCLK; - break; - default: - break; - } - break; - case TRIG_TIMER: - /* burst mode with internal pacer clock */ - control_c |= BMDE | IPCLK; - break; - case TRIG_EXT: - /* burst mode with external trigger */ - control_c |= BMDE | XPCLK; - break; - default: - break; - } + bits |= CMEN; + if (comedi_range_is_unipolar(s, range)) + bits |= UB; - return control_c; + return bits; } static unsigned int das1800_ai_transfer_size(struct comedi_device *dev, @@ -934,13 +789,14 @@ static void das1800_ai_setup_dma(struct comedi_device *dev, { struct das1800_private *devpriv = dev->private; struct comedi_isadma *dma = devpriv->dma; - struct comedi_isadma_desc *desc = &dma->desc[0]; + struct comedi_isadma_desc *desc; unsigned int bytes; if ((devpriv->irq_dma_bits & DMA_ENABLED) == 0) return; dma->cur_dma = 0; + desc = &dma->desc[0]; /* determine a dma transfer size to fill buffer in 0.3 sec */ bytes = das1800_ai_transfer_size(dev, s, desc->maxsize, 300000000); @@ -956,43 +812,48 @@ static void das1800_ai_setup_dma(struct comedi_device *dev, } } -/* programs channel/gain list into card */ -static void program_chanlist(struct comedi_device *dev, - const struct comedi_cmd *cmd) +static void das1800_ai_set_chanlist(struct comedi_device *dev, + unsigned int *chanlist, unsigned int len) { - int i, n, chan_range; - unsigned long irq_flags; - const int range_mask = 0x3; /* masks unipolar/bipolar bit off range */ - const int range_bitshift = 8; - - n = cmd->chanlist_len; - /* spinlock protects indirect addressing */ - spin_lock_irqsave(&dev->spinlock, irq_flags); - outb(QRAM, dev->iobase + DAS1800_SELECT); /* select QRAM for baseAddress + 0x0 */ - outb(n - 1, dev->iobase + DAS1800_QRAM_ADDRESS); /*set QRAM address start */ + unsigned long flags; + unsigned int i; + + /* protects the indirect addressing selected by DAS1800_SELECT */ + spin_lock_irqsave(&dev->spinlock, flags); + + /* select QRAM register and set start address */ + outb(QRAM, dev->iobase + DAS1800_SELECT); + outb(len - 1, dev->iobase + DAS1800_QRAM_ADDRESS); + /* make channel / gain list */ - for (i = 0; i < n; i++) { - chan_range = - CR_CHAN(cmd->chanlist[i]) | - ((CR_RANGE(cmd->chanlist[i]) & range_mask) << - range_bitshift); - outw(chan_range, dev->iobase + DAS1800_QRAM); + for (i = 0; i < len; i++) { + unsigned int chan = CR_CHAN(chanlist[i]); + unsigned int range = CR_RANGE(chanlist[i]); + unsigned short val; + + val = chan | ((range & 0x3) << 8); + outw(val, dev->iobase + DAS1800_QRAM); } - outb(n - 1, dev->iobase + DAS1800_QRAM_ADDRESS); /*finish write to QRAM */ - spin_unlock_irqrestore(&dev->spinlock, irq_flags); + + /* finish write to QRAM */ + outb(len - 1, dev->iobase + DAS1800_QRAM_ADDRESS); + + spin_unlock_irqrestore(&dev->spinlock, flags); } -/* analog input do_cmd */ -static int das1800_ai_do_cmd(struct comedi_device *dev, - struct comedi_subdevice *s) +static int das1800_ai_cmd(struct comedi_device *dev, + struct comedi_subdevice *s) { struct das1800_private *devpriv = dev->private; int control_a, control_c; struct comedi_async *async = s->async; const struct comedi_cmd *cmd = &async->cmd; + unsigned int range0 = CR_RANGE(cmd->chanlist[0]); - /* disable dma on CMDF_WAKE_EOS, or CMDF_PRIORITY - * (because dma in handler is unsafe at hard real-time priority) */ + /* + * Disable dma on CMDF_WAKE_EOS, or CMDF_PRIORITY (because dma in + * handler is unsafe at hard real-time priority). + */ if (cmd->flags & (CMDF_WAKE_EOS | CMDF_PRIORITY)) devpriv->irq_dma_bits &= ~DMA_ENABLED; else @@ -1006,14 +867,42 @@ static int das1800_ai_do_cmd(struct comedi_device *dev, devpriv->irq_dma_bits |= FIMD; } - das1800_cancel(dev, s); + das1800_ai_cancel(dev, s); + + devpriv->ai_is_unipolar = comedi_range_is_unipolar(s, range0); - /* determine proper bits for control registers */ - control_a = control_a_bits(cmd); - control_c = control_c_bits(cmd); + control_a = FFEN; + if (cmd->stop_src == TRIG_EXT) + control_a |= ATEN; + if (cmd->start_src == TRIG_EXT) + control_a |= TGEN | CGSL; + else /* TRIG_NOW */ + control_a |= CGEN; + if (control_a & (ATEN | TGEN)) { + if ((cmd->start_arg & CR_INVERT) || (cmd->stop_arg & CR_INVERT)) + control_a |= TGPL; + } + + control_c = das1800_ai_chanspec_bits(s, cmd->chanlist[0]); + /* set clock source to internal or external */ + if (cmd->scan_begin_src == TRIG_FOLLOW) { + /* not in burst mode */ + if (cmd->convert_src == TRIG_TIMER) { + /* trig on cascaded counters */ + control_c |= IPCLK; + } else { /* TRIG_EXT */ + /* trig on falling edge of external trigger */ + control_c |= XPCLK; + } + } else if (cmd->scan_begin_src == TRIG_TIMER) { + /* burst mode with internal pacer clock */ + control_c |= BMDE | IPCLK; + } else { /* TRIG_EXT */ + /* burst mode with external trigger */ + control_c |= BMDE | XPCLK; + } - /* setup card and start */ - program_chanlist(dev, cmd); + das1800_ai_set_chanlist(dev, cmd->chanlist, cmd->chanlist_len); /* setup cascaded counters for conversion/scan frequency */ if ((cmd->scan_begin_src == TRIG_FOLLOW || @@ -1031,118 +920,117 @@ static int das1800_ai_do_cmd(struct comedi_device *dev, outb(control_c, dev->iobase + DAS1800_CONTROL_C); /* set conversion rate and length for burst mode */ if (control_c & BMDE) { - /* program conversion period with number of microseconds minus 1 */ - outb(cmd->convert_arg / 1000 - 1, + outb(cmd->convert_arg / 1000 - 1, /* microseconds - 1 */ dev->iobase + DAS1800_BURST_RATE); outb(cmd->chanlist_len - 1, dev->iobase + DAS1800_BURST_LENGTH); } - outb(devpriv->irq_dma_bits, dev->iobase + DAS1800_CONTROL_B); /* enable irq/dma */ - outb(control_a, dev->iobase + DAS1800_CONTROL_A); /* enable fifo and triggering */ - outb(CVEN, dev->iobase + DAS1800_STATUS); /* enable conversions */ + + /* enable and start conversions */ + outb(devpriv->irq_dma_bits, dev->iobase + DAS1800_CONTROL_B); + outb(control_a, dev->iobase + DAS1800_CONTROL_A); + outb(CVEN, dev->iobase + DAS1800_STATUS); return 0; } -/* read analog input */ -static int das1800_ai_rinsn(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, unsigned int *data) +static int das1800_ai_eoc(struct comedi_device *dev, + struct comedi_subdevice *s, + struct comedi_insn *insn, + unsigned long context) { - const struct das1800_board *board = dev->board_ptr; - int i, n; - int chan, range, aref, chan_range; - int timeout = 1000; - unsigned short dpnt; - int conv_flags = 0; - unsigned long irq_flags; + unsigned char status; - /* set up analog reference and unipolar / bipolar mode */ - aref = CR_AREF(insn->chanspec); - conv_flags |= UQEN; - if (aref != AREF_DIFF) - conv_flags |= SD; - if (aref == AREF_COMMON) - conv_flags |= CMEN; - /* if a unipolar range was selected */ - if (CR_RANGE(insn->chanspec) & UNIPOLAR) - conv_flags |= UB; + status = inb(dev->iobase + DAS1800_STATUS); + if (status & FNE) + return 0; + return -EBUSY; +} + +static int das1800_ai_insn_read(struct comedi_device *dev, + struct comedi_subdevice *s, + struct comedi_insn *insn, + unsigned int *data) +{ + unsigned int range = CR_RANGE(insn->chanspec); + bool is_unipolar = comedi_range_is_unipolar(s, range); + int ret = 0; + int n; + unsigned short dpnt; + unsigned long flags; - outb(conv_flags, dev->iobase + DAS1800_CONTROL_C); /* software conversion enabled */ + outb(das1800_ai_chanspec_bits(s, insn->chanspec), + dev->iobase + DAS1800_CONTROL_C); /* software pacer */ outb(CVEN, dev->iobase + DAS1800_STATUS); /* enable conversions */ outb(0x0, dev->iobase + DAS1800_CONTROL_A); /* reset fifo */ outb(FFEN, dev->iobase + DAS1800_CONTROL_A); - chan = CR_CHAN(insn->chanspec); - /* mask of unipolar/bipolar bit from range */ - range = CR_RANGE(insn->chanspec) & 0x3; - chan_range = chan | (range << 8); - spin_lock_irqsave(&dev->spinlock, irq_flags); - outb(QRAM, dev->iobase + DAS1800_SELECT); /* select QRAM for baseAddress + 0x0 */ - outb(0x0, dev->iobase + DAS1800_QRAM_ADDRESS); /* set QRAM address start */ - outw(chan_range, dev->iobase + DAS1800_QRAM); - outb(0x0, dev->iobase + DAS1800_QRAM_ADDRESS); /*finish write to QRAM */ - outb(ADC, dev->iobase + DAS1800_SELECT); /* select ADC for baseAddress + 0x0 */ + das1800_ai_set_chanlist(dev, &insn->chanspec, 1); + + /* protects the indirect addressing selected by DAS1800_SELECT */ + spin_lock_irqsave(&dev->spinlock, flags); + + /* select ai fifo register */ + outb(ADC, dev->iobase + DAS1800_SELECT); for (n = 0; n < insn->n; n++) { /* trigger conversion */ outb(0, dev->iobase + DAS1800_FIFO); - for (i = 0; i < timeout; i++) { - if (inb(dev->iobase + DAS1800_STATUS) & FNE) - break; - } - if (i == timeout) { - dev_err(dev->class_dev, "timeout\n"); - n = -ETIME; - goto exit; - } + + ret = comedi_timeout(dev, s, insn, das1800_ai_eoc, 0); + if (ret) + break; + dpnt = inw(dev->iobase + DAS1800_FIFO); - /* shift data to offset binary for bipolar ranges */ - if ((conv_flags & UB) == 0) - dpnt += 1 << (board->resolution - 1); + if (!is_unipolar) + dpnt = comedi_offset_munge(s, dpnt); data[n] = dpnt; } -exit: - spin_unlock_irqrestore(&dev->spinlock, irq_flags); + spin_unlock_irqrestore(&dev->spinlock, flags); - return n; + return ret ? ret : insn->n; } -/* writes to an analog output channel */ -static int das1800_ao_winsn(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, unsigned int *data) +static int das1800_ao_insn_write(struct comedi_device *dev, + struct comedi_subdevice *s, + struct comedi_insn *insn, + unsigned int *data) { - const struct das1800_board *board = dev->board_ptr; - struct das1800_private *devpriv = dev->private; - int chan = CR_CHAN(insn->chanspec); -/* int range = CR_RANGE(insn->chanspec); */ - int update_chan = board->ao_n_chan - 1; - unsigned short output; - unsigned long irq_flags; - - /* card expects two's complement data */ - output = data[0] - (1 << (board->resolution - 1)); - /* if the write is to the 'update' channel, we need to remember its value */ - if (chan == update_chan) - devpriv->ao_update_bits = output; - /* write to channel */ - spin_lock_irqsave(&dev->spinlock, irq_flags); - outb(DAC(chan), dev->iobase + DAS1800_SELECT); /* select dac channel for baseAddress + 0x0 */ - outw(output, dev->iobase + DAS1800_DAC); - /* now we need to write to 'update' channel to update all dac channels */ - if (chan != update_chan) { - outb(DAC(update_chan), dev->iobase + DAS1800_SELECT); /* select 'update' channel for baseAddress + 0x0 */ - outw(devpriv->ao_update_bits, dev->iobase + DAS1800_DAC); + unsigned int chan = CR_CHAN(insn->chanspec); + unsigned int update_chan = s->n_chan - 1; + unsigned long flags; + int i; + + /* protects the indirect addressing selected by DAS1800_SELECT */ + spin_lock_irqsave(&dev->spinlock, flags); + + for (i = 0; i < insn->n; i++) { + unsigned int val = data[i]; + + s->readback[chan] = val; + + val = comedi_offset_munge(s, val); + + /* load this channel (and update if it's the last channel) */ + outb(DAC(chan), dev->iobase + DAS1800_SELECT); + outw(val, dev->iobase + DAS1800_DAC); + + /* update all channels */ + if (chan != update_chan) { + val = comedi_offset_munge(s, s->readback[update_chan]); + + outb(DAC(update_chan), dev->iobase + DAS1800_SELECT); + outw(val, dev->iobase + DAS1800_DAC); + } } - spin_unlock_irqrestore(&dev->spinlock, irq_flags); + spin_unlock_irqrestore(&dev->spinlock, flags); - return 1; + return insn->n; } -/* reads from digital input channels */ -static int das1800_di_rbits(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, unsigned int *data) +static int das1800_di_insn_bits(struct comedi_device *dev, + struct comedi_subdevice *s, + struct comedi_insn *insn, + unsigned int *data) { data[1] = inb(dev->iobase + DAS1800_DIGITAL) & 0xf; data[0] = 0; @@ -1150,10 +1038,10 @@ static int das1800_di_rbits(struct comedi_device *dev, return insn->n; } -static int das1800_do_wbits(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, - unsigned int *data) +static int das1800_do_insn_bits(struct comedi_device *dev, + struct comedi_subdevice *s, + struct comedi_insn *insn, + unsigned int *data) { if (comedi_dio_update_state(s, data)) outb(s->state, dev->iobase + DAS1800_DIGITAL); @@ -1216,68 +1104,68 @@ static void das1800_free_dma(struct comedi_device *dev) comedi_isadma_free(devpriv->dma); } -static const struct das1800_board *das1800_probe(struct comedi_device *dev) +static int das1800_probe(struct comedi_device *dev) { const struct das1800_board *board = dev->board_ptr; - int index = board ? board - das1800_boards : -EINVAL; - int id; + unsigned char id; + + id = (inb(dev->iobase + DAS1800_DIGITAL) >> 4) & 0xf; /* * The dev->board_ptr will be set by comedi_device_attach() if the * board name provided by the user matches a board->name in this * driver. If so, this function sanity checks the id to verify that * the board is correct. - * - * If the dev->board_ptr is not set, the user is trying to attach - * an unspecified board to this driver. In this case the id is used - * to 'probe' for the correct dev->board_ptr. */ - id = (inb(dev->iobase + DAS1800_DIGITAL) >> 4) & 0xf; + if (board) { + if (board->id == id) + return 0; + dev_err(dev->class_dev, + "probed id does not match board id (0x%x != 0x%x)\n", + id, board->id); + return -ENODEV; + } + + /* + * If the dev->board_ptr is not set, the user is trying to attach + * an unspecified board to this driver. In this case the id is used + * to 'probe' for the dev->board_ptr. + */ switch (id) { - case 0x3: - if (index == das1801st_da || index == das1802st_da || - index == das1701st_da || index == das1702st_da) - return board; - index = das1801st; + case DAS1800_ID_ST_DA: + /* das-1701st-da, das-1702st-da, das-1801st-da, das-1802st-da */ + board = &das1800_boards[BOARD_DAS1801ST_DA]; break; - case 0x4: - if (index == das1802hr_da || index == das1702hr_da) - return board; - index = das1802hr; + case DAS1800_ID_HR_DA: + /* das-1702hr-da, das-1802hr-da */ + board = &das1800_boards[BOARD_DAS1802HR_DA]; break; - case 0x5: - if (index == das1801ao || index == das1802ao || - index == das1701ao || index == das1702ao) - return board; - index = das1801ao; + case DAS1800_ID_AO: + /* das-1701ao, das-1702ao, das-1801ao, das-1802ao */ + board = &das1800_boards[BOARD_DAS1801AO]; break; - case 0x6: - if (index == das1802hr || index == das1702hr) - return board; - index = das1802hr; + case DAS1800_ID_HR: + /* das-1702hr, das-1802hr */ + board = &das1800_boards[BOARD_DAS1802HR]; break; - case 0x7: - if (index == das1801st || index == das1802st || - index == das1701st || index == das1702st) - return board; - index = das1801st; + case DAS1800_ID_ST: + /* das-1701st, das-1702st, das-1801st, das-1802st */ + board = &das1800_boards[BOARD_DAS1801ST]; break; - case 0x8: - if (index == das1801hc || index == das1802hc) - return board; - index = das1801hc; + case DAS1800_ID_HC: + /* das-1801hc, das-1802hc */ + board = &das1800_boards[BOARD_DAS1801HC]; break; default: - dev_err(dev->class_dev, - "Board model: probe returned 0x%x (unknown, please report)\n", - id); - return NULL; + dev_err(dev->class_dev, "invalid probe id 0x%x\n", id); + return -ENODEV; } - dev_err(dev->class_dev, - "Board model (probed, not recommended): %s series\n", - das1800_boards[index].name); - - return &das1800_boards[index]; + dev->board_ptr = board; + dev->board_name = board->name; + dev_warn(dev->class_dev, + "probed id 0x%0x: %s series (not recommended)\n", + id, board->name); + return 0; } static int das1800_attach(struct comedi_device *dev, @@ -1287,7 +1175,9 @@ static int das1800_attach(struct comedi_device *dev, struct das1800_private *devpriv; struct comedi_subdevice *s; unsigned int irq = it->options[1]; + bool is_16bit; int ret; + int i; devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv)); if (!devpriv) @@ -1297,16 +1187,15 @@ static int das1800_attach(struct comedi_device *dev, if (ret) return ret; - board = das1800_probe(dev); - if (!board) { - dev_err(dev->class_dev, "unable to determine board type\n"); - return -ENODEV; - } - dev->board_ptr = board; - dev->board_name = board->name; + ret = das1800_probe(dev); + if (ret) + return ret; + board = dev->board_ptr; - /* if it is an 'ao' board with fancy analog out then we need extra io ports */ - if (board->ao_ability == 2) { + is_16bit = board->id == DAS1800_ID_HR || board->id == DAS1800_ID_HR_DA; + + /* waveform 'ao' boards have additional io ports */ + if (board->id == DAS1800_ID_AO) { unsigned long iobase2 = dev->iobase + IOBASE2; ret = __comedi_request_region(dev, iobase2, DAS1800_SIZE); @@ -1349,7 +1238,9 @@ static int das1800_attach(struct comedi_device *dev, if (dev->irq & it->options[2]) das1800_init_dma(dev, it); - devpriv->fifo_buf = kmalloc_array(FIFO_SIZE, sizeof(uint16_t), GFP_KERNEL); + devpriv->fifo_buf = kmalloc_array(FIFO_SIZE, + sizeof(*devpriv->fifo_buf), + GFP_KERNEL); if (!devpriv->fifo_buf) return -ENOMEM; @@ -1362,70 +1253,94 @@ static int das1800_attach(struct comedi_device *dev, if (ret) return ret; - /* analog input subdevice */ + /* + * Analog Input subdevice + * + * The "hc" type boards have 64 analog input channels and a 64 + * entry QRAM fifo. + * + * All the other board types have 16 on-board channels. Each channel + * can be expanded to 16 channels with the addition of an EXP-1800 + * expansion board for a total of 256 channels. The QRAM fifo on + * these boards has 256 entries. + * + * From the datasheets it's not clear what the comedi channel to + * actual physical channel mapping is when EXP-1800 boards are used. + */ s = &dev->subdevices[0]; - s->type = COMEDI_SUBD_AI; - s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_GROUND; - if (board->common) - s->subdev_flags |= SDF_COMMON; - s->n_chan = board->qram_len; - s->maxdata = (1 << board->resolution) - 1; - s->range_table = board->range_ai; - s->insn_read = das1800_ai_rinsn; + s->type = COMEDI_SUBD_AI; + s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_GROUND; + if (board->id != DAS1800_ID_HC) + s->subdev_flags |= SDF_COMMON; + s->n_chan = (board->id == DAS1800_ID_HC) ? 64 : 256; + s->maxdata = is_16bit ? 0xffff : 0x0fff; + s->range_table = board->is_01_series ? &das1801_ai_range + : &das1802_ai_range; + s->insn_read = das1800_ai_insn_read; if (dev->irq) { dev->read_subdev = s; - s->subdev_flags |= SDF_CMD_READ; - s->len_chanlist = s->n_chan; - s->do_cmd = das1800_ai_do_cmd; - s->do_cmdtest = das1800_ai_do_cmdtest; - s->poll = das1800_ai_poll; - s->cancel = das1800_cancel; + s->subdev_flags |= SDF_CMD_READ; + s->len_chanlist = s->n_chan; + s->do_cmd = das1800_ai_cmd; + s->do_cmdtest = das1800_ai_cmdtest; + s->poll = das1800_ai_poll; + s->cancel = das1800_ai_cancel; + s->munge = das1800_ai_munge; } - /* analog out */ + /* Analog Output subdevice */ s = &dev->subdevices[1]; - if (board->ao_ability == 1) { - s->type = COMEDI_SUBD_AO; - s->subdev_flags = SDF_WRITABLE; - s->n_chan = board->ao_n_chan; - s->maxdata = (1 << board->resolution) - 1; - s->range_table = &range_bipolar10; - s->insn_write = das1800_ao_winsn; + if (board->id == DAS1800_ID_ST_DA || board->id == DAS1800_ID_HR_DA) { + s->type = COMEDI_SUBD_AO; + s->subdev_flags = SDF_WRITABLE; + s->n_chan = (board->id == DAS1800_ID_ST_DA) ? 4 : 2; + s->maxdata = is_16bit ? 0xffff : 0x0fff; + s->range_table = &range_bipolar10; + s->insn_write = das1800_ao_insn_write; + + ret = comedi_alloc_subdev_readback(s); + if (ret) + return ret; + + /* initialize all channels to 0V */ + for (i = 0; i < s->n_chan; i++) { + /* spinlock is not necessary during the attach */ + outb(DAC(i), dev->iobase + DAS1800_SELECT); + outw(0, dev->iobase + DAS1800_DAC); + } + } else if (board->id == DAS1800_ID_AO) { + /* + * 'ao' boards have waveform analog outputs that are not + * currently supported. + */ + s->type = COMEDI_SUBD_UNUSED; } else { - s->type = COMEDI_SUBD_UNUSED; + s->type = COMEDI_SUBD_UNUSED; } - /* di */ + /* Digital Input subdevice */ s = &dev->subdevices[2]; - s->type = COMEDI_SUBD_DI; - s->subdev_flags = SDF_READABLE; - s->n_chan = 4; - s->maxdata = 1; - s->range_table = &range_digital; - s->insn_bits = das1800_di_rbits; - - /* do */ + s->type = COMEDI_SUBD_DI; + s->subdev_flags = SDF_READABLE; + s->n_chan = 4; + s->maxdata = 1; + s->range_table = &range_digital; + s->insn_bits = das1800_di_insn_bits; + + /* Digital Output subdevice */ s = &dev->subdevices[3]; - s->type = COMEDI_SUBD_DO; - s->subdev_flags = SDF_WRITABLE; - s->n_chan = board->do_n_chan; - s->maxdata = 1; - s->range_table = &range_digital; - s->insn_bits = das1800_do_wbits; + s->type = COMEDI_SUBD_DO; + s->subdev_flags = SDF_WRITABLE; + s->n_chan = (board->id == DAS1800_ID_HC) ? 8 : 4; + s->maxdata = 1; + s->range_table = &range_digital; + s->insn_bits = das1800_do_insn_bits; - das1800_cancel(dev, dev->read_subdev); + das1800_ai_cancel(dev, dev->read_subdev); /* initialize digital out channels */ outb(0, dev->iobase + DAS1800_DIGITAL); - /* initialize analog out channels */ - if (board->ao_ability == 1) { - /* select 'update' dac channel for baseAddress + 0x0 */ - outb(DAC(board->ao_n_chan - 1), - dev->iobase + DAS1800_SELECT); - outw(devpriv->ao_update_bits, dev->iobase + DAS1800_DAC); - } - return 0; }; @@ -1454,5 +1369,5 @@ static struct comedi_driver das1800_driver = { module_comedi_driver(das1800_driver); MODULE_AUTHOR("Comedi http://www.comedi.org"); -MODULE_DESCRIPTION("Comedi low-level driver"); +MODULE_DESCRIPTION("Comedi driver for DAS1800 compatible ISA boards"); MODULE_LICENSE("GPL"); diff --git a/drivers/staging/comedi/drivers/dt282x.c b/drivers/staging/comedi/drivers/dt282x.c index 40bf00984fa5..d5295bbdd28c 100644 --- a/drivers/staging/comedi/drivers/dt282x.c +++ b/drivers/staging/comedi/drivers/dt282x.c @@ -69,49 +69,61 @@ * Register map */ #define DT2821_ADCSR_REG 0x00 -#define DT2821_ADCSR_ADERR (1 << 15) -#define DT2821_ADCSR_ADCLK (1 << 9) -#define DT2821_ADCSR_MUXBUSY (1 << 8) -#define DT2821_ADCSR_ADDONE (1 << 7) -#define DT2821_ADCSR_IADDONE (1 << 6) +#define DT2821_ADCSR_ADERR BIT(15) +#define DT2821_ADCSR_ADCLK BIT(9) +#define DT2821_ADCSR_MUXBUSY BIT(8) +#define DT2821_ADCSR_ADDONE BIT(7) +#define DT2821_ADCSR_IADDONE BIT(6) #define DT2821_ADCSR_GS(x) (((x) & 0x3) << 4) #define DT2821_ADCSR_CHAN(x) (((x) & 0xf) << 0) #define DT2821_CHANCSR_REG 0x02 -#define DT2821_CHANCSR_LLE (1 << 15) -#define DT2821_CHANCSR_PRESLA(x) (((x) & 0xf) >> 8) +#define DT2821_CHANCSR_LLE BIT(15) +#define DT2821_CHANCSR_TO_PRESLA(x) (((x) >> 8) & 0xf) #define DT2821_CHANCSR_NUMB(x) ((((x) - 1) & 0xf) << 0) #define DT2821_ADDAT_REG 0x04 #define DT2821_DACSR_REG 0x06 -#define DT2821_DACSR_DAERR (1 << 15) +#define DT2821_DACSR_DAERR BIT(15) #define DT2821_DACSR_YSEL(x) ((x) << 9) -#define DT2821_DACSR_SSEL (1 << 8) -#define DT2821_DACSR_DACRDY (1 << 7) -#define DT2821_DACSR_IDARDY (1 << 6) -#define DT2821_DACSR_DACLK (1 << 5) -#define DT2821_DACSR_HBOE (1 << 1) -#define DT2821_DACSR_LBOE (1 << 0) +#define DT2821_DACSR_SSEL BIT(8) +#define DT2821_DACSR_DACRDY BIT(7) +#define DT2821_DACSR_IDARDY BIT(6) +#define DT2821_DACSR_DACLK BIT(5) +#define DT2821_DACSR_HBOE BIT(1) +#define DT2821_DACSR_LBOE BIT(0) #define DT2821_DADAT_REG 0x08 #define DT2821_DIODAT_REG 0x0a #define DT2821_SUPCSR_REG 0x0c -#define DT2821_SUPCSR_DMAD (1 << 15) -#define DT2821_SUPCSR_ERRINTEN (1 << 14) -#define DT2821_SUPCSR_CLRDMADNE (1 << 13) -#define DT2821_SUPCSR_DDMA (1 << 12) -#define DT2821_SUPCSR_DS_PIO (0 << 10) -#define DT2821_SUPCSR_DS_AD_CLK (1 << 10) -#define DT2821_SUPCSR_DS_DA_CLK (2 << 10) -#define DT2821_SUPCSR_DS_AD_TRIG (3 << 10) -#define DT2821_SUPCSR_BUFFB (1 << 9) -#define DT2821_SUPCSR_SCDN (1 << 8) -#define DT2821_SUPCSR_DACON (1 << 7) -#define DT2821_SUPCSR_ADCINIT (1 << 6) -#define DT2821_SUPCSR_DACINIT (1 << 5) -#define DT2821_SUPCSR_PRLD (1 << 4) -#define DT2821_SUPCSR_STRIG (1 << 3) -#define DT2821_SUPCSR_XTRIG (1 << 2) -#define DT2821_SUPCSR_XCLK (1 << 1) -#define DT2821_SUPCSR_BDINIT (1 << 0) +#define DT2821_SUPCSR_DMAD BIT(15) +#define DT2821_SUPCSR_ERRINTEN BIT(14) +#define DT2821_SUPCSR_CLRDMADNE BIT(13) +#define DT2821_SUPCSR_DDMA BIT(12) +#define DT2821_SUPCSR_DS(x) (((x) & 0x3) << 10) +#define DT2821_SUPCSR_DS_PIO DT2821_SUPCSR_DS(0) +#define DT2821_SUPCSR_DS_AD_CLK DT2821_SUPCSR_DS(1) +#define DT2821_SUPCSR_DS_DA_CLK DT2821_SUPCSR_DS(2) +#define DT2821_SUPCSR_DS_AD_TRIG DT2821_SUPCSR_DS(3) +#define DT2821_SUPCSR_BUFFB BIT(9) +#define DT2821_SUPCSR_SCDN BIT(8) +#define DT2821_SUPCSR_DACON BIT(7) +#define DT2821_SUPCSR_ADCINIT BIT(6) +#define DT2821_SUPCSR_DACINIT BIT(5) +#define DT2821_SUPCSR_PRLD BIT(4) +#define DT2821_SUPCSR_STRIG BIT(3) +#define DT2821_SUPCSR_XTRIG BIT(2) +#define DT2821_SUPCSR_XCLK BIT(1) +#define DT2821_SUPCSR_BDINIT BIT(0) #define DT2821_TMRCTR_REG 0x0e +#define DT2821_TMRCTR_PRESCALE(x) (((x) & 0xf) << 8) +#define DT2821_TMRCTR_DIVIDER(x) ((255 - ((x) & 0xff)) << 0) + +/* Pacer Clock */ +#define DT2821_OSC_BASE 250 /* 4 MHz (in nanoseconds) */ +#define DT2821_PRESCALE(x) BIT(x) +#define DT2821_PRESCALE_MAX 15 +#define DT2821_DIVIDER_MAX 255 +#define DT2821_OSC_MAX (DT2821_OSC_BASE * \ + DT2821_PRESCALE(DT2821_PRESCALE_MAX) * \ + DT2821_DIVIDER_MAX) static const struct comedi_lrange range_dt282x_ai_lo_bipolar = { 4, { @@ -364,10 +376,10 @@ static unsigned int dt282x_ns_to_timer(unsigned int *ns, unsigned int flags) { unsigned int prescale, base, divider; - for (prescale = 0; prescale < 16; prescale++) { - if (prescale == 1) + for (prescale = 0; prescale <= DT2821_PRESCALE_MAX; prescale++) { + if (prescale == 1) /* 0 and 1 are both divide by 1 */ continue; - base = 250 * (1 << prescale); + base = DT2821_OSC_BASE * DT2821_PRESCALE(prescale); switch (flags & CMDF_ROUND_MASK) { case CMDF_ROUND_NEAREST: default: @@ -380,15 +392,17 @@ static unsigned int dt282x_ns_to_timer(unsigned int *ns, unsigned int flags) divider = DIV_ROUND_UP(*ns, base); break; } - if (divider < 256) { - *ns = divider * base; - return (prescale << 8) | (255 - divider); - } + if (divider <= DT2821_DIVIDER_MAX) + break; + } + if (divider > DT2821_DIVIDER_MAX) { + prescale = DT2821_PRESCALE_MAX; + divider = DT2821_DIVIDER_MAX; + base = DT2821_OSC_BASE * DT2821_PRESCALE(prescale); } - base = 250 * (1 << 15); - divider = 255; *ns = divider * base; - return (15 << 8) | (255 - divider); + return DT2821_TMRCTR_PRESCALE(prescale) | + DT2821_TMRCTR_DIVIDER(divider); } static void dt282x_munge(struct comedi_device *dev, @@ -683,13 +697,8 @@ static int dt282x_ai_cmdtest(struct comedi_device *dev, /* Step 3: check if arguments are trivially valid */ err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0); - err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0); - - err |= comedi_check_trigger_arg_min(&cmd->convert_arg, 4000); - -#define SLOWEST_TIMER (250*(1<<15)*255) - err |= comedi_check_trigger_arg_max(&cmd->convert_arg, SLOWEST_TIMER); + err |= comedi_check_trigger_arg_max(&cmd->convert_arg, DT2821_OSC_MAX); err |= comedi_check_trigger_arg_min(&cmd->convert_arg, board->ai_speed); err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len); @@ -1084,20 +1093,6 @@ static int dt282x_initialize(struct comedi_device *dev) return 0; } -/* - options: - 0 i/o base - 1 irq - 2 dma1 - 3 dma2 - 4 0=single ended, 1=differential - 5 ai 0=straight binary, 1=2's comp - 6 ao0 0=straight binary, 1=2's comp - 7 ao1 0=straight binary, 1=2's comp - 8 ai 0=±10 V, 1=0-10 V, 2=±5 V, 3=0-5 V - 9 ao0 0=±10 V, 1=0-10 V, 2=±5 V, 3=0-5 V, 4=±2.5 V - 10 ao1 0=±10 V, 1=0-10 V, 2=±5 V, 3=0-5 V, 4=±2.5 V - */ static int dt282x_attach(struct comedi_device *dev, struct comedi_devconfig *it) { const struct dt282x_board *board = dev->board_ptr; diff --git a/drivers/staging/comedi/drivers/mite.c b/drivers/staging/comedi/drivers/mite.c index 8f24702c3380..b1c0860135d0 100644 --- a/drivers/staging/comedi/drivers/mite.c +++ b/drivers/staging/comedi/drivers/mite.c @@ -46,355 +46,451 @@ #include <linux/module.h> #include <linux/slab.h> +#include <linux/log2.h> #include "../comedi_pci.h" #include "mite.h" -#define TOP_OF_PAGE(x) ((x)|(~(PAGE_MASK))) +/* + * Mite registers + */ +#define MITE_UNKNOWN_DMA_BURST_REG 0x28 +#define UNKNOWN_DMA_BURST_ENABLE_BITS 0x600 + +#define MITE_PCI_CONFIG_OFFSET 0x300 +#define MITE_CSIGR 0x460 /* chip signature */ +#define CSIGR_TO_IOWINS(x) (((x) >> 29) & 0x7) +#define CSIGR_TO_WINS(x) (((x) >> 24) & 0x1f) +#define CSIGR_TO_WPDEP(x) (((x) >> 20) & 0x7) +#define CSIGR_TO_DMAC(x) (((x) >> 16) & 0xf) +#define CSIGR_TO_IMODE(x) (((x) >> 12) & 0x3) /* pci=0x3 */ +#define CSIGR_TO_MMODE(x) (((x) >> 8) & 0x3) /* minimite=1 */ +#define CSIGR_TO_TYPE(x) (((x) >> 4) & 0xf) /* mite=0, minimite=1 */ +#define CSIGR_TO_VER(x) (((x) >> 0) & 0xf) + +#define MITE_CHAN(x) (0x500 + 0x100 * (x)) +#define MITE_CHOR(x) (0x00 + MITE_CHAN(x)) /* channel operation */ +#define CHOR_DMARESET BIT(31) +#define CHOR_SET_SEND_TC BIT(11) +#define CHOR_CLR_SEND_TC BIT(10) +#define CHOR_SET_LPAUSE BIT(9) +#define CHOR_CLR_LPAUSE BIT(8) +#define CHOR_CLRDONE BIT(7) +#define CHOR_CLRRB BIT(6) +#define CHOR_CLRLC BIT(5) +#define CHOR_FRESET BIT(4) +#define CHOR_ABORT BIT(3) /* stop without emptying fifo */ +#define CHOR_STOP BIT(2) /* stop after emptying fifo */ +#define CHOR_CONT BIT(1) +#define CHOR_START BIT(0) +#define MITE_CHCR(x) (0x04 + MITE_CHAN(x)) /* channel control */ +#define CHCR_SET_DMA_IE BIT(31) +#define CHCR_CLR_DMA_IE BIT(30) +#define CHCR_SET_LINKP_IE BIT(29) +#define CHCR_CLR_LINKP_IE BIT(28) +#define CHCR_SET_SAR_IE BIT(27) +#define CHCR_CLR_SAR_IE BIT(26) +#define CHCR_SET_DONE_IE BIT(25) +#define CHCR_CLR_DONE_IE BIT(24) +#define CHCR_SET_MRDY_IE BIT(23) +#define CHCR_CLR_MRDY_IE BIT(22) +#define CHCR_SET_DRDY_IE BIT(21) +#define CHCR_CLR_DRDY_IE BIT(20) +#define CHCR_SET_LC_IE BIT(19) +#define CHCR_CLR_LC_IE BIT(18) +#define CHCR_SET_CONT_RB_IE BIT(17) +#define CHCR_CLR_CONT_RB_IE BIT(16) +#define CHCR_FIFO(x) (((x) & 0x1) << 15) +#define CHCR_FIFODIS CHCR_FIFO(1) +#define CHCR_FIFO_ON CHCR_FIFO(0) +#define CHCR_BURST(x) (((x) & 0x1) << 14) +#define CHCR_BURSTEN CHCR_BURST(1) +#define CHCR_NO_BURSTEN CHCR_BURST(0) +#define CHCR_BYTE_SWAP_DEVICE BIT(6) +#define CHCR_BYTE_SWAP_MEMORY BIT(4) +#define CHCR_DIR(x) (((x) & 0x1) << 3) +#define CHCR_DEV_TO_MEM CHCR_DIR(1) +#define CHCR_MEM_TO_DEV CHCR_DIR(0) +#define CHCR_MODE(x) (((x) & 0x7) << 0) +#define CHCR_NORMAL CHCR_MODE(0) +#define CHCR_CONTINUE CHCR_MODE(1) +#define CHCR_RINGBUFF CHCR_MODE(2) +#define CHCR_LINKSHORT CHCR_MODE(4) +#define CHCR_LINKLONG CHCR_MODE(5) +#define MITE_TCR(x) (0x08 + MITE_CHAN(x)) /* transfer count */ +#define MITE_MCR(x) (0x0c + MITE_CHAN(x)) /* memory config */ +#define MITE_MAR(x) (0x10 + MITE_CHAN(x)) /* memory address */ +#define MITE_DCR(x) (0x14 + MITE_CHAN(x)) /* device config */ +#define DCR_NORMAL BIT(29) +#define MITE_DAR(x) (0x18 + MITE_CHAN(x)) /* device address */ +#define MITE_LKCR(x) (0x1c + MITE_CHAN(x)) /* link config */ +#define MITE_LKAR(x) (0x20 + MITE_CHAN(x)) /* link address */ +#define MITE_LLKAR(x) (0x24 + MITE_CHAN(x)) /* see tnt5002 manual */ +#define MITE_BAR(x) (0x28 + MITE_CHAN(x)) /* base address */ +#define MITE_BCR(x) (0x2c + MITE_CHAN(x)) /* base count */ +#define MITE_SAR(x) (0x30 + MITE_CHAN(x)) /* ? address */ +#define MITE_WSCR(x) (0x34 + MITE_CHAN(x)) /* ? */ +#define MITE_WSER(x) (0x38 + MITE_CHAN(x)) /* ? */ +#define MITE_CHSR(x) (0x3c + MITE_CHAN(x)) /* channel status */ +#define CHSR_INT BIT(31) +#define CHSR_LPAUSES BIT(29) +#define CHSR_SARS BIT(27) +#define CHSR_DONE BIT(25) +#define CHSR_MRDY BIT(23) +#define CHSR_DRDY BIT(21) +#define CHSR_LINKC BIT(19) +#define CHSR_CONTS_RB BIT(17) +#define CHSR_ERROR BIT(15) +#define CHSR_SABORT BIT(14) +#define CHSR_HABORT BIT(13) +#define CHSR_STOPS BIT(12) +#define CHSR_OPERR(x) (((x) & 0x3) << 10) +#define CHSR_OPERR_MASK CHSR_OPERR(3) +#define CHSR_OPERR_NOERROR CHSR_OPERR(0) +#define CHSR_OPERR_FIFOERROR CHSR_OPERR(1) +#define CHSR_OPERR_LINKERROR CHSR_OPERR(1) /* ??? */ +#define CHSR_XFERR BIT(9) +#define CHSR_END BIT(8) +#define CHSR_DRQ1 BIT(7) +#define CHSR_DRQ0 BIT(6) +#define CHSR_LERR(x) (((x) & 0x3) << 4) +#define CHSR_LERR_MASK CHSR_LERR(3) +#define CHSR_LBERR CHSR_LERR(1) +#define CHSR_LRERR CHSR_LERR(2) +#define CHSR_LOERR CHSR_LERR(3) +#define CHSR_MERR(x) (((x) & 0x3) << 2) +#define CHSR_MERR_MASK CHSR_MERR(3) +#define CHSR_MBERR CHSR_MERR(1) +#define CHSR_MRERR CHSR_MERR(2) +#define CHSR_MOERR CHSR_MERR(3) +#define CHSR_DERR(x) (((x) & 0x3) << 0) +#define CHSR_DERR_MASK CHSR_DERR(3) +#define CHSR_DBERR CHSR_DERR(1) +#define CHSR_DRERR CHSR_DERR(2) +#define CHSR_DOERR CHSR_DERR(3) +#define MITE_FCR(x) (0x40 + MITE_CHAN(x)) /* fifo count */ + +/* common bits for the memory/device/link config registers */ +#define CR_RL(x) (((x) & 0x7) << 21) +#define CR_REQS(x) (((x) & 0x7) << 16) +#define CR_REQS_MASK CR_REQS(7) +#define CR_ASEQ(x) (((x) & 0x3) << 10) +#define CR_ASEQDONT CR_ASEQ(0) +#define CR_ASEQUP CR_ASEQ(1) +#define CR_ASEQDOWN CR_ASEQ(2) +#define CR_ASEQ_MASK CR_ASEQ(3) +#define CR_PSIZE(x) (((x) & 0x3) << 8) +#define CR_PSIZE8 CR_PSIZE(1) +#define CR_PSIZE16 CR_PSIZE(2) +#define CR_PSIZE32 CR_PSIZE(3) +#define CR_PORT(x) (((x) & 0x3) << 6) +#define CR_PORTCPU CR_PORT(0) +#define CR_PORTIO CR_PORT(1) +#define CR_PORTVXI CR_PORT(2) +#define CR_PORTMXI CR_PORT(3) +#define CR_AMDEVICE BIT(0) + +static unsigned int MITE_IODWBSR_1_WSIZE_bits(unsigned int size) +{ + return (ilog2(size) - 1) & 0x1f; +} -struct mite_struct *mite_alloc(struct pci_dev *pcidev) +static unsigned int mite_retry_limit(unsigned int retry_limit) { - struct mite_struct *mite; - unsigned int i; + unsigned int value = 0; - mite = kzalloc(sizeof(*mite), GFP_KERNEL); - if (mite) { - spin_lock_init(&mite->lock); - mite->pcidev = pcidev; - for (i = 0; i < MAX_MITE_DMA_CHANNELS; ++i) { - mite->channels[i].mite = mite; - mite->channels[i].channel = i; - mite->channels[i].done = 1; - } - } - return mite; + if (retry_limit) + value = 1 + ilog2(retry_limit); + if (value > 0x7) + value = 0x7; + return CR_RL(value); } -EXPORT_SYMBOL_GPL(mite_alloc); -static void dump_chip_signature(u32 csigr_bits) +static unsigned int mite_drq_reqs(unsigned int drq_line) { - pr_info("version = %i, type = %i, mite mode = %i, interface mode = %i\n", - mite_csigr_version(csigr_bits), mite_csigr_type(csigr_bits), - mite_csigr_mmode(csigr_bits), mite_csigr_imode(csigr_bits)); - pr_info("num channels = %i, write post fifo depth = %i, wins = %i, iowins = %i\n", - mite_csigr_dmac(csigr_bits), mite_csigr_wpdep(csigr_bits), - mite_csigr_wins(csigr_bits), mite_csigr_iowins(csigr_bits)); + /* This also works on m-series when using channels (drq_line) 4 or 5. */ + return CR_REQS((drq_line & 0x3) | 0x4); } -static unsigned mite_fifo_size(struct mite_struct *mite, unsigned channel) +static unsigned int mite_fifo_size(struct mite *mite, unsigned int channel) { - unsigned fcr_bits = readl(mite->mite_io_addr + MITE_FCR(channel)); - unsigned empty_count = (fcr_bits >> 16) & 0xff; - unsigned full_count = fcr_bits & 0xff; + unsigned int fcr_bits = readl(mite->mmio + MITE_FCR(channel)); + unsigned int empty_count = (fcr_bits >> 16) & 0xff; + unsigned int full_count = fcr_bits & 0xff; return empty_count + full_count; } -int mite_setup2(struct comedi_device *dev, - struct mite_struct *mite, bool use_win1) +static u32 mite_device_bytes_transferred(struct mite_channel *mite_chan) { - unsigned long length; - int i; - u32 csigr_bits; - unsigned unknown_dma_burst_bits; + struct mite *mite = mite_chan->mite; - pci_set_master(mite->pcidev); + return readl(mite->mmio + MITE_DAR(mite_chan->channel)); +} - mite->mite_io_addr = pci_ioremap_bar(mite->pcidev, 0); - if (!mite->mite_io_addr) { - dev_err(dev->class_dev, - "Failed to remap mite io memory address\n"); - return -ENOMEM; - } - mite->mite_phys_addr = pci_resource_start(mite->pcidev, 0); +/** + * mite_bytes_in_transit() - Returns the number of unread bytes in the fifo. + * @mite_chan: MITE dma channel. + */ +u32 mite_bytes_in_transit(struct mite_channel *mite_chan) +{ + struct mite *mite = mite_chan->mite; - dev->mmio = pci_ioremap_bar(mite->pcidev, 1); - if (!dev->mmio) { - dev_err(dev->class_dev, - "Failed to remap daq io memory address\n"); - return -ENOMEM; - } - mite->daq_phys_addr = pci_resource_start(mite->pcidev, 1); - length = pci_resource_len(mite->pcidev, 1); + return readl(mite->mmio + MITE_FCR(mite_chan->channel)) & 0xff; +} +EXPORT_SYMBOL_GPL(mite_bytes_in_transit); - if (use_win1) { - writel(0, mite->mite_io_addr + MITE_IODWBSR); - dev_info(dev->class_dev, - "using I/O Window Base Size register 1\n"); - writel(mite->daq_phys_addr | WENAB | - MITE_IODWBSR_1_WSIZE_bits(length), - mite->mite_io_addr + MITE_IODWBSR_1); - writel(0, mite->mite_io_addr + MITE_IODWCR_1); - } else { - writel(mite->daq_phys_addr | WENAB, - mite->mite_io_addr + MITE_IODWBSR); - } - /* - * Make sure dma bursts work. I got this from running a bus analyzer - * on a pxi-6281 and a pxi-6713. 6713 powered up with register value - * of 0x61f and bursts worked. 6281 powered up with register value of - * 0x1f and bursts didn't work. The NI windows driver reads the - * register, then does a bitwise-or of 0x600 with it and writes it back. - */ - unknown_dma_burst_bits = - readl(mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG); - unknown_dma_burst_bits |= UNKNOWN_DMA_BURST_ENABLE_BITS; - writel(unknown_dma_burst_bits, - mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG); +/* returns lower bound for number of bytes transferred from device to memory */ +static u32 mite_bytes_written_to_memory_lb(struct mite_channel *mite_chan) +{ + u32 device_byte_count; - csigr_bits = readl(mite->mite_io_addr + MITE_CSIGR); - mite->num_channels = mite_csigr_dmac(csigr_bits); - if (mite->num_channels > MAX_MITE_DMA_CHANNELS) { - dev_warn(dev->class_dev, - "mite: bug? chip claims to have %i dma channels. Setting to %i.\n", - mite->num_channels, MAX_MITE_DMA_CHANNELS); - mite->num_channels = MAX_MITE_DMA_CHANNELS; - } - dump_chip_signature(csigr_bits); - for (i = 0; i < mite->num_channels; i++) { - writel(CHOR_DMARESET, mite->mite_io_addr + MITE_CHOR(i)); - /* disable interrupts */ - writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE | - CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE | - CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE, - mite->mite_io_addr + MITE_CHCR(i)); - } - mite->fifo_size = mite_fifo_size(mite, 0); - dev_info(dev->class_dev, "fifo size is %i.\n", mite->fifo_size); - return 0; + device_byte_count = mite_device_bytes_transferred(mite_chan); + return device_byte_count - mite_bytes_in_transit(mite_chan); } -EXPORT_SYMBOL_GPL(mite_setup2); -void mite_detach(struct mite_struct *mite) +/* returns upper bound for number of bytes transferred from device to memory */ +static u32 mite_bytes_written_to_memory_ub(struct mite_channel *mite_chan) { - if (!mite) - return; - - if (mite->mite_io_addr) - iounmap(mite->mite_io_addr); + u32 in_transit_count; - kfree(mite); + in_transit_count = mite_bytes_in_transit(mite_chan); + return mite_device_bytes_transferred(mite_chan) - in_transit_count; } -EXPORT_SYMBOL_GPL(mite_detach); -struct mite_dma_descriptor_ring *mite_alloc_ring(struct mite_struct *mite) +/* returns lower bound for number of bytes read from memory to device */ +static u32 mite_bytes_read_from_memory_lb(struct mite_channel *mite_chan) { - struct mite_dma_descriptor_ring *ring = - kmalloc(sizeof(struct mite_dma_descriptor_ring), GFP_KERNEL); + u32 device_byte_count; - if (!ring) - return NULL; - ring->hw_dev = get_device(&mite->pcidev->dev); - if (!ring->hw_dev) { - kfree(ring); - return NULL; - } - ring->n_links = 0; - ring->descriptors = NULL; - ring->descriptors_dma_addr = 0; - return ring; -}; -EXPORT_SYMBOL_GPL(mite_alloc_ring); + device_byte_count = mite_device_bytes_transferred(mite_chan); + return device_byte_count + mite_bytes_in_transit(mite_chan); +} -void mite_free_ring(struct mite_dma_descriptor_ring *ring) +/* returns upper bound for number of bytes read from memory to device */ +static u32 mite_bytes_read_from_memory_ub(struct mite_channel *mite_chan) { - if (ring) { - if (ring->descriptors) { - dma_free_coherent(ring->hw_dev, - ring->n_links * - sizeof(struct mite_dma_descriptor), - ring->descriptors, - ring->descriptors_dma_addr); - } - put_device(ring->hw_dev); - kfree(ring); - } -}; -EXPORT_SYMBOL_GPL(mite_free_ring); + u32 in_transit_count; + + in_transit_count = mite_bytes_in_transit(mite_chan); + return mite_device_bytes_transferred(mite_chan) + in_transit_count; +} -struct mite_channel *mite_request_channel_in_range(struct mite_struct *mite, - struct - mite_dma_descriptor_ring - *ring, unsigned min_channel, - unsigned max_channel) +static void mite_sync_input_dma(struct mite_channel *mite_chan, + struct comedi_subdevice *s) { - int i; - unsigned long flags; - struct mite_channel *channel = NULL; + struct comedi_async *async = s->async; + int count; + unsigned int nbytes, old_alloc_count; + + old_alloc_count = async->buf_write_alloc_count; + /* write alloc as much as we can */ + comedi_buf_write_alloc(s, async->prealloc_bufsz); + nbytes = mite_bytes_written_to_memory_lb(mite_chan); + if ((int)(mite_bytes_written_to_memory_ub(mite_chan) - + old_alloc_count) > 0) { + dev_warn(s->device->class_dev, + "mite: DMA overwrite of free area\n"); + async->events |= COMEDI_CB_OVERFLOW; + return; + } + + count = nbytes - async->buf_write_count; /* - * spin lock so mite_release_channel can be called safely - * from interrupts + * it's possible count will be negative due to conservative value + * returned by mite_bytes_written_to_memory_lb */ - spin_lock_irqsave(&mite->lock, flags); - for (i = min_channel; i <= max_channel; ++i) { - if (mite->channel_allocated[i] == 0) { - mite->channel_allocated[i] = 1; - channel = &mite->channels[i]; - channel->ring = ring; - break; - } + if (count > 0) { + comedi_buf_write_free(s, count); + comedi_inc_scan_progress(s, count); + async->events |= COMEDI_CB_BLOCK; } - spin_unlock_irqrestore(&mite->lock, flags); - return channel; } -EXPORT_SYMBOL_GPL(mite_request_channel_in_range); -void mite_release_channel(struct mite_channel *mite_chan) +static void mite_sync_output_dma(struct mite_channel *mite_chan, + struct comedi_subdevice *s) { - struct mite_struct *mite = mite_chan->mite; - unsigned long flags; + struct comedi_async *async = s->async; + struct comedi_cmd *cmd = &async->cmd; + u32 stop_count = cmd->stop_arg * comedi_bytes_per_scan(s); + unsigned int old_alloc_count = async->buf_read_alloc_count; + u32 nbytes_ub, nbytes_lb; + int count; + bool finite_regen = (cmd->stop_src == TRIG_NONE && stop_count != 0); - /* spin lock to prevent races with mite_request_channel */ - spin_lock_irqsave(&mite->lock, flags); - if (mite->channel_allocated[mite_chan->channel]) { - mite_dma_disarm(mite_chan); - mite_dma_reset(mite_chan); + /* read alloc as much as we can */ + comedi_buf_read_alloc(s, async->prealloc_bufsz); + nbytes_lb = mite_bytes_read_from_memory_lb(mite_chan); + if (cmd->stop_src == TRIG_COUNT && (int)(nbytes_lb - stop_count) > 0) + nbytes_lb = stop_count; + nbytes_ub = mite_bytes_read_from_memory_ub(mite_chan); + if (cmd->stop_src == TRIG_COUNT && (int)(nbytes_ub - stop_count) > 0) + nbytes_ub = stop_count; + + if ((!finite_regen || stop_count > old_alloc_count) && + ((int)(nbytes_ub - old_alloc_count) > 0)) { + dev_warn(s->device->class_dev, "mite: DMA underrun\n"); + async->events |= COMEDI_CB_OVERFLOW; + return; + } + + if (finite_regen) { /* - * disable all channel's interrupts (do it after disarm/reset so - * MITE_CHCR reg isn't changed while dma is still active!) + * This is a special case where we continuously output a finite + * buffer. In this case, we do not free any of the memory, + * hence we expect that old_alloc_count will reach a maximum of + * stop_count bytes. */ - writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | - CHCR_CLR_SAR_IE | CHCR_CLR_DONE_IE | - CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE | - CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE, - mite->mite_io_addr + MITE_CHCR(mite_chan->channel)); - mite->channel_allocated[mite_chan->channel] = 0; - mite_chan->ring = NULL; - mmiowb(); + return; + } + + count = nbytes_lb - async->buf_read_count; + if (count > 0) { + comedi_buf_read_free(s, count); + async->events |= COMEDI_CB_BLOCK; } - spin_unlock_irqrestore(&mite->lock, flags); } -EXPORT_SYMBOL_GPL(mite_release_channel); -void mite_dma_arm(struct mite_channel *mite_chan) +/** + * mite_sync_dma() - Sync the MITE dma with the COMEDI async buffer. + * @mite_chan: MITE dma channel. + * @s: COMEDI subdevice. + */ +void mite_sync_dma(struct mite_channel *mite_chan, struct comedi_subdevice *s) +{ + if (mite_chan->dir == COMEDI_INPUT) + mite_sync_input_dma(mite_chan, s); + else + mite_sync_output_dma(mite_chan, s); +} +EXPORT_SYMBOL_GPL(mite_sync_dma); + +static unsigned int mite_get_status(struct mite_channel *mite_chan) { - struct mite_struct *mite = mite_chan->mite; - int chor; + struct mite *mite = mite_chan->mite; + unsigned int status; unsigned long flags; - /* - * memory barrier is intended to insure any twiddling with the buffer - * is done before writing to the mite to arm dma transfer - */ - smp_mb(); - /* arm */ - chor = CHOR_START; spin_lock_irqsave(&mite->lock, flags); - mite_chan->done = 0; - writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel)); + status = readl(mite->mmio + MITE_CHSR(mite_chan->channel)); + if (status & CHSR_DONE) { + mite_chan->done = 1; + writel(CHOR_CLRDONE, + mite->mmio + MITE_CHOR(mite_chan->channel)); + } mmiowb(); spin_unlock_irqrestore(&mite->lock, flags); - /* mite_dma_tcr(mite, channel); */ + return status; } -EXPORT_SYMBOL_GPL(mite_dma_arm); -/**************************************/ - -int mite_buf_change(struct mite_dma_descriptor_ring *ring, - struct comedi_subdevice *s) +/** + * mite_ack_linkc() - Check and ack the LINKC interrupt, + * @mite_chan: MITE dma channel. + * @s: COMEDI subdevice. + * @sync: flag to force a mite_sync_dma(). + * + * This will also ack the DONE interrupt if active. + */ +void mite_ack_linkc(struct mite_channel *mite_chan, + struct comedi_subdevice *s, + bool sync) { - struct comedi_async *async = s->async; - unsigned int n_links; + struct mite *mite = mite_chan->mite; + unsigned int status; - if (ring->descriptors) { - dma_free_coherent(ring->hw_dev, - ring->n_links * - sizeof(struct mite_dma_descriptor), - ring->descriptors, - ring->descriptors_dma_addr); + status = mite_get_status(mite_chan); + if (status & CHSR_LINKC) { + writel(CHOR_CLRLC, mite->mmio + MITE_CHOR(mite_chan->channel)); + sync = true; } - ring->descriptors = NULL; - ring->descriptors_dma_addr = 0; - ring->n_links = 0; + if (sync) + mite_sync_dma(mite_chan, s); - if (async->prealloc_bufsz == 0) - return 0; - - n_links = async->prealloc_bufsz >> PAGE_SHIFT; - - ring->descriptors = - dma_alloc_coherent(ring->hw_dev, - n_links * sizeof(struct mite_dma_descriptor), - &ring->descriptors_dma_addr, GFP_KERNEL); - if (!ring->descriptors) { + if (status & CHSR_XFERR) { dev_err(s->device->class_dev, - "mite: ring buffer allocation failed\n"); - return -ENOMEM; + "mite: transfer error %08x\n", status); + s->async->events |= COMEDI_CB_ERROR; } - ring->n_links = n_links; - - return mite_init_ring_descriptors(ring, s, n_links << PAGE_SHIFT); } -EXPORT_SYMBOL_GPL(mite_buf_change); +EXPORT_SYMBOL_GPL(mite_ack_linkc); -/* - * initializes the ring buffer descriptors to provide correct DMA transfer links - * to the exact amount of memory required. When the ring buffer is allocated in - * mite_buf_change, the default is to initialize the ring to refer to the entire - * DMA data buffer. A command may call this function later to re-initialize and - * shorten the amount of memory that will be transferred. +/** + * mite_done() - Check is a MITE dma transfer is complete. + * @mite_chan: MITE dma channel. + * + * This will also ack the DONE interrupt if active. */ -int mite_init_ring_descriptors(struct mite_dma_descriptor_ring *ring, - struct comedi_subdevice *s, - unsigned int nbytes) +int mite_done(struct mite_channel *mite_chan) { - struct comedi_async *async = s->async; - unsigned int n_full_links = nbytes >> PAGE_SHIFT; - unsigned int remainder = nbytes % PAGE_SIZE; - int i; - - dev_dbg(s->device->class_dev, - "mite: init ring buffer to %u bytes\n", nbytes); - - if ((n_full_links + (remainder > 0 ? 1 : 0)) > ring->n_links) { - dev_err(s->device->class_dev, - "mite: ring buffer too small for requested init\n"); - return -ENOMEM; - } + struct mite *mite = mite_chan->mite; + unsigned long flags; + int done; - /* We set the descriptors for all full links. */ - for (i = 0; i < n_full_links; ++i) { - ring->descriptors[i].count = cpu_to_le32(PAGE_SIZE); - ring->descriptors[i].addr = - cpu_to_le32(async->buf_map->page_list[i].dma_addr); - ring->descriptors[i].next = - cpu_to_le32(ring->descriptors_dma_addr + - (i + 1) * sizeof(struct mite_dma_descriptor)); - } + mite_get_status(mite_chan); + spin_lock_irqsave(&mite->lock, flags); + done = mite_chan->done; + spin_unlock_irqrestore(&mite->lock, flags); + return done; +} +EXPORT_SYMBOL_GPL(mite_done); - /* the last link is either a remainder or was a full link. */ - if (remainder > 0) { - /* set the lesser count for the remainder link */ - ring->descriptors[i].count = cpu_to_le32(remainder); - ring->descriptors[i].addr = - cpu_to_le32(async->buf_map->page_list[i].dma_addr); - /* increment i so that assignment below refs last link */ - ++i; - } +static void mite_dma_reset(struct mite_channel *mite_chan) +{ + writel(CHOR_DMARESET | CHOR_FRESET, + mite_chan->mite->mmio + MITE_CHOR(mite_chan->channel)); +} - /* Assign the last link->next to point back to the head of the list. */ - ring->descriptors[i - 1].next = cpu_to_le32(ring->descriptors_dma_addr); +/** + * mite_dma_arm() - Start a MITE dma transfer. + * @mite_chan: MITE dma channel. + */ +void mite_dma_arm(struct mite_channel *mite_chan) +{ + struct mite *mite = mite_chan->mite; + unsigned long flags; /* - * barrier is meant to insure that all the writes to the dma descriptors - * have completed before the dma controller is commanded to read them + * memory barrier is intended to insure any twiddling with the buffer + * is done before writing to the mite to arm dma transfer */ - smp_wmb(); - return 0; + smp_mb(); + spin_lock_irqsave(&mite->lock, flags); + mite_chan->done = 0; + /* arm */ + writel(CHOR_START, mite->mmio + MITE_CHOR(mite_chan->channel)); + mmiowb(); + spin_unlock_irqrestore(&mite->lock, flags); } -EXPORT_SYMBOL_GPL(mite_init_ring_descriptors); +EXPORT_SYMBOL_GPL(mite_dma_arm); + +/** + * mite_dma_disarm() - Stop a MITE dma transfer. + * @mite_chan: MITE dma channel. + */ +void mite_dma_disarm(struct mite_channel *mite_chan) +{ + struct mite *mite = mite_chan->mite; + + /* disarm */ + writel(CHOR_ABORT, mite->mmio + MITE_CHOR(mite_chan->channel)); +} +EXPORT_SYMBOL_GPL(mite_dma_disarm); +/** + * mite_prep_dma() - Prepare a MITE dma channel for transfers. + * @mite_chan: MITE dma channel. + * @num_device_bits: device transfer size (8, 16, or 32-bits). + * @num_memory_bits: memory transfer size (8, 16, or 32-bits). + */ void mite_prep_dma(struct mite_channel *mite_chan, unsigned int num_device_bits, unsigned int num_memory_bits) { - unsigned int chor, chcr, mcr, dcr, lkcr; - struct mite_struct *mite = mite_chan->mite; + struct mite *mite = mite_chan->mite; + unsigned int chcr, mcr, dcr, lkcr; - /* reset DMA and FIFO */ - chor = CHOR_DMARESET | CHOR_FRESET; - writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel)); + mite_dma_reset(mite_chan); /* short link chaining mode */ chcr = CHCR_SET_DMA_IE | CHCR_LINKSHORT | CHCR_SET_DONE_IE | @@ -421,10 +517,10 @@ void mite_prep_dma(struct mite_channel *mite_chan, if (mite_chan->dir == COMEDI_INPUT) chcr |= CHCR_DEV_TO_MEM; - writel(chcr, mite->mite_io_addr + MITE_CHCR(mite_chan->channel)); + writel(chcr, mite->mmio + MITE_CHCR(mite_chan->channel)); /* to/from memory */ - mcr = CR_RL(64) | CR_ASEQUP; + mcr = mite_retry_limit(64) | CR_ASEQUP; switch (num_memory_bits) { case 8: mcr |= CR_PSIZE8; @@ -439,11 +535,11 @@ void mite_prep_dma(struct mite_channel *mite_chan, pr_warn("bug! invalid mem bit width for dma transfer\n"); break; } - writel(mcr, mite->mite_io_addr + MITE_MCR(mite_chan->channel)); + writel(mcr, mite->mmio + MITE_MCR(mite_chan->channel)); /* from/to device */ - dcr = CR_RL(64) | CR_ASEQUP; - dcr |= CR_PORTIO | CR_AMDEVICE | CR_REQSDRQ(mite_chan->channel); + dcr = mite_retry_limit(64) | CR_ASEQUP; + dcr |= CR_PORTIO | CR_AMDEVICE | mite_drq_reqs(mite_chan->channel); switch (num_device_bits) { case 8: dcr |= CR_PSIZE8; @@ -458,223 +554,402 @@ void mite_prep_dma(struct mite_channel *mite_chan, pr_warn("bug! invalid dev bit width for dma transfer\n"); break; } - writel(dcr, mite->mite_io_addr + MITE_DCR(mite_chan->channel)); + writel(dcr, mite->mmio + MITE_DCR(mite_chan->channel)); /* reset the DAR */ - writel(0, mite->mite_io_addr + MITE_DAR(mite_chan->channel)); + writel(0, mite->mmio + MITE_DAR(mite_chan->channel)); /* the link is 32bits */ - lkcr = CR_RL(64) | CR_ASEQUP | CR_PSIZE32; - writel(lkcr, mite->mite_io_addr + MITE_LKCR(mite_chan->channel)); + lkcr = mite_retry_limit(64) | CR_ASEQUP | CR_PSIZE32; + writel(lkcr, mite->mmio + MITE_LKCR(mite_chan->channel)); /* starting address for link chaining */ - writel(mite_chan->ring->descriptors_dma_addr, - mite->mite_io_addr + MITE_LKAR(mite_chan->channel)); + writel(mite_chan->ring->dma_addr, + mite->mmio + MITE_LKAR(mite_chan->channel)); } EXPORT_SYMBOL_GPL(mite_prep_dma); -static u32 mite_device_bytes_transferred(struct mite_channel *mite_chan) +static struct mite_channel *__mite_request_channel(struct mite *mite, + struct mite_ring *ring, + unsigned int min_channel, + unsigned int max_channel) { - struct mite_struct *mite = mite_chan->mite; + struct mite_channel *mite_chan = NULL; + unsigned long flags; + int i; - return readl(mite->mite_io_addr + MITE_DAR(mite_chan->channel)); + /* + * spin lock so mite_release_channel can be called safely + * from interrupts + */ + spin_lock_irqsave(&mite->lock, flags); + for (i = min_channel; i <= max_channel; ++i) { + mite_chan = &mite->channels[i]; + if (!mite_chan->ring) { + mite_chan->ring = ring; + break; + } + mite_chan = NULL; + } + spin_unlock_irqrestore(&mite->lock, flags); + return mite_chan; } -u32 mite_bytes_in_transit(struct mite_channel *mite_chan) +/** + * mite_request_channel_in_range() - Request a MITE dma channel. + * @mite: MITE device. + * @ring: MITE dma ring. + * @min_channel: minimum channel index to use. + * @max_channel: maximum channel index to use. + */ +struct mite_channel *mite_request_channel_in_range(struct mite *mite, + struct mite_ring *ring, + unsigned int min_channel, + unsigned int max_channel) { - struct mite_struct *mite = mite_chan->mite; - - return readl(mite->mite_io_addr + - MITE_FCR(mite_chan->channel)) & 0x000000FF; + return __mite_request_channel(mite, ring, min_channel, max_channel); } -EXPORT_SYMBOL_GPL(mite_bytes_in_transit); +EXPORT_SYMBOL_GPL(mite_request_channel_in_range); -/* returns lower bound for number of bytes transferred from device to memory */ -u32 mite_bytes_written_to_memory_lb(struct mite_channel *mite_chan) +/** + * mite_request_channel() - Request a MITE dma channel. + * @mite: MITE device. + * @ring: MITE dma ring. + */ +struct mite_channel *mite_request_channel(struct mite *mite, + struct mite_ring *ring) { - u32 device_byte_count; - - device_byte_count = mite_device_bytes_transferred(mite_chan); - return device_byte_count - mite_bytes_in_transit(mite_chan); + return __mite_request_channel(mite, ring, 0, mite->num_channels - 1); } -EXPORT_SYMBOL_GPL(mite_bytes_written_to_memory_lb); +EXPORT_SYMBOL_GPL(mite_request_channel); -/* returns upper bound for number of bytes transferred from device to memory */ -u32 mite_bytes_written_to_memory_ub(struct mite_channel *mite_chan) +/** + * mite_release_channel() - Release a MITE dma channel. + * @mite_chan: MITE dma channel. + */ +void mite_release_channel(struct mite_channel *mite_chan) { - u32 in_transit_count; + struct mite *mite = mite_chan->mite; + unsigned long flags; - in_transit_count = mite_bytes_in_transit(mite_chan); - return mite_device_bytes_transferred(mite_chan) - in_transit_count; + /* spin lock to prevent races with mite_request_channel */ + spin_lock_irqsave(&mite->lock, flags); + if (mite_chan->ring) { + mite_dma_disarm(mite_chan); + mite_dma_reset(mite_chan); + /* + * disable all channel's interrupts (do it after disarm/reset so + * MITE_CHCR reg isn't changed while dma is still active!) + */ + writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | + CHCR_CLR_SAR_IE | CHCR_CLR_DONE_IE | + CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE | + CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE, + mite->mmio + MITE_CHCR(mite_chan->channel)); + mite_chan->ring = NULL; + mmiowb(); + } + spin_unlock_irqrestore(&mite->lock, flags); } -EXPORT_SYMBOL_GPL(mite_bytes_written_to_memory_ub); +EXPORT_SYMBOL_GPL(mite_release_channel); -/* returns lower bound for number of bytes read from memory to device */ -u32 mite_bytes_read_from_memory_lb(struct mite_channel *mite_chan) +/** + * mite_init_ring_descriptors() - Initialize a MITE dma ring descriptors. + * @ring: MITE dma ring. + * @s: COMEDI subdevice. + * @nbytes: the size of the dma ring (in bytes). + * + * Initializes the ring buffer descriptors to provide correct DMA transfer + * links to the exact amount of memory required. When the ring buffer is + * allocated by mite_buf_change(), the default is to initialize the ring + * to refer to the entire DMA data buffer. A command may call this function + * later to re-initialize and shorten the amount of memory that will be + * transferred. + */ +int mite_init_ring_descriptors(struct mite_ring *ring, + struct comedi_subdevice *s, + unsigned int nbytes) { - u32 device_byte_count; + struct comedi_async *async = s->async; + struct mite_dma_desc *desc = NULL; + unsigned int n_full_links = nbytes >> PAGE_SHIFT; + unsigned int remainder = nbytes % PAGE_SIZE; + int i; - device_byte_count = mite_device_bytes_transferred(mite_chan); - return device_byte_count + mite_bytes_in_transit(mite_chan); -} -EXPORT_SYMBOL_GPL(mite_bytes_read_from_memory_lb); + dev_dbg(s->device->class_dev, + "mite: init ring buffer to %u bytes\n", nbytes); -/* returns upper bound for number of bytes read from memory to device */ -u32 mite_bytes_read_from_memory_ub(struct mite_channel *mite_chan) -{ - u32 in_transit_count; + if ((n_full_links + (remainder > 0 ? 1 : 0)) > ring->n_links) { + dev_err(s->device->class_dev, + "mite: ring buffer too small for requested init\n"); + return -ENOMEM; + } - in_transit_count = mite_bytes_in_transit(mite_chan); - return mite_device_bytes_transferred(mite_chan) + in_transit_count; -} -EXPORT_SYMBOL_GPL(mite_bytes_read_from_memory_ub); + /* We set the descriptors for all full links. */ + for (i = 0; i < n_full_links; ++i) { + desc = &ring->descs[i]; + desc->count = cpu_to_le32(PAGE_SIZE); + desc->addr = cpu_to_le32(async->buf_map->page_list[i].dma_addr); + desc->next = cpu_to_le32(ring->dma_addr + + (i + 1) * sizeof(*desc)); + } -unsigned mite_dma_tcr(struct mite_channel *mite_chan) -{ - struct mite_struct *mite = mite_chan->mite; + /* the last link is either a remainder or was a full link. */ + if (remainder > 0) { + desc = &ring->descs[i]; + /* set the lesser count for the remainder link */ + desc->count = cpu_to_le32(remainder); + desc->addr = cpu_to_le32(async->buf_map->page_list[i].dma_addr); + } + + /* Assign the last link->next to point back to the head of the list. */ + desc->next = cpu_to_le32(ring->dma_addr); - return readl(mite->mite_io_addr + MITE_TCR(mite_chan->channel)); + /* + * barrier is meant to insure that all the writes to the dma descriptors + * have completed before the dma controller is commanded to read them + */ + smp_wmb(); + return 0; } -EXPORT_SYMBOL_GPL(mite_dma_tcr); +EXPORT_SYMBOL_GPL(mite_init_ring_descriptors); -void mite_dma_disarm(struct mite_channel *mite_chan) +static void mite_free_dma_descs(struct mite_ring *ring) { - struct mite_struct *mite = mite_chan->mite; - unsigned chor; + struct mite_dma_desc *descs = ring->descs; - /* disarm */ - chor = CHOR_ABORT; - writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel)); + if (descs) { + dma_free_coherent(ring->hw_dev, + ring->n_links * sizeof(*descs), + descs, ring->dma_addr); + ring->descs = NULL; + ring->dma_addr = 0; + ring->n_links = 0; + } } -EXPORT_SYMBOL_GPL(mite_dma_disarm); -int mite_sync_input_dma(struct mite_channel *mite_chan, - struct comedi_subdevice *s) +/** + * mite_buf_change() - COMEDI subdevice (*buf_change) for a MITE dma ring. + * @ring: MITE dma ring. + * @s: COMEDI subdevice. + */ +int mite_buf_change(struct mite_ring *ring, struct comedi_subdevice *s) { struct comedi_async *async = s->async; - int count; - unsigned int nbytes, old_alloc_count; + struct mite_dma_desc *descs; + unsigned int n_links; - old_alloc_count = async->buf_write_alloc_count; - /* write alloc as much as we can */ - comedi_buf_write_alloc(s, async->prealloc_bufsz); + mite_free_dma_descs(ring); - nbytes = mite_bytes_written_to_memory_lb(mite_chan); - if ((int)(mite_bytes_written_to_memory_ub(mite_chan) - - old_alloc_count) > 0) { - dev_warn(s->device->class_dev, - "mite: DMA overwrite of free area\n"); - async->events |= COMEDI_CB_OVERFLOW; - return -1; + if (async->prealloc_bufsz == 0) + return 0; + + n_links = async->prealloc_bufsz >> PAGE_SHIFT; + + descs = dma_alloc_coherent(ring->hw_dev, + n_links * sizeof(*descs), + &ring->dma_addr, GFP_KERNEL); + if (!descs) { + dev_err(s->device->class_dev, + "mite: ring buffer allocation failed\n"); + return -ENOMEM; } + ring->descs = descs; + ring->n_links = n_links; - count = nbytes - async->buf_write_count; - /* - * it's possible count will be negative due to conservative value - * returned by mite_bytes_written_to_memory_lb - */ - if (count <= 0) - return 0; + return mite_init_ring_descriptors(ring, s, n_links << PAGE_SHIFT); +} +EXPORT_SYMBOL_GPL(mite_buf_change); - comedi_buf_write_free(s, count); - comedi_inc_scan_progress(s, count); - async->events |= COMEDI_CB_BLOCK; - return 0; +/** + * mite_alloc_ring() - Allocate a MITE dma ring. + * @mite: MITE device. + */ +struct mite_ring *mite_alloc_ring(struct mite *mite) +{ + struct mite_ring *ring; + + ring = kmalloc(sizeof(*ring), GFP_KERNEL); + if (!ring) + return NULL; + ring->hw_dev = get_device(&mite->pcidev->dev); + if (!ring->hw_dev) { + kfree(ring); + return NULL; + } + ring->n_links = 0; + ring->descs = NULL; + ring->dma_addr = 0; + return ring; } -EXPORT_SYMBOL_GPL(mite_sync_input_dma); +EXPORT_SYMBOL_GPL(mite_alloc_ring); -int mite_sync_output_dma(struct mite_channel *mite_chan, - struct comedi_subdevice *s) +/** + * mite_free_ring() - Free a MITE dma ring and its descriptors. + * @ring: MITE dma ring. + */ +void mite_free_ring(struct mite_ring *ring) { - struct comedi_async *async = s->async; - struct comedi_cmd *cmd = &async->cmd; - u32 stop_count = cmd->stop_arg * comedi_bytes_per_scan(s); - unsigned int old_alloc_count = async->buf_read_alloc_count; - u32 nbytes_ub, nbytes_lb; - int count; - bool finite_regen = (cmd->stop_src == TRIG_NONE && stop_count != 0); + if (ring) { + mite_free_dma_descs(ring); + put_device(ring->hw_dev); + kfree(ring); + } +} +EXPORT_SYMBOL_GPL(mite_free_ring); - /* read alloc as much as we can */ - comedi_buf_read_alloc(s, async->prealloc_bufsz); - nbytes_lb = mite_bytes_read_from_memory_lb(mite_chan); - if (cmd->stop_src == TRIG_COUNT && (int)(nbytes_lb - stop_count) > 0) - nbytes_lb = stop_count; - nbytes_ub = mite_bytes_read_from_memory_ub(mite_chan); - if (cmd->stop_src == TRIG_COUNT && (int)(nbytes_ub - stop_count) > 0) - nbytes_ub = stop_count; +static int mite_setup(struct comedi_device *dev, struct mite *mite, + bool use_win1) +{ + resource_size_t daq_phys_addr; + unsigned long length; + int i; + u32 csigr_bits; + unsigned int unknown_dma_burst_bits; + unsigned int wpdep; - if ((!finite_regen || stop_count > old_alloc_count) && - ((int)(nbytes_ub - old_alloc_count) > 0)) { - dev_warn(s->device->class_dev, "mite: DMA underrun\n"); - async->events |= COMEDI_CB_OVERFLOW; - return -1; + pci_set_master(mite->pcidev); + + mite->mmio = pci_ioremap_bar(mite->pcidev, 0); + if (!mite->mmio) + return -ENOMEM; + + dev->mmio = pci_ioremap_bar(mite->pcidev, 1); + if (!dev->mmio) + return -ENOMEM; + daq_phys_addr = pci_resource_start(mite->pcidev, 1); + length = pci_resource_len(mite->pcidev, 1); + + if (use_win1) { + writel(0, mite->mmio + MITE_IODWBSR); + dev_dbg(dev->class_dev, + "mite: using I/O Window Base Size register 1\n"); + writel(daq_phys_addr | WENAB | + MITE_IODWBSR_1_WSIZE_bits(length), + mite->mmio + MITE_IODWBSR_1); + writel(0, mite->mmio + MITE_IODWCR_1); + } else { + writel(daq_phys_addr | WENAB, mite->mmio + MITE_IODWBSR); } + /* + * Make sure dma bursts work. I got this from running a bus analyzer + * on a pxi-6281 and a pxi-6713. 6713 powered up with register value + * of 0x61f and bursts worked. 6281 powered up with register value of + * 0x1f and bursts didn't work. The NI windows driver reads the + * register, then does a bitwise-or of 0x600 with it and writes it back. + * + * The bits 0x90180700 in MITE_UNKNOWN_DMA_BURST_REG can be + * written and read back. The bits 0x1f always read as 1. + * The rest always read as zero. + */ + unknown_dma_burst_bits = readl(mite->mmio + MITE_UNKNOWN_DMA_BURST_REG); + unknown_dma_burst_bits |= UNKNOWN_DMA_BURST_ENABLE_BITS; + writel(unknown_dma_burst_bits, mite->mmio + MITE_UNKNOWN_DMA_BURST_REG); - if (finite_regen) { - /* - * This is a special case where we continuously output a finite - * buffer. In this case, we do not free any of the memory, - * hence we expect that old_alloc_count will reach a maximum of - * stop_count bytes. - */ - return 0; + csigr_bits = readl(mite->mmio + MITE_CSIGR); + mite->num_channels = CSIGR_TO_DMAC(csigr_bits); + if (mite->num_channels > MAX_MITE_DMA_CHANNELS) { + dev_warn(dev->class_dev, + "mite: bug? chip claims to have %i dma channels. Setting to %i.\n", + mite->num_channels, MAX_MITE_DMA_CHANNELS); + mite->num_channels = MAX_MITE_DMA_CHANNELS; } - count = nbytes_lb - async->buf_read_count; - if (count <= 0) - return 0; + /* get the wpdep bits and convert it to the write port fifo depth */ + wpdep = CSIGR_TO_WPDEP(csigr_bits); + if (wpdep) + wpdep = BIT(wpdep); - if (count) { - comedi_buf_read_free(s, count); - async->events |= COMEDI_CB_BLOCK; + dev_dbg(dev->class_dev, + "mite: version = %i, type = %i, mite mode = %i, interface mode = %i\n", + CSIGR_TO_VER(csigr_bits), CSIGR_TO_TYPE(csigr_bits), + CSIGR_TO_MMODE(csigr_bits), CSIGR_TO_IMODE(csigr_bits)); + dev_dbg(dev->class_dev, + "mite: num channels = %i, write post fifo depth = %i, wins = %i, iowins = %i\n", + CSIGR_TO_DMAC(csigr_bits), wpdep, + CSIGR_TO_WINS(csigr_bits), CSIGR_TO_IOWINS(csigr_bits)); + + for (i = 0; i < mite->num_channels; i++) { + writel(CHOR_DMARESET, mite->mmio + MITE_CHOR(i)); + /* disable interrupts */ + writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE | + CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE | + CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE, + mite->mmio + MITE_CHCR(i)); } + mite->fifo_size = mite_fifo_size(mite, 0); + dev_dbg(dev->class_dev, "mite: fifo size is %i.\n", mite->fifo_size); return 0; } -EXPORT_SYMBOL_GPL(mite_sync_output_dma); -unsigned mite_get_status(struct mite_channel *mite_chan) +/** + * mite_attach() - Allocate and initialize a MITE device for a comedi driver. + * @dev: COMEDI device. + * @use_win1: flag to use I/O Window 1 instead of I/O Window 0. + * + * Called by a COMEDI drivers (*auto_attach). + * + * Returns a pointer to the MITE device on success, or NULL if the MITE cannot + * be allocated or remapped. + */ +struct mite *mite_attach(struct comedi_device *dev, bool use_win1) { - struct mite_struct *mite = mite_chan->mite; - unsigned status; - unsigned long flags; + struct pci_dev *pcidev = comedi_to_pci_dev(dev); + struct mite *mite; + unsigned int i; + int ret; - spin_lock_irqsave(&mite->lock, flags); - status = readl(mite->mite_io_addr + MITE_CHSR(mite_chan->channel)); - if (status & CHSR_DONE) { - mite_chan->done = 1; - writel(CHOR_CLRDONE, - mite->mite_io_addr + MITE_CHOR(mite_chan->channel)); + mite = kzalloc(sizeof(*mite), GFP_KERNEL); + if (!mite) + return NULL; + + spin_lock_init(&mite->lock); + mite->pcidev = pcidev; + for (i = 0; i < MAX_MITE_DMA_CHANNELS; ++i) { + mite->channels[i].mite = mite; + mite->channels[i].channel = i; + mite->channels[i].done = 1; } - mmiowb(); - spin_unlock_irqrestore(&mite->lock, flags); - return status; + + ret = mite_setup(dev, mite, use_win1); + if (ret) { + if (mite->mmio) + iounmap(mite->mmio); + kfree(mite); + return NULL; + } + + return mite; } -EXPORT_SYMBOL_GPL(mite_get_status); +EXPORT_SYMBOL_GPL(mite_attach); -int mite_done(struct mite_channel *mite_chan) +/** + * mite_detach() - Unmap and free a MITE device for a comedi driver. + * @mite: MITE device. + * + * Called by a COMEDI drivers (*detach). + */ +void mite_detach(struct mite *mite) { - struct mite_struct *mite = mite_chan->mite; - unsigned long flags; - int done; + if (!mite) + return; - mite_get_status(mite_chan); - spin_lock_irqsave(&mite->lock, flags); - done = mite_chan->done; - spin_unlock_irqrestore(&mite->lock, flags); - return done; + if (mite->mmio) + iounmap(mite->mmio); + + kfree(mite); } -EXPORT_SYMBOL_GPL(mite_done); +EXPORT_SYMBOL_GPL(mite_detach); static int __init mite_module_init(void) { return 0; } +module_init(mite_module_init); static void __exit mite_module_exit(void) { } - -module_init(mite_module_init); module_exit(mite_module_exit); MODULE_AUTHOR("Comedi http://www.comedi.org"); diff --git a/drivers/staging/comedi/drivers/mite.h b/drivers/staging/comedi/drivers/mite.h index 87534b07ec81..b6349aed97d0 100644 --- a/drivers/staging/comedi/drivers/mite.h +++ b/drivers/staging/comedi/drivers/mite.h @@ -19,8 +19,6 @@ #ifndef _MITE_H_ #define _MITE_H_ -#include <linux/io.h> -#include <linux/log2.h> #include <linux/spinlock.h> #define MAX_MITE_DMA_CHANNELS 8 @@ -30,323 +28,74 @@ struct comedi_subdevice; struct device; struct pci_dev; -struct mite_dma_descriptor { +struct mite_dma_desc { __le32 count; __le32 addr; __le32 next; u32 dar; }; -struct mite_dma_descriptor_ring { +struct mite_ring { struct device *hw_dev; unsigned int n_links; - struct mite_dma_descriptor *descriptors; - dma_addr_t descriptors_dma_addr; + struct mite_dma_desc *descs; + dma_addr_t dma_addr; }; struct mite_channel { - struct mite_struct *mite; - unsigned channel; + struct mite *mite; + unsigned int channel; int dir; int done; - struct mite_dma_descriptor_ring *ring; + struct mite_ring *ring; }; -struct mite_struct { +struct mite { struct pci_dev *pcidev; - resource_size_t mite_phys_addr; - void __iomem *mite_io_addr; - resource_size_t daq_phys_addr; + void __iomem *mmio; struct mite_channel channels[MAX_MITE_DMA_CHANNELS]; - short channel_allocated[MAX_MITE_DMA_CHANNELS]; int num_channels; - unsigned fifo_size; + unsigned int fifo_size; + /* protects mite_channel from being released by the driver */ spinlock_t lock; }; -struct mite_struct *mite_alloc(struct pci_dev *pcidev); +u32 mite_bytes_in_transit(struct mite_channel *); -int mite_setup2(struct comedi_device *, struct mite_struct *, bool use_win1); +void mite_sync_dma(struct mite_channel *, struct comedi_subdevice *); +void mite_ack_linkc(struct mite_channel *, struct comedi_subdevice *s, + bool sync); +int mite_done(struct mite_channel *); -static inline int mite_setup(struct comedi_device *dev, - struct mite_struct *mite) -{ - return mite_setup2(dev, mite, false); -} +void mite_dma_arm(struct mite_channel *); +void mite_dma_disarm(struct mite_channel *); -void mite_detach(struct mite_struct *mite); -struct mite_dma_descriptor_ring *mite_alloc_ring(struct mite_struct *mite); -void mite_free_ring(struct mite_dma_descriptor_ring *ring); -struct mite_channel * -mite_request_channel_in_range(struct mite_struct *mite, - struct mite_dma_descriptor_ring *ring, - unsigned min_channel, unsigned max_channel); -static inline struct mite_channel * -mite_request_channel(struct mite_struct *mite, - struct mite_dma_descriptor_ring *ring) -{ - return mite_request_channel_in_range(mite, ring, 0, - mite->num_channels - 1); -} - -void mite_release_channel(struct mite_channel *mite_chan); - -unsigned mite_dma_tcr(struct mite_channel *mite_chan); -void mite_dma_arm(struct mite_channel *mite_chan); -void mite_dma_disarm(struct mite_channel *mite_chan); -int mite_sync_input_dma(struct mite_channel *mite_chan, - struct comedi_subdevice *s); -int mite_sync_output_dma(struct mite_channel *mite_chan, - struct comedi_subdevice *s); -u32 mite_bytes_written_to_memory_lb(struct mite_channel *mite_chan); -u32 mite_bytes_written_to_memory_ub(struct mite_channel *mite_chan); -u32 mite_bytes_read_from_memory_lb(struct mite_channel *mite_chan); -u32 mite_bytes_read_from_memory_ub(struct mite_channel *mite_chan); -u32 mite_bytes_in_transit(struct mite_channel *mite_chan); -unsigned mite_get_status(struct mite_channel *mite_chan); -int mite_done(struct mite_channel *mite_chan); - -void mite_prep_dma(struct mite_channel *mite_chan, +void mite_prep_dma(struct mite_channel *, unsigned int num_device_bits, unsigned int num_memory_bits); -int mite_buf_change(struct mite_dma_descriptor_ring *ring, - struct comedi_subdevice *s); -int mite_init_ring_descriptors(struct mite_dma_descriptor_ring *ring, - struct comedi_subdevice *s, - unsigned int nbytes); - -enum mite_registers { - /* - * The bits 0x90180700 in MITE_UNKNOWN_DMA_BURST_REG can be - * written and read back. The bits 0x1f always read as 1. - * The rest always read as zero. - */ - MITE_UNKNOWN_DMA_BURST_REG = 0x28, - MITE_IODWBSR = 0xc0, /* IO Device Window Base Size Register */ - MITE_IODWBSR_1 = 0xc4, /* IO Device Window Base Size Register 1 */ - MITE_IODWCR_1 = 0xf4, - MITE_PCI_CONFIG_OFFSET = 0x300, - MITE_CSIGR = 0x460 /* chip signature */ -}; - -#define MITE_CHAN(x) (0x500 + 0x100 * (x)) -#define MITE_CHOR(x) (0x00 + MITE_CHAN(x)) /* channel operation */ -#define MITE_CHCR(x) (0x04 + MITE_CHAN(x)) /* channel control */ -#define MITE_TCR(x) (0x08 + MITE_CHAN(x)) /* transfer count */ -#define MITE_MCR(x) (0x0c + MITE_CHAN(x)) /* memory configuration */ -#define MITE_MAR(x) (0x10 + MITE_CHAN(x)) /* memory address */ -#define MITE_DCR(x) (0x14 + MITE_CHAN(x)) /* device configuration */ -#define MITE_DAR(x) (0x18 + MITE_CHAN(x)) /* device address */ -#define MITE_LKCR(x) (0x1c + MITE_CHAN(x)) /* link configuration */ -#define MITE_LKAR(x) (0x20 + MITE_CHAN(x)) /* link address */ -#define MITE_LLKAR(x) (0x24 + MITE_CHAN(x)) /* see tnt5002 manual */ -#define MITE_BAR(x) (0x28 + MITE_CHAN(x)) /* base address */ -#define MITE_BCR(x) (0x2c + MITE_CHAN(x)) /* base count */ -#define MITE_SAR(x) (0x30 + MITE_CHAN(x)) /* ? address */ -#define MITE_WSCR(x) (0x34 + MITE_CHAN(x)) /* ? */ -#define MITE_WSER(x) (0x38 + MITE_CHAN(x)) /* ? */ -#define MITE_CHSR(x) (0x3c + MITE_CHAN(x)) /* channel status */ -#define MITE_FCR(x) (0x40 + MITE_CHAN(x)) /* fifo count */ - -enum MITE_IODWBSR_bits { - WENAB = 0x80, /* window enable */ -}; - -static inline unsigned MITE_IODWBSR_1_WSIZE_bits(unsigned size) -{ - unsigned order = 0; - - BUG_ON(size == 0); - order = ilog2(size); - BUG_ON(order < 1); - return (order - 1) & 0x1f; -} - -enum MITE_UNKNOWN_DMA_BURST_bits { - UNKNOWN_DMA_BURST_ENABLE_BITS = 0x600 -}; - -static inline int mite_csigr_version(u32 csigr_bits) -{ - return csigr_bits & 0xf; -}; - -static inline int mite_csigr_type(u32 csigr_bits) -{ /* original mite = 0, minimite = 1 */ - return (csigr_bits >> 4) & 0xf; -}; - -static inline int mite_csigr_mmode(u32 csigr_bits) -{ /* mite mode, minimite = 1 */ - return (csigr_bits >> 8) & 0x3; -}; - -static inline int mite_csigr_imode(u32 csigr_bits) -{ /* cpu port interface mode, pci = 0x3 */ - return (csigr_bits >> 12) & 0x3; -}; - -static inline int mite_csigr_dmac(u32 csigr_bits) -{ /* number of dma channels */ - return (csigr_bits >> 16) & 0xf; -}; -static inline int mite_csigr_wpdep(u32 csigr_bits) -{ /* write post fifo depth */ - unsigned int wpdep_bits = (csigr_bits >> 20) & 0x7; +struct mite_channel *mite_request_channel_in_range(struct mite *, + struct mite_ring *, + unsigned int min_channel, + unsigned int max_channel); +struct mite_channel *mite_request_channel(struct mite *, struct mite_ring *); +void mite_release_channel(struct mite_channel *); - return (wpdep_bits) ? (1 << (wpdep_bits - 1)) : 0; -} - -static inline int mite_csigr_wins(u32 csigr_bits) -{ - return (csigr_bits >> 24) & 0x1f; -}; - -static inline int mite_csigr_iowins(u32 csigr_bits) -{ /* number of io windows */ - return (csigr_bits >> 29) & 0x7; -}; - -enum MITE_MCR_bits { - MCRPON = 0, -}; - -enum MITE_DCR_bits { - DCR_NORMAL = (1 << 29), - DCRPON = 0, -}; - -enum MITE_CHOR_bits { - CHOR_DMARESET = (1 << 31), - CHOR_SET_SEND_TC = (1 << 11), - CHOR_CLR_SEND_TC = (1 << 10), - CHOR_SET_LPAUSE = (1 << 9), - CHOR_CLR_LPAUSE = (1 << 8), - CHOR_CLRDONE = (1 << 7), - CHOR_CLRRB = (1 << 6), - CHOR_CLRLC = (1 << 5), - CHOR_FRESET = (1 << 4), - CHOR_ABORT = (1 << 3), /* stop without emptying fifo */ - CHOR_STOP = (1 << 2), /* stop after emptying fifo */ - CHOR_CONT = (1 << 1), - CHOR_START = (1 << 0), - CHOR_PON = (CHOR_CLR_SEND_TC | CHOR_CLR_LPAUSE), -}; - -enum MITE_CHCR_bits { - CHCR_SET_DMA_IE = (1 << 31), - CHCR_CLR_DMA_IE = (1 << 30), - CHCR_SET_LINKP_IE = (1 << 29), - CHCR_CLR_LINKP_IE = (1 << 28), - CHCR_SET_SAR_IE = (1 << 27), - CHCR_CLR_SAR_IE = (1 << 26), - CHCR_SET_DONE_IE = (1 << 25), - CHCR_CLR_DONE_IE = (1 << 24), - CHCR_SET_MRDY_IE = (1 << 23), - CHCR_CLR_MRDY_IE = (1 << 22), - CHCR_SET_DRDY_IE = (1 << 21), - CHCR_CLR_DRDY_IE = (1 << 20), - CHCR_SET_LC_IE = (1 << 19), - CHCR_CLR_LC_IE = (1 << 18), - CHCR_SET_CONT_RB_IE = (1 << 17), - CHCR_CLR_CONT_RB_IE = (1 << 16), - CHCR_FIFODIS = (1 << 15), - CHCR_FIFO_ON = 0, - CHCR_BURSTEN = (1 << 14), - CHCR_NO_BURSTEN = 0, - CHCR_BYTE_SWAP_DEVICE = (1 << 6), - CHCR_BYTE_SWAP_MEMORY = (1 << 4), - CHCR_DIR = (1 << 3), - CHCR_DEV_TO_MEM = CHCR_DIR, - CHCR_MEM_TO_DEV = 0, - CHCR_NORMAL = (0 << 0), - CHCR_CONTINUE = (1 << 0), - CHCR_RINGBUFF = (2 << 0), - CHCR_LINKSHORT = (4 << 0), - CHCR_LINKLONG = (5 << 0), - CHCRPON = - (CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE | - CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE | - CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE), -}; - -enum ConfigRegister_bits { - CR_REQS_MASK = 0x7 << 16, - CR_ASEQDONT = 0x0 << 10, - CR_ASEQUP = 0x1 << 10, - CR_ASEQDOWN = 0x2 << 10, - CR_ASEQ_MASK = 0x3 << 10, - CR_PSIZE8 = (1 << 8), - CR_PSIZE16 = (2 << 8), - CR_PSIZE32 = (3 << 8), - CR_PORTCPU = (0 << 6), - CR_PORTIO = (1 << 6), - CR_PORTVXI = (2 << 6), - CR_PORTMXI = (3 << 6), - CR_AMDEVICE = (1 << 0), -}; - -static inline int CR_REQS(int source) -{ - return (source & 0x7) << 16; -}; - -static inline int CR_REQSDRQ(unsigned drq_line) -{ - /* This also works on m-series when using channels (drq_line) 4 or 5. */ - return CR_REQS((drq_line & 0x3) | 0x4); -} - -static inline int CR_RL(unsigned int retry_limit) -{ - int value = 0; +int mite_init_ring_descriptors(struct mite_ring *, struct comedi_subdevice *, + unsigned int nbytes); +int mite_buf_change(struct mite_ring *, struct comedi_subdevice *); - if (retry_limit) - value = 1 + ilog2(retry_limit); - if (value > 0x7) - value = 0x7; - return (value & 0x7) << 21; -} +struct mite_ring *mite_alloc_ring(struct mite *); +void mite_free_ring(struct mite_ring *); -enum CHSR_bits { - CHSR_INT = (1 << 31), - CHSR_LPAUSES = (1 << 29), - CHSR_SARS = (1 << 27), - CHSR_DONE = (1 << 25), - CHSR_MRDY = (1 << 23), - CHSR_DRDY = (1 << 21), - CHSR_LINKC = (1 << 19), - CHSR_CONTS_RB = (1 << 17), - CHSR_ERROR = (1 << 15), - CHSR_SABORT = (1 << 14), - CHSR_HABORT = (1 << 13), - CHSR_STOPS = (1 << 12), - CHSR_OPERR_mask = (3 << 10), - CHSR_OPERR_NOERROR = (0 << 10), - CHSR_OPERR_FIFOERROR = (1 << 10), - CHSR_OPERR_LINKERROR = (1 << 10), /* ??? */ - CHSR_XFERR = (1 << 9), - CHSR_END = (1 << 8), - CHSR_DRQ1 = (1 << 7), - CHSR_DRQ0 = (1 << 6), - CHSR_LxERR_mask = (3 << 4), - CHSR_LBERR = (1 << 4), - CHSR_LRERR = (2 << 4), - CHSR_LOERR = (3 << 4), - CHSR_MxERR_mask = (3 << 2), - CHSR_MBERR = (1 << 2), - CHSR_MRERR = (2 << 2), - CHSR_MOERR = (3 << 2), - CHSR_DxERR_mask = (3 << 0), - CHSR_DBERR = (1 << 0), - CHSR_DRERR = (2 << 0), - CHSR_DOERR = (3 << 0), -}; +struct mite *mite_attach(struct comedi_device *, bool use_win1); +void mite_detach(struct mite *); -static inline void mite_dma_reset(struct mite_channel *mite_chan) -{ - writel(CHOR_DMARESET | CHOR_FRESET, - mite_chan->mite->mite_io_addr + MITE_CHOR(mite_chan->channel)); -}; +/* + * Mite registers (used outside of the mite driver) + */ +#define MITE_IODWBSR 0xc0 /* IO Device Window Base Size */ +#define MITE_IODWBSR_1 0xc4 /* IO Device Window1 Base Size */ +#define WENAB BIT(7) /* window enable */ +#define MITE_IODWCR_1 0xf4 #endif diff --git a/drivers/staging/comedi/drivers/ni_660x.c b/drivers/staging/comedi/drivers/ni_660x.c index 46647c64f369..0dcb826a9f1f 100644 --- a/drivers/staging/comedi/drivers/ni_660x.c +++ b/drivers/staging/comedi/drivers/ni_660x.c @@ -1,17 +1,16 @@ /* - comedi/drivers/ni_660x.c - Hardware driver for NI 660x devices - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*/ + * Hardware driver for NI 660x devices + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ /* * Driver: ni_660x @@ -42,91 +41,13 @@ #include "mite.h" #include "ni_tio.h" -enum ni_660x_constants { - min_counter_pfi_chan = 8, - max_dio_pfi_chan = 31, - counters_per_chip = 4 -}; - -#define NUM_PFI_CHANNELS 40 -/* really there are only up to 3 dma channels, but the register layout allows -for 4 */ -#define MAX_DMA_CHANNEL 4 - /* See Register-Level Programmer Manual page 3.1 */ enum ni_660x_register { - NI660X_G0_INT_ACK, - NI660X_G0_STATUS, - NI660X_G1_INT_ACK, - NI660X_G1_STATUS, - NI660X_G01_STATUS, - NI660X_G0_CMD, - NI660X_STC_DIO_PARALLEL_INPUT, - NI660X_G1_CMD, - NI660X_G0_HW_SAVE, - NI660X_G1_HW_SAVE, + /* see enum ni_gpct_register */ + NI660X_STC_DIO_PARALLEL_INPUT = NITIO_NUM_REGS, NI660X_STC_DIO_OUTPUT, NI660X_STC_DIO_CONTROL, - NI660X_G0_SW_SAVE, - NI660X_G1_SW_SAVE, - NI660X_G0_MODE, - NI660X_G01_STATUS1, - NI660X_G1_MODE, NI660X_STC_DIO_SERIAL_INPUT, - NI660X_G0_LOADA, - NI660X_G01_STATUS2, - NI660X_G0_LOADB, - NI660X_G1_LOADA, - NI660X_G1_LOADB, - NI660X_G0_INPUT_SEL, - NI660X_G1_INPUT_SEL, - NI660X_G0_AUTO_INC, - NI660X_G1_AUTO_INC, - NI660X_G01_RESET, - NI660X_G0_INT_ENA, - NI660X_G1_INT_ENA, - NI660X_G0_CNT_MODE, - NI660X_G1_CNT_MODE, - NI660X_G0_GATE2, - NI660X_G1_GATE2, - NI660X_G0_DMA_CFG, - NI660X_G0_DMA_STATUS, - NI660X_G1_DMA_CFG, - NI660X_G1_DMA_STATUS, - NI660X_G2_INT_ACK, - NI660X_G2_STATUS, - NI660X_G3_INT_ACK, - NI660X_G3_STATUS, - NI660X_G23_STATUS, - NI660X_G2_CMD, - NI660X_G3_CMD, - NI660X_G2_HW_SAVE, - NI660X_G3_HW_SAVE, - NI660X_G2_SW_SAVE, - NI660X_G3_SW_SAVE, - NI660X_G2_MODE, - NI660X_G23_STATUS1, - NI660X_G3_MODE, - NI660X_G2_LOADA, - NI660X_G23_STATUS2, - NI660X_G2_LOADB, - NI660X_G3_LOADA, - NI660X_G3_LOADB, - NI660X_G2_INPUT_SEL, - NI660X_G3_INPUT_SEL, - NI660X_G2_AUTO_INC, - NI660X_G3_AUTO_INC, - NI660X_G23_RESET, - NI660X_G2_INT_ENA, - NI660X_G3_INT_ENA, - NI660X_G2_CNT_MODE, - NI660X_G3_CNT_MODE, - NI660X_G3_GATE2, - NI660X_G2_GATE2, - NI660X_G2_DMA_CFG, - NI660X_G2_DMA_STATUS, - NI660X_G3_DMA_CFG, - NI660X_G3_DMA_STATUS, NI660X_DIO32_INPUT, NI660X_DIO32_OUTPUT, NI660X_CLK_CFG, @@ -156,224 +77,134 @@ enum ni_660x_register { NI660X_NUM_REGS, }; -static inline unsigned IOConfigReg(unsigned pfi_channel) -{ - unsigned reg = NI660X_IO_CFG_0_1 + pfi_channel / 2; - - BUG_ON(reg > NI660X_IO_CFG_38_39); - return reg; -} - -enum ni_660x_register_width { - DATA_1B, - DATA_2B, - DATA_4B -}; +#define NI660X_CLK_CFG_COUNTER_SWAP BIT(21) -enum ni_660x_register_direction { - NI_660x_READ, - NI_660x_WRITE, - NI_660x_READ_WRITE -}; +#define NI660X_GLOBAL_INT_COUNTER0 BIT(8) +#define NI660X_GLOBAL_INT_COUNTER1 BIT(9) +#define NI660X_GLOBAL_INT_COUNTER2 BIT(10) +#define NI660X_GLOBAL_INT_COUNTER3 BIT(11) +#define NI660X_GLOBAL_INT_CASCADE BIT(29) +#define NI660X_GLOBAL_INT_GLOBAL_POL BIT(30) +#define NI660X_GLOBAL_INT_GLOBAL BIT(31) -enum ni_660x_pfi_output_select { - pfi_output_select_high_Z = 0, - pfi_output_select_counter = 1, - pfi_output_select_do = 2, - num_pfi_output_selects -}; +#define NI660X_DMA_CFG_SEL(_c, _s) (((_s) & 0x1f) << (8 * (_c))) +#define NI660X_DMA_CFG_SEL_MASK(_c) NI660X_DMA_CFG_SEL((_c), 0x1f) +#define NI660X_DMA_CFG_SEL_NONE(_c) NI660X_DMA_CFG_SEL((_c), 0x1f) +#define NI660X_DMA_CFG_RESET(_c) NI660X_DMA_CFG_SEL((_c), 0x80) -enum ni_660x_subdevices { - NI_660X_DIO_SUBDEV = 1, - NI_660X_GPCT_SUBDEV_0 = 2 -}; -static inline unsigned NI_660X_GPCT_SUBDEV(unsigned index) -{ - return NI_660X_GPCT_SUBDEV_0 + index; -} +#define NI660X_IO_CFG(x) (NI660X_IO_CFG_0_1 + ((x) / 2)) +#define NI660X_IO_CFG_OUT_SEL(_c, _s) (((_s) & 0x3) << (((_c) % 2) ? 0 : 8)) +#define NI660X_IO_CFG_OUT_SEL_MASK(_c) NI660X_IO_CFG_OUT_SEL((_c), 0x3) +#define NI660X_IO_CFG_IN_SEL(_c, _s) (((_s) & 0x7) << (((_c) % 2) ? 4 : 12)) +#define NI660X_IO_CFG_IN_SEL_MASK(_c) NI660X_IO_CFG_IN_SEL((_c), 0x7) -struct NI_660xRegisterData { - const char *name; /* Register Name */ +struct ni_660x_register_data { int offset; /* Offset from base address from GPCT chip */ - enum ni_660x_register_direction direction; - enum ni_660x_register_width size; /* 1 byte, 2 bytes, or 4 bytes */ -}; - -static const struct NI_660xRegisterData registerData[NI660X_NUM_REGS] = { - {"G0 Interrupt Acknowledge", 0x004, NI_660x_WRITE, DATA_2B}, - {"G0 Status Register", 0x004, NI_660x_READ, DATA_2B}, - {"G1 Interrupt Acknowledge", 0x006, NI_660x_WRITE, DATA_2B}, - {"G1 Status Register", 0x006, NI_660x_READ, DATA_2B}, - {"G01 Status Register ", 0x008, NI_660x_READ, DATA_2B}, - {"G0 Command Register", 0x00C, NI_660x_WRITE, DATA_2B}, - {"STC DIO Parallel Input", 0x00E, NI_660x_READ, DATA_2B}, - {"G1 Command Register", 0x00E, NI_660x_WRITE, DATA_2B}, - {"G0 HW Save Register", 0x010, NI_660x_READ, DATA_4B}, - {"G1 HW Save Register", 0x014, NI_660x_READ, DATA_4B}, - {"STC DIO Output", 0x014, NI_660x_WRITE, DATA_2B}, - {"STC DIO Control", 0x016, NI_660x_WRITE, DATA_2B}, - {"G0 SW Save Register", 0x018, NI_660x_READ, DATA_4B}, - {"G1 SW Save Register", 0x01C, NI_660x_READ, DATA_4B}, - {"G0 Mode Register", 0x034, NI_660x_WRITE, DATA_2B}, - {"G01 Joint Status 1 Register", 0x036, NI_660x_READ, DATA_2B}, - {"G1 Mode Register", 0x036, NI_660x_WRITE, DATA_2B}, - {"STC DIO Serial Input", 0x038, NI_660x_READ, DATA_2B}, - {"G0 Load A Register", 0x038, NI_660x_WRITE, DATA_4B}, - {"G01 Joint Status 2 Register", 0x03A, NI_660x_READ, DATA_2B}, - {"G0 Load B Register", 0x03C, NI_660x_WRITE, DATA_4B}, - {"G1 Load A Register", 0x040, NI_660x_WRITE, DATA_4B}, - {"G1 Load B Register", 0x044, NI_660x_WRITE, DATA_4B}, - {"G0 Input Select Register", 0x048, NI_660x_WRITE, DATA_2B}, - {"G1 Input Select Register", 0x04A, NI_660x_WRITE, DATA_2B}, - {"G0 Autoincrement Register", 0x088, NI_660x_WRITE, DATA_2B}, - {"G1 Autoincrement Register", 0x08A, NI_660x_WRITE, DATA_2B}, - {"G01 Joint Reset Register", 0x090, NI_660x_WRITE, DATA_2B}, - {"G0 Interrupt Enable", 0x092, NI_660x_WRITE, DATA_2B}, - {"G1 Interrupt Enable", 0x096, NI_660x_WRITE, DATA_2B}, - {"G0 Counting Mode Register", 0x0B0, NI_660x_WRITE, DATA_2B}, - {"G1 Counting Mode Register", 0x0B2, NI_660x_WRITE, DATA_2B}, - {"G0 Second Gate Register", 0x0B4, NI_660x_WRITE, DATA_2B}, - {"G1 Second Gate Register", 0x0B6, NI_660x_WRITE, DATA_2B}, - {"G0 DMA Config Register", 0x0B8, NI_660x_WRITE, DATA_2B}, - {"G0 DMA Status Register", 0x0B8, NI_660x_READ, DATA_2B}, - {"G1 DMA Config Register", 0x0BA, NI_660x_WRITE, DATA_2B}, - {"G1 DMA Status Register", 0x0BA, NI_660x_READ, DATA_2B}, - {"G2 Interrupt Acknowledge", 0x104, NI_660x_WRITE, DATA_2B}, - {"G2 Status Register", 0x104, NI_660x_READ, DATA_2B}, - {"G3 Interrupt Acknowledge", 0x106, NI_660x_WRITE, DATA_2B}, - {"G3 Status Register", 0x106, NI_660x_READ, DATA_2B}, - {"G23 Status Register", 0x108, NI_660x_READ, DATA_2B}, - {"G2 Command Register", 0x10C, NI_660x_WRITE, DATA_2B}, - {"G3 Command Register", 0x10E, NI_660x_WRITE, DATA_2B}, - {"G2 HW Save Register", 0x110, NI_660x_READ, DATA_4B}, - {"G3 HW Save Register", 0x114, NI_660x_READ, DATA_4B}, - {"G2 SW Save Register", 0x118, NI_660x_READ, DATA_4B}, - {"G3 SW Save Register", 0x11C, NI_660x_READ, DATA_4B}, - {"G2 Mode Register", 0x134, NI_660x_WRITE, DATA_2B}, - {"G23 Joint Status 1 Register", 0x136, NI_660x_READ, DATA_2B}, - {"G3 Mode Register", 0x136, NI_660x_WRITE, DATA_2B}, - {"G2 Load A Register", 0x138, NI_660x_WRITE, DATA_4B}, - {"G23 Joint Status 2 Register", 0x13A, NI_660x_READ, DATA_2B}, - {"G2 Load B Register", 0x13C, NI_660x_WRITE, DATA_4B}, - {"G3 Load A Register", 0x140, NI_660x_WRITE, DATA_4B}, - {"G3 Load B Register", 0x144, NI_660x_WRITE, DATA_4B}, - {"G2 Input Select Register", 0x148, NI_660x_WRITE, DATA_2B}, - {"G3 Input Select Register", 0x14A, NI_660x_WRITE, DATA_2B}, - {"G2 Autoincrement Register", 0x188, NI_660x_WRITE, DATA_2B}, - {"G3 Autoincrement Register", 0x18A, NI_660x_WRITE, DATA_2B}, - {"G23 Joint Reset Register", 0x190, NI_660x_WRITE, DATA_2B}, - {"G2 Interrupt Enable", 0x192, NI_660x_WRITE, DATA_2B}, - {"G3 Interrupt Enable", 0x196, NI_660x_WRITE, DATA_2B}, - {"G2 Counting Mode Register", 0x1B0, NI_660x_WRITE, DATA_2B}, - {"G3 Counting Mode Register", 0x1B2, NI_660x_WRITE, DATA_2B}, - {"G3 Second Gate Register", 0x1B6, NI_660x_WRITE, DATA_2B}, - {"G2 Second Gate Register", 0x1B4, NI_660x_WRITE, DATA_2B}, - {"G2 DMA Config Register", 0x1B8, NI_660x_WRITE, DATA_2B}, - {"G2 DMA Status Register", 0x1B8, NI_660x_READ, DATA_2B}, - {"G3 DMA Config Register", 0x1BA, NI_660x_WRITE, DATA_2B}, - {"G3 DMA Status Register", 0x1BA, NI_660x_READ, DATA_2B}, - {"32 bit Digital Input", 0x414, NI_660x_READ, DATA_4B}, - {"32 bit Digital Output", 0x510, NI_660x_WRITE, DATA_4B}, - {"Clock Config Register", 0x73C, NI_660x_WRITE, DATA_4B}, - {"Global Interrupt Status Register", 0x754, NI_660x_READ, DATA_4B}, - {"DMA Configuration Register", 0x76C, NI_660x_WRITE, DATA_4B}, - {"Global Interrupt Config Register", 0x770, NI_660x_WRITE, DATA_4B}, - {"IO Config Register 0-1", 0x77C, NI_660x_READ_WRITE, DATA_2B}, - {"IO Config Register 2-3", 0x77E, NI_660x_READ_WRITE, DATA_2B}, - {"IO Config Register 4-5", 0x780, NI_660x_READ_WRITE, DATA_2B}, - {"IO Config Register 6-7", 0x782, NI_660x_READ_WRITE, DATA_2B}, - {"IO Config Register 8-9", 0x784, NI_660x_READ_WRITE, DATA_2B}, - {"IO Config Register 10-11", 0x786, NI_660x_READ_WRITE, DATA_2B}, - {"IO Config Register 12-13", 0x788, NI_660x_READ_WRITE, DATA_2B}, - {"IO Config Register 14-15", 0x78A, NI_660x_READ_WRITE, DATA_2B}, - {"IO Config Register 16-17", 0x78C, NI_660x_READ_WRITE, DATA_2B}, - {"IO Config Register 18-19", 0x78E, NI_660x_READ_WRITE, DATA_2B}, - {"IO Config Register 20-21", 0x790, NI_660x_READ_WRITE, DATA_2B}, - {"IO Config Register 22-23", 0x792, NI_660x_READ_WRITE, DATA_2B}, - {"IO Config Register 24-25", 0x794, NI_660x_READ_WRITE, DATA_2B}, - {"IO Config Register 26-27", 0x796, NI_660x_READ_WRITE, DATA_2B}, - {"IO Config Register 28-29", 0x798, NI_660x_READ_WRITE, DATA_2B}, - {"IO Config Register 30-31", 0x79A, NI_660x_READ_WRITE, DATA_2B}, - {"IO Config Register 32-33", 0x79C, NI_660x_READ_WRITE, DATA_2B}, - {"IO Config Register 34-35", 0x79E, NI_660x_READ_WRITE, DATA_2B}, - {"IO Config Register 36-37", 0x7A0, NI_660x_READ_WRITE, DATA_2B}, - {"IO Config Register 38-39", 0x7A2, NI_660x_READ_WRITE, DATA_2B} -}; - -/* kind of ENABLE for the second counter */ -enum clock_config_register_bits { - CounterSwap = 0x1 << 21 -}; - -/* ioconfigreg */ -static inline unsigned ioconfig_bitshift(unsigned pfi_channel) -{ - return (pfi_channel % 2) ? 0 : 8; -} - -static inline unsigned pfi_output_select_mask(unsigned pfi_channel) -{ - return 0x3 << ioconfig_bitshift(pfi_channel); -} - -static inline unsigned pfi_output_select_bits(unsigned pfi_channel, - unsigned output_select) -{ - return (output_select & 0x3) << ioconfig_bitshift(pfi_channel); -} - -static inline unsigned pfi_input_select_mask(unsigned pfi_channel) -{ - return 0x7 << (4 + ioconfig_bitshift(pfi_channel)); -} - -static inline unsigned pfi_input_select_bits(unsigned pfi_channel, - unsigned input_select) -{ - return (input_select & 0x7) << (4 + ioconfig_bitshift(pfi_channel)); -} - -/* dma configuration register bits */ -static inline unsigned dma_select_mask(unsigned dma_channel) -{ - BUG_ON(dma_channel >= MAX_DMA_CHANNEL); - return 0x1f << (8 * dma_channel); -} - -enum dma_selection { - dma_selection_none = 0x1f, -}; - -static inline unsigned dma_select_bits(unsigned dma_channel, unsigned selection) -{ - BUG_ON(dma_channel >= MAX_DMA_CHANNEL); - return (selection << (8 * dma_channel)) & dma_select_mask(dma_channel); -} - -static inline unsigned dma_reset_bit(unsigned dma_channel) -{ - BUG_ON(dma_channel >= MAX_DMA_CHANNEL); - return 0x80 << (8 * dma_channel); -} - -enum global_interrupt_status_register_bits { - Counter_0_Int_Bit = 0x100, - Counter_1_Int_Bit = 0x200, - Counter_2_Int_Bit = 0x400, - Counter_3_Int_Bit = 0x800, - Cascade_Int_Bit = 0x20000000, - Global_Int_Bit = 0x80000000 + char size; /* 2 or 4 bytes */ }; -enum global_interrupt_config_register_bits { - Cascade_Int_Enable_Bit = 0x20000000, - Global_Int_Polarity_Bit = 0x40000000, - Global_Int_Enable_Bit = 0x80000000 +static const struct ni_660x_register_data ni_660x_reg_data[NI660X_NUM_REGS] = { + [NITIO_G0_INT_ACK] = { 0x004, 2 }, /* write */ + [NITIO_G0_STATUS] = { 0x004, 2 }, /* read */ + [NITIO_G1_INT_ACK] = { 0x006, 2 }, /* write */ + [NITIO_G1_STATUS] = { 0x006, 2 }, /* read */ + [NITIO_G01_STATUS] = { 0x008, 2 }, /* read */ + [NITIO_G0_CMD] = { 0x00c, 2 }, /* write */ + [NI660X_STC_DIO_PARALLEL_INPUT] = { 0x00e, 2 }, /* read */ + [NITIO_G1_CMD] = { 0x00e, 2 }, /* write */ + [NITIO_G0_HW_SAVE] = { 0x010, 4 }, /* read */ + [NITIO_G1_HW_SAVE] = { 0x014, 4 }, /* read */ + [NI660X_STC_DIO_OUTPUT] = { 0x014, 2 }, /* write */ + [NI660X_STC_DIO_CONTROL] = { 0x016, 2 }, /* write */ + [NITIO_G0_SW_SAVE] = { 0x018, 4 }, /* read */ + [NITIO_G1_SW_SAVE] = { 0x01c, 4 }, /* read */ + [NITIO_G0_MODE] = { 0x034, 2 }, /* write */ + [NITIO_G01_STATUS1] = { 0x036, 2 }, /* read */ + [NITIO_G1_MODE] = { 0x036, 2 }, /* write */ + [NI660X_STC_DIO_SERIAL_INPUT] = { 0x038, 2 }, /* read */ + [NITIO_G0_LOADA] = { 0x038, 4 }, /* write */ + [NITIO_G01_STATUS2] = { 0x03a, 2 }, /* read */ + [NITIO_G0_LOADB] = { 0x03c, 4 }, /* write */ + [NITIO_G1_LOADA] = { 0x040, 4 }, /* write */ + [NITIO_G1_LOADB] = { 0x044, 4 }, /* write */ + [NITIO_G0_INPUT_SEL] = { 0x048, 2 }, /* write */ + [NITIO_G1_INPUT_SEL] = { 0x04a, 2 }, /* write */ + [NITIO_G0_AUTO_INC] = { 0x088, 2 }, /* write */ + [NITIO_G1_AUTO_INC] = { 0x08a, 2 }, /* write */ + [NITIO_G01_RESET] = { 0x090, 2 }, /* write */ + [NITIO_G0_INT_ENA] = { 0x092, 2 }, /* write */ + [NITIO_G1_INT_ENA] = { 0x096, 2 }, /* write */ + [NITIO_G0_CNT_MODE] = { 0x0b0, 2 }, /* write */ + [NITIO_G1_CNT_MODE] = { 0x0b2, 2 }, /* write */ + [NITIO_G0_GATE2] = { 0x0b4, 2 }, /* write */ + [NITIO_G1_GATE2] = { 0x0b6, 2 }, /* write */ + [NITIO_G0_DMA_CFG] = { 0x0b8, 2 }, /* write */ + [NITIO_G0_DMA_STATUS] = { 0x0b8, 2 }, /* read */ + [NITIO_G1_DMA_CFG] = { 0x0ba, 2 }, /* write */ + [NITIO_G1_DMA_STATUS] = { 0x0ba, 2 }, /* read */ + [NITIO_G2_INT_ACK] = { 0x104, 2 }, /* write */ + [NITIO_G2_STATUS] = { 0x104, 2 }, /* read */ + [NITIO_G3_INT_ACK] = { 0x106, 2 }, /* write */ + [NITIO_G3_STATUS] = { 0x106, 2 }, /* read */ + [NITIO_G23_STATUS] = { 0x108, 2 }, /* read */ + [NITIO_G2_CMD] = { 0x10c, 2 }, /* write */ + [NITIO_G3_CMD] = { 0x10e, 2 }, /* write */ + [NITIO_G2_HW_SAVE] = { 0x110, 4 }, /* read */ + [NITIO_G3_HW_SAVE] = { 0x114, 4 }, /* read */ + [NITIO_G2_SW_SAVE] = { 0x118, 4 }, /* read */ + [NITIO_G3_SW_SAVE] = { 0x11c, 4 }, /* read */ + [NITIO_G2_MODE] = { 0x134, 2 }, /* write */ + [NITIO_G23_STATUS1] = { 0x136, 2 }, /* read */ + [NITIO_G3_MODE] = { 0x136, 2 }, /* write */ + [NITIO_G2_LOADA] = { 0x138, 4 }, /* write */ + [NITIO_G23_STATUS2] = { 0x13a, 2 }, /* read */ + [NITIO_G2_LOADB] = { 0x13c, 4 }, /* write */ + [NITIO_G3_LOADA] = { 0x140, 4 }, /* write */ + [NITIO_G3_LOADB] = { 0x144, 4 }, /* write */ + [NITIO_G2_INPUT_SEL] = { 0x148, 2 }, /* write */ + [NITIO_G3_INPUT_SEL] = { 0x14a, 2 }, /* write */ + [NITIO_G2_AUTO_INC] = { 0x188, 2 }, /* write */ + [NITIO_G3_AUTO_INC] = { 0x18a, 2 }, /* write */ + [NITIO_G23_RESET] = { 0x190, 2 }, /* write */ + [NITIO_G2_INT_ENA] = { 0x192, 2 }, /* write */ + [NITIO_G3_INT_ENA] = { 0x196, 2 }, /* write */ + [NITIO_G2_CNT_MODE] = { 0x1b0, 2 }, /* write */ + [NITIO_G3_CNT_MODE] = { 0x1b2, 2 }, /* write */ + [NITIO_G2_GATE2] = { 0x1b4, 2 }, /* write */ + [NITIO_G3_GATE2] = { 0x1b6, 2 }, /* write */ + [NITIO_G2_DMA_CFG] = { 0x1b8, 2 }, /* write */ + [NITIO_G2_DMA_STATUS] = { 0x1b8, 2 }, /* read */ + [NITIO_G3_DMA_CFG] = { 0x1ba, 2 }, /* write */ + [NITIO_G3_DMA_STATUS] = { 0x1ba, 2 }, /* read */ + [NI660X_DIO32_INPUT] = { 0x414, 4 }, /* read */ + [NI660X_DIO32_OUTPUT] = { 0x510, 4 }, /* write */ + [NI660X_CLK_CFG] = { 0x73c, 4 }, /* write */ + [NI660X_GLOBAL_INT_STATUS] = { 0x754, 4 }, /* read */ + [NI660X_DMA_CFG] = { 0x76c, 4 }, /* write */ + [NI660X_GLOBAL_INT_CFG] = { 0x770, 4 }, /* write */ + [NI660X_IO_CFG_0_1] = { 0x77c, 2 }, /* read/write */ + [NI660X_IO_CFG_2_3] = { 0x77e, 2 }, /* read/write */ + [NI660X_IO_CFG_4_5] = { 0x780, 2 }, /* read/write */ + [NI660X_IO_CFG_6_7] = { 0x782, 2 }, /* read/write */ + [NI660X_IO_CFG_8_9] = { 0x784, 2 }, /* read/write */ + [NI660X_IO_CFG_10_11] = { 0x786, 2 }, /* read/write */ + [NI660X_IO_CFG_12_13] = { 0x788, 2 }, /* read/write */ + [NI660X_IO_CFG_14_15] = { 0x78a, 2 }, /* read/write */ + [NI660X_IO_CFG_16_17] = { 0x78c, 2 }, /* read/write */ + [NI660X_IO_CFG_18_19] = { 0x78e, 2 }, /* read/write */ + [NI660X_IO_CFG_20_21] = { 0x790, 2 }, /* read/write */ + [NI660X_IO_CFG_22_23] = { 0x792, 2 }, /* read/write */ + [NI660X_IO_CFG_24_25] = { 0x794, 2 }, /* read/write */ + [NI660X_IO_CFG_26_27] = { 0x796, 2 }, /* read/write */ + [NI660X_IO_CFG_28_29] = { 0x798, 2 }, /* read/write */ + [NI660X_IO_CFG_30_31] = { 0x79a, 2 }, /* read/write */ + [NI660X_IO_CFG_32_33] = { 0x79c, 2 }, /* read/write */ + [NI660X_IO_CFG_34_35] = { 0x79e, 2 }, /* read/write */ + [NI660X_IO_CFG_36_37] = { 0x7a0, 2 }, /* read/write */ + [NI660X_IO_CFG_38_39] = { 0x7a2, 2 } /* read/write */ }; -/* Offset of the GPCT chips from the base-address of the card */ -/* First chip is at base-address + 0x00, etc. */ -static const unsigned GPCT_OFFSET[2] = { 0x0, 0x800 }; +#define NI660X_CHIP_OFFSET 0x800 enum ni_660x_boardid { BOARD_PCI6601, @@ -385,7 +216,7 @@ enum ni_660x_boardid { struct ni_660x_board { const char *name; - unsigned n_chips; /* total number of TIO chips */ + unsigned int n_chips; /* total number of TIO chips */ }; static const struct ni_660x_board ni_660x_boards[] = { @@ -411,280 +242,95 @@ static const struct ni_660x_board ni_660x_boards[] = { }, }; -#define NI_660X_MAX_NUM_CHIPS 2 -#define NI_660X_MAX_NUM_COUNTERS (NI_660X_MAX_NUM_CHIPS * counters_per_chip) +#define NI660X_NUM_PFI_CHANNELS 40 + +/* there are only up to 3 dma channels, but the register layout allows for 4 */ +#define NI660X_MAX_DMA_CHANNEL 4 + +#define NI660X_COUNTERS_PER_CHIP 4 +#define NI660X_MAX_CHIPS 2 +#define NI660X_MAX_COUNTERS (NI660X_MAX_CHIPS * \ + NI660X_COUNTERS_PER_CHIP) struct ni_660x_private { - struct mite_struct *mite; + struct mite *mite; struct ni_gpct_device *counter_dev; - uint64_t pfi_direction_bits; - struct mite_dma_descriptor_ring - *mite_rings[NI_660X_MAX_NUM_CHIPS][counters_per_chip]; + struct mite_ring *ring[NI660X_MAX_CHIPS][NI660X_COUNTERS_PER_CHIP]; + /* protects mite channel request/release */ spinlock_t mite_channel_lock; - /* interrupt_lock prevents races between interrupt and comedi_poll */ + /* prevents races between interrupt and comedi_poll */ spinlock_t interrupt_lock; - unsigned dma_configuration_soft_copies[NI_660X_MAX_NUM_CHIPS]; - spinlock_t soft_reg_copy_lock; - unsigned short pfi_output_selects[NUM_PFI_CHANNELS]; + unsigned int dma_cfg[NI660X_MAX_CHIPS]; + unsigned int io_cfg[NI660X_NUM_PFI_CHANNELS]; + u64 io_dir; }; -static inline unsigned ni_660x_num_counters(struct comedi_device *dev) -{ - const struct ni_660x_board *board = dev->board_ptr; - - return board->n_chips * counters_per_chip; -} - -static enum ni_660x_register ni_gpct_to_660x_register(enum ni_gpct_register reg) -{ - switch (reg) { - case NITIO_G0_AUTO_INC: - return NI660X_G0_AUTO_INC; - case NITIO_G1_AUTO_INC: - return NI660X_G1_AUTO_INC; - case NITIO_G2_AUTO_INC: - return NI660X_G2_AUTO_INC; - case NITIO_G3_AUTO_INC: - return NI660X_G3_AUTO_INC; - case NITIO_G0_CMD: - return NI660X_G0_CMD; - case NITIO_G1_CMD: - return NI660X_G1_CMD; - case NITIO_G2_CMD: - return NI660X_G2_CMD; - case NITIO_G3_CMD: - return NI660X_G3_CMD; - case NITIO_G0_HW_SAVE: - return NI660X_G0_HW_SAVE; - case NITIO_G1_HW_SAVE: - return NI660X_G1_HW_SAVE; - case NITIO_G2_HW_SAVE: - return NI660X_G2_HW_SAVE; - case NITIO_G3_HW_SAVE: - return NI660X_G3_HW_SAVE; - case NITIO_G0_SW_SAVE: - return NI660X_G0_SW_SAVE; - case NITIO_G1_SW_SAVE: - return NI660X_G1_SW_SAVE; - case NITIO_G2_SW_SAVE: - return NI660X_G2_SW_SAVE; - case NITIO_G3_SW_SAVE: - return NI660X_G3_SW_SAVE; - case NITIO_G0_MODE: - return NI660X_G0_MODE; - case NITIO_G1_MODE: - return NI660X_G1_MODE; - case NITIO_G2_MODE: - return NI660X_G2_MODE; - case NITIO_G3_MODE: - return NI660X_G3_MODE; - case NITIO_G0_LOADA: - return NI660X_G0_LOADA; - case NITIO_G1_LOADA: - return NI660X_G1_LOADA; - case NITIO_G2_LOADA: - return NI660X_G2_LOADA; - case NITIO_G3_LOADA: - return NI660X_G3_LOADA; - case NITIO_G0_LOADB: - return NI660X_G0_LOADB; - case NITIO_G1_LOADB: - return NI660X_G1_LOADB; - case NITIO_G2_LOADB: - return NI660X_G2_LOADB; - case NITIO_G3_LOADB: - return NI660X_G3_LOADB; - case NITIO_G0_INPUT_SEL: - return NI660X_G0_INPUT_SEL; - case NITIO_G1_INPUT_SEL: - return NI660X_G1_INPUT_SEL; - case NITIO_G2_INPUT_SEL: - return NI660X_G2_INPUT_SEL; - case NITIO_G3_INPUT_SEL: - return NI660X_G3_INPUT_SEL; - case NITIO_G01_STATUS: - return NI660X_G01_STATUS; - case NITIO_G23_STATUS: - return NI660X_G23_STATUS; - case NITIO_G01_RESET: - return NI660X_G01_RESET; - case NITIO_G23_RESET: - return NI660X_G23_RESET; - case NITIO_G01_STATUS1: - return NI660X_G01_STATUS1; - case NITIO_G23_STATUS1: - return NI660X_G23_STATUS1; - case NITIO_G01_STATUS2: - return NI660X_G01_STATUS2; - case NITIO_G23_STATUS2: - return NI660X_G23_STATUS2; - case NITIO_G0_CNT_MODE: - return NI660X_G0_CNT_MODE; - case NITIO_G1_CNT_MODE: - return NI660X_G1_CNT_MODE; - case NITIO_G2_CNT_MODE: - return NI660X_G2_CNT_MODE; - case NITIO_G3_CNT_MODE: - return NI660X_G3_CNT_MODE; - case NITIO_G0_GATE2: - return NI660X_G0_GATE2; - case NITIO_G1_GATE2: - return NI660X_G1_GATE2; - case NITIO_G2_GATE2: - return NI660X_G2_GATE2; - case NITIO_G3_GATE2: - return NI660X_G3_GATE2; - case NITIO_G0_DMA_CFG: - return NI660X_G0_DMA_CFG; - case NITIO_G0_DMA_STATUS: - return NI660X_G0_DMA_STATUS; - case NITIO_G1_DMA_CFG: - return NI660X_G1_DMA_CFG; - case NITIO_G1_DMA_STATUS: - return NI660X_G1_DMA_STATUS; - case NITIO_G2_DMA_CFG: - return NI660X_G2_DMA_CFG; - case NITIO_G2_DMA_STATUS: - return NI660X_G2_DMA_STATUS; - case NITIO_G3_DMA_CFG: - return NI660X_G3_DMA_CFG; - case NITIO_G3_DMA_STATUS: - return NI660X_G3_DMA_STATUS; - case NITIO_G0_INT_ACK: - return NI660X_G0_INT_ACK; - case NITIO_G1_INT_ACK: - return NI660X_G1_INT_ACK; - case NITIO_G2_INT_ACK: - return NI660X_G2_INT_ACK; - case NITIO_G3_INT_ACK: - return NI660X_G3_INT_ACK; - case NITIO_G0_STATUS: - return NI660X_G0_STATUS; - case NITIO_G1_STATUS: - return NI660X_G1_STATUS; - case NITIO_G2_STATUS: - return NI660X_G2_STATUS; - case NITIO_G3_STATUS: - return NI660X_G3_STATUS; - case NITIO_G0_INT_ENA: - return NI660X_G0_INT_ENA; - case NITIO_G1_INT_ENA: - return NI660X_G1_INT_ENA; - case NITIO_G2_INT_ENA: - return NI660X_G2_INT_ENA; - case NITIO_G3_INT_ENA: - return NI660X_G3_INT_ENA; - default: - BUG(); - return 0; - } -} - -static inline void ni_660x_write_register(struct comedi_device *dev, - unsigned chip, unsigned bits, - enum ni_660x_register reg) +static void ni_660x_write(struct comedi_device *dev, unsigned int chip, + unsigned int bits, unsigned int reg) { - unsigned int addr = GPCT_OFFSET[chip] + registerData[reg].offset; + unsigned int addr = (chip * NI660X_CHIP_OFFSET) + + ni_660x_reg_data[reg].offset; - switch (registerData[reg].size) { - case DATA_2B: + if (ni_660x_reg_data[reg].size == 2) writew(bits, dev->mmio + addr); - break; - case DATA_4B: + else writel(bits, dev->mmio + addr); - break; - default: - BUG(); - break; - } } -static inline unsigned ni_660x_read_register(struct comedi_device *dev, - unsigned chip, - enum ni_660x_register reg) +static unsigned int ni_660x_read(struct comedi_device *dev, + unsigned int chip, unsigned int reg) { - unsigned int addr = GPCT_OFFSET[chip] + registerData[reg].offset; + unsigned int addr = (chip * NI660X_CHIP_OFFSET) + + ni_660x_reg_data[reg].offset; - switch (registerData[reg].size) { - case DATA_2B: + if (ni_660x_reg_data[reg].size == 2) return readw(dev->mmio + addr); - case DATA_4B: - return readl(dev->mmio + addr); - default: - BUG(); - break; - } - return 0; + return readl(dev->mmio + addr); } -static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits, - enum ni_gpct_register reg) +static void ni_660x_gpct_write(struct ni_gpct *counter, unsigned int bits, + enum ni_gpct_register reg) { struct comedi_device *dev = counter->counter_dev->dev; - enum ni_660x_register ni_660x_register = ni_gpct_to_660x_register(reg); - unsigned chip = counter->chip_index; - ni_660x_write_register(dev, chip, bits, ni_660x_register); + ni_660x_write(dev, counter->chip_index, bits, reg); } -static unsigned ni_gpct_read_register(struct ni_gpct *counter, +static unsigned int ni_660x_gpct_read(struct ni_gpct *counter, enum ni_gpct_register reg) { struct comedi_device *dev = counter->counter_dev->dev; - enum ni_660x_register ni_660x_register = ni_gpct_to_660x_register(reg); - unsigned chip = counter->chip_index; - - return ni_660x_read_register(dev, chip, ni_660x_register); -} - -static inline struct mite_dma_descriptor_ring *mite_ring(struct ni_660x_private - *priv, - struct ni_gpct - *counter) -{ - unsigned chip = counter->chip_index; - return priv->mite_rings[chip][counter->counter_index]; + return ni_660x_read(dev, counter->chip_index, reg); } static inline void ni_660x_set_dma_channel(struct comedi_device *dev, - unsigned mite_channel, + unsigned int mite_channel, struct ni_gpct *counter) { struct ni_660x_private *devpriv = dev->private; - unsigned chip = counter->chip_index; - unsigned long flags; - - spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags); - devpriv->dma_configuration_soft_copies[chip] &= - ~dma_select_mask(mite_channel); - devpriv->dma_configuration_soft_copies[chip] |= - dma_select_bits(mite_channel, counter->counter_index); - ni_660x_write_register(dev, chip, - devpriv->dma_configuration_soft_copies[chip] | - dma_reset_bit(mite_channel), NI660X_DMA_CFG); + unsigned int chip = counter->chip_index; + + devpriv->dma_cfg[chip] &= ~NI660X_DMA_CFG_SEL_MASK(mite_channel); + devpriv->dma_cfg[chip] |= NI660X_DMA_CFG_SEL(mite_channel, + counter->counter_index); + ni_660x_write(dev, chip, devpriv->dma_cfg[chip] | + NI660X_DMA_CFG_RESET(mite_channel), + NI660X_DMA_CFG); mmiowb(); - spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags); } static inline void ni_660x_unset_dma_channel(struct comedi_device *dev, - unsigned mite_channel, + unsigned int mite_channel, struct ni_gpct *counter) { struct ni_660x_private *devpriv = dev->private; - unsigned chip = counter->chip_index; - unsigned long flags; + unsigned int chip = counter->chip_index; - spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags); - devpriv->dma_configuration_soft_copies[chip] &= - ~dma_select_mask(mite_channel); - devpriv->dma_configuration_soft_copies[chip] |= - dma_select_bits(mite_channel, dma_selection_none); - ni_660x_write_register(dev, chip, - devpriv->dma_configuration_soft_copies[chip], - NI660X_DMA_CFG); + devpriv->dma_cfg[chip] &= ~NI660X_DMA_CFG_SEL_MASK(mite_channel); + devpriv->dma_cfg[chip] |= NI660X_DMA_CFG_SEL_NONE(mite_channel); + ni_660x_write(dev, chip, devpriv->dma_cfg[chip], NI660X_DMA_CFG); mmiowb(); - spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags); } static int ni_660x_request_mite_channel(struct comedi_device *dev, @@ -692,13 +338,13 @@ static int ni_660x_request_mite_channel(struct comedi_device *dev, enum comedi_io_direction direction) { struct ni_660x_private *devpriv = dev->private; - unsigned long flags; + struct mite_ring *ring; struct mite_channel *mite_chan; + unsigned long flags; spin_lock_irqsave(&devpriv->mite_channel_lock, flags); - BUG_ON(counter->mite_chan); - mite_chan = mite_request_channel(devpriv->mite, - mite_ring(devpriv, counter)); + ring = devpriv->ring[counter->chip_index][counter->counter_index]; + mite_chan = mite_request_channel(devpriv->mite, ring); if (!mite_chan) { spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); dev_err(dev->class_dev, @@ -757,7 +403,7 @@ static int ni_660x_cancel(struct comedi_device *dev, struct comedi_subdevice *s) static void set_tio_counterswap(struct comedi_device *dev, int chip) { - unsigned bits = 0; + unsigned int bits = 0; /* * See P. 3.5 of the Register-Level Programming manual. @@ -766,9 +412,9 @@ static void set_tio_counterswap(struct comedi_device *dev, int chip) * first chip. */ if (chip) - bits = CounterSwap; + bits = NI660X_CLK_CFG_COUNTER_SWAP; - ni_660x_write_register(dev, chip, bits, NI660X_CLK_CFG); + ni_660x_write(dev, chip, bits, NI660X_CLK_CFG); } static void ni_660x_handle_gpct_interrupt(struct comedi_device *dev, @@ -785,17 +431,20 @@ static irqreturn_t ni_660x_interrupt(int irq, void *d) struct comedi_device *dev = d; struct ni_660x_private *devpriv = dev->private; struct comedi_subdevice *s; - unsigned i; + unsigned int i; unsigned long flags; if (!dev->attached) return IRQ_NONE; + /* make sure dev->attached is checked before doing anything else */ + smp_mb(); + /* lock to avoid race with comedi_poll */ spin_lock_irqsave(&devpriv->interrupt_lock, flags); - smp_mb(); - for (i = 0; i < ni_660x_num_counters(dev); ++i) { - s = &dev->subdevices[NI_660X_GPCT_SUBDEV(i)]; - ni_660x_handle_gpct_interrupt(dev, s); + for (i = 0; i < dev->n_subdevices; ++i) { + s = &dev->subdevices[i]; + if (s->type == COMEDI_SUBD_COUNTER) + ni_660x_handle_gpct_interrupt(dev, s); } spin_unlock_irqrestore(&devpriv->interrupt_lock, flags); return IRQ_HANDLED; @@ -810,7 +459,7 @@ static int ni_660x_input_poll(struct comedi_device *dev, /* lock to avoid race with comedi_poll */ spin_lock_irqsave(&devpriv->interrupt_lock, flags); - mite_sync_input_dma(counter->mite_chan, s); + mite_sync_dma(counter->mite_chan, s); spin_unlock_irqrestore(&devpriv->interrupt_lock, flags); return comedi_buf_read_n_available(s); } @@ -820,9 +469,11 @@ static int ni_660x_buf_change(struct comedi_device *dev, { struct ni_660x_private *devpriv = dev->private; struct ni_gpct *counter = s->private; + struct mite_ring *ring; int ret; - ret = mite_buf_change(mite_ring(devpriv, counter), s); + ring = devpriv->ring[counter->chip_index][counter->counter_index]; + ret = mite_buf_change(ring, s); if (ret < 0) return ret; @@ -832,7 +483,7 @@ static int ni_660x_buf_change(struct comedi_device *dev, static int ni_660x_allocate_private(struct comedi_device *dev) { struct ni_660x_private *devpriv; - unsigned i; + unsigned int i; devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv)); if (!devpriv) @@ -840,9 +491,8 @@ static int ni_660x_allocate_private(struct comedi_device *dev) spin_lock_init(&devpriv->mite_channel_lock); spin_lock_init(&devpriv->interrupt_lock); - spin_lock_init(&devpriv->soft_reg_copy_lock); - for (i = 0; i < NUM_PFI_CHANNELS; ++i) - devpriv->pfi_output_selects[i] = pfi_output_select_counter; + for (i = 0; i < NI660X_NUM_PFI_CHANNELS; ++i) + devpriv->io_cfg[i] = NI_660X_PFI_OUTPUT_COUNTER; return 0; } @@ -851,14 +501,13 @@ static int ni_660x_alloc_mite_rings(struct comedi_device *dev) { const struct ni_660x_board *board = dev->board_ptr; struct ni_660x_private *devpriv = dev->private; - unsigned i; - unsigned j; + unsigned int i; + unsigned int j; for (i = 0; i < board->n_chips; ++i) { - for (j = 0; j < counters_per_chip; ++j) { - devpriv->mite_rings[i][j] = - mite_alloc_ring(devpriv->mite); - if (!devpriv->mite_rings[i][j]) + for (j = 0; j < NI660X_COUNTERS_PER_CHIP; ++j) { + devpriv->ring[i][j] = mite_alloc_ring(devpriv->mite); + if (!devpriv->ring[i][j]) return -ENOMEM; } } @@ -869,120 +518,101 @@ static void ni_660x_free_mite_rings(struct comedi_device *dev) { const struct ni_660x_board *board = dev->board_ptr; struct ni_660x_private *devpriv = dev->private; - unsigned i; - unsigned j; + unsigned int i; + unsigned int j; for (i = 0; i < board->n_chips; ++i) { - for (j = 0; j < counters_per_chip; ++j) - mite_free_ring(devpriv->mite_rings[i][j]); - } -} - -static void init_tio_chip(struct comedi_device *dev, int chipset) -{ - struct ni_660x_private *devpriv = dev->private; - unsigned i; - - /* init dma configuration register */ - devpriv->dma_configuration_soft_copies[chipset] = 0; - for (i = 0; i < MAX_DMA_CHANNEL; ++i) { - devpriv->dma_configuration_soft_copies[chipset] |= - dma_select_bits(i, dma_selection_none) & dma_select_mask(i); + for (j = 0; j < NI660X_COUNTERS_PER_CHIP; ++j) + mite_free_ring(devpriv->ring[i][j]); } - ni_660x_write_register(dev, chipset, - devpriv->dma_configuration_soft_copies[chipset], - NI660X_DMA_CFG); - for (i = 0; i < NUM_PFI_CHANNELS; ++i) - ni_660x_write_register(dev, chipset, 0, IOConfigReg(i)); } static int ni_660x_dio_insn_bits(struct comedi_device *dev, struct comedi_subdevice *s, - struct comedi_insn *insn, unsigned int *data) + struct comedi_insn *insn, + unsigned int *data) { - unsigned base_bitfield_channel = CR_CHAN(insn->chanspec); - - /* Check if we have to write some bits */ - if (data[0]) { - s->state &= ~(data[0] << base_bitfield_channel); - s->state |= (data[0] & data[1]) << base_bitfield_channel; - /* Write out the new digital output lines */ - ni_660x_write_register(dev, 0, s->state, NI660X_DIO32_OUTPUT); + unsigned int shift = CR_CHAN(insn->chanspec); + unsigned int mask = data[0] << shift; + unsigned int bits = data[1] << shift; + + /* + * There are 40 channels in this subdevice but only 32 are usable + * as DIO. The shift adjusts the mask/bits to account for the base + * channel in insn->chanspec. The state update can then be handled + * normally for the 32 usable channels. + */ + if (mask) { + s->state &= ~mask; + s->state |= (bits & mask); + ni_660x_write(dev, 0, s->state, NI660X_DIO32_OUTPUT); } - /* on return, data[1] contains the value of the digital - * input and output lines. */ - data[1] = (ni_660x_read_register(dev, 0, NI660X_DIO32_INPUT) >> - base_bitfield_channel); + + /* + * Return the input channels, shifted back to account for the base + * channel. + */ + data[1] = ni_660x_read(dev, 0, NI660X_DIO32_INPUT) >> shift; return insn->n; } static void ni_660x_select_pfi_output(struct comedi_device *dev, - unsigned pfi_channel, - unsigned output_select) + unsigned int chan, unsigned int out_sel) { const struct ni_660x_board *board = dev->board_ptr; - static const unsigned counter_4_7_first_pfi = 8; - static const unsigned counter_4_7_last_pfi = 23; - unsigned active_chipset = 0; - unsigned idle_chipset = 0; - unsigned active_bits; - unsigned idle_bits; + unsigned int active_chip = 0; + unsigned int idle_chip = 0; + unsigned int bits; if (board->n_chips > 1) { - if (output_select == pfi_output_select_counter && - pfi_channel >= counter_4_7_first_pfi && - pfi_channel <= counter_4_7_last_pfi) { - active_chipset = 1; - idle_chipset = 0; + if (out_sel == NI_660X_PFI_OUTPUT_COUNTER && + chan >= 8 && chan <= 23) { + /* counters 4-7 pfi channels */ + active_chip = 1; + idle_chip = 0; } else { - active_chipset = 0; - idle_chipset = 1; + /* counters 0-3 pfi channels */ + active_chip = 0; + idle_chip = 1; } } - if (idle_chipset != active_chipset) { - idle_bits = - ni_660x_read_register(dev, idle_chipset, - IOConfigReg(pfi_channel)); - idle_bits &= ~pfi_output_select_mask(pfi_channel); - idle_bits |= - pfi_output_select_bits(pfi_channel, - pfi_output_select_high_Z); - ni_660x_write_register(dev, idle_chipset, idle_bits, - IOConfigReg(pfi_channel)); + if (idle_chip != active_chip) { + /* set the pfi channel to high-z on the inactive chip */ + bits = ni_660x_read(dev, idle_chip, NI660X_IO_CFG(chan)); + bits &= ~NI660X_IO_CFG_OUT_SEL_MASK(chan); + bits |= NI660X_IO_CFG_OUT_SEL(chan, 0); /* high-z */ + ni_660x_write(dev, idle_chip, bits, NI660X_IO_CFG(chan)); } - active_bits = - ni_660x_read_register(dev, active_chipset, - IOConfigReg(pfi_channel)); - active_bits &= ~pfi_output_select_mask(pfi_channel); - active_bits |= pfi_output_select_bits(pfi_channel, output_select); - ni_660x_write_register(dev, active_chipset, active_bits, - IOConfigReg(pfi_channel)); + /* set the pfi channel output on the active chip */ + bits = ni_660x_read(dev, active_chip, NI660X_IO_CFG(chan)); + bits &= ~NI660X_IO_CFG_OUT_SEL_MASK(chan); + bits |= NI660X_IO_CFG_OUT_SEL(chan, out_sel); + ni_660x_write(dev, active_chip, bits, NI660X_IO_CFG(chan)); } -static int ni_660x_set_pfi_routing(struct comedi_device *dev, unsigned chan, - unsigned source) +static int ni_660x_set_pfi_routing(struct comedi_device *dev, + unsigned int chan, unsigned int source) { struct ni_660x_private *devpriv = dev->private; - if (source > num_pfi_output_selects) - return -EINVAL; - if (source == pfi_output_select_high_Z) - return -EINVAL; - if (chan < min_counter_pfi_chan) { - if (source == pfi_output_select_counter) + switch (source) { + case NI_660X_PFI_OUTPUT_COUNTER: + if (chan < 8) return -EINVAL; - } else if (chan > max_dio_pfi_chan) { - if (source == pfi_output_select_do) + break; + case NI_660X_PFI_OUTPUT_DIO: + if (chan > 31) return -EINVAL; + default: + return -EINVAL; } - devpriv->pfi_output_selects[chan] = source; - if (devpriv->pfi_direction_bits & (((uint64_t) 1) << chan)) - ni_660x_select_pfi_output(dev, chan, - devpriv->pfi_output_selects[chan]); + devpriv->io_cfg[chan] = source; + if (devpriv->io_dir & (1ULL << chan)) + ni_660x_select_pfi_output(dev, chan, devpriv->io_cfg[chan]); return 0; } @@ -993,25 +623,24 @@ static int ni_660x_dio_insn_config(struct comedi_device *dev, { struct ni_660x_private *devpriv = dev->private; unsigned int chan = CR_CHAN(insn->chanspec); - uint64_t bit = 1ULL << chan; + u64 bit = 1ULL << chan; unsigned int val; int ret; switch (data[0]) { case INSN_CONFIG_DIO_OUTPUT: - devpriv->pfi_direction_bits |= bit; - ni_660x_select_pfi_output(dev, chan, - devpriv->pfi_output_selects[chan]); + devpriv->io_dir |= bit; + ni_660x_select_pfi_output(dev, chan, devpriv->io_cfg[chan]); break; case INSN_CONFIG_DIO_INPUT: - devpriv->pfi_direction_bits &= ~bit; - ni_660x_select_pfi_output(dev, chan, pfi_output_select_high_Z); + devpriv->io_dir &= ~bit; + ni_660x_select_pfi_output(dev, chan, 0); /* high-z */ break; case INSN_CONFIG_DIO_QUERY: - data[1] = (devpriv->pfi_direction_bits & bit) ? COMEDI_OUTPUT - : COMEDI_INPUT; + data[1] = (devpriv->io_dir & bit) ? COMEDI_OUTPUT + : COMEDI_INPUT; break; case INSN_CONFIG_SET_ROUTING: @@ -1021,14 +650,14 @@ static int ni_660x_dio_insn_config(struct comedi_device *dev, break; case INSN_CONFIG_GET_ROUTING: - data[1] = devpriv->pfi_output_selects[chan]; + data[1] = devpriv->io_cfg[chan]; break; case INSN_CONFIG_FILTER: - val = ni_660x_read_register(dev, 0, IOConfigReg(chan)); - val &= ~pfi_input_select_mask(chan); - val |= pfi_input_select_bits(chan, data[1]); - ni_660x_write_register(dev, 0, val, IOConfigReg(chan)); + val = ni_660x_read(dev, 0, NI660X_IO_CFG(chan)); + val &= ~NI660X_IO_CFG_IN_SEL_MASK(chan); + val |= NI660X_IO_CFG_IN_SEL(chan, data[1]); + ni_660x_write(dev, 0, val, NI660X_IO_CFG(chan)); break; default: @@ -1038,6 +667,33 @@ static int ni_660x_dio_insn_config(struct comedi_device *dev, return insn->n; } +static void ni_660x_init_tio_chips(struct comedi_device *dev, + unsigned int n_chips) +{ + struct ni_660x_private *devpriv = dev->private; + unsigned int chip; + unsigned int chan; + + /* + * We use the ioconfig registers to control dio direction, so zero + * output enables in stc dio control reg. + */ + ni_660x_write(dev, 0, 0, NI660X_STC_DIO_CONTROL); + + for (chip = 0; chip < n_chips; ++chip) { + /* init dma configuration register */ + devpriv->dma_cfg[chip] = 0; + for (chan = 0; chan < NI660X_MAX_DMA_CHANNEL; ++chan) + devpriv->dma_cfg[chip] |= NI660X_DMA_CFG_SEL_NONE(chan); + ni_660x_write(dev, chip, devpriv->dma_cfg[chip], + NI660X_DMA_CFG); + + /* init ioconfig registers */ + for (chan = 0; chan < NI660X_NUM_PFI_CHANNELS; ++chan) + ni_660x_write(dev, chip, 0, NI660X_IO_CFG(chan)); + } +} + static int ni_660x_auto_attach(struct comedi_device *dev, unsigned long context) { @@ -1045,9 +701,12 @@ static int ni_660x_auto_attach(struct comedi_device *dev, const struct ni_660x_board *board = NULL; struct ni_660x_private *devpriv; struct comedi_subdevice *s; + struct ni_gpct_device *gpct_dev; + unsigned int n_counters; + int subdev; int ret; - unsigned i; - unsigned global_interrupt_config_bits; + unsigned int i; + unsigned int global_interrupt_config_bits; if (context < ARRAY_SIZE(ni_660x_boards)) board = &ni_660x_boards[context]; @@ -1065,91 +724,147 @@ static int ni_660x_auto_attach(struct comedi_device *dev, return ret; devpriv = dev->private; - devpriv->mite = mite_alloc(pcidev); + devpriv->mite = mite_attach(dev, true); /* use win1 */ if (!devpriv->mite) return -ENOMEM; - ret = mite_setup2(dev, devpriv->mite, true); - if (ret < 0) - return ret; - ret = ni_660x_alloc_mite_rings(dev); if (ret < 0) return ret; - ret = comedi_alloc_subdevices(dev, 2 + NI_660X_MAX_NUM_COUNTERS); + ni_660x_init_tio_chips(dev, board->n_chips); + + n_counters = board->n_chips * NI660X_COUNTERS_PER_CHIP; + gpct_dev = ni_gpct_device_construct(dev, + ni_660x_gpct_write, + ni_660x_gpct_read, + ni_gpct_variant_660x, + n_counters); + if (!gpct_dev) + return -ENOMEM; + devpriv->counter_dev = gpct_dev; + + ret = comedi_alloc_subdevices(dev, 2 + NI660X_MAX_COUNTERS); if (ret) return ret; - s = &dev->subdevices[0]; + subdev = 0; + + s = &dev->subdevices[subdev++]; /* Old GENERAL-PURPOSE COUNTER/TIME (GPCT) subdevice, no longer used */ s->type = COMEDI_SUBD_UNUSED; - s = &dev->subdevices[NI_660X_DIO_SUBDEV]; - /* DIGITAL I/O SUBDEVICE */ - s->type = COMEDI_SUBD_DIO; - s->subdev_flags = SDF_READABLE | SDF_WRITABLE; - s->n_chan = NUM_PFI_CHANNELS; - s->maxdata = 1; - s->range_table = &range_digital; - s->insn_bits = ni_660x_dio_insn_bits; - s->insn_config = ni_660x_dio_insn_config; - /* we use the ioconfig registers to control dio direction, so zero - output enables in stc dio control reg */ - ni_660x_write_register(dev, 0, 0, NI660X_STC_DIO_CONTROL); - - devpriv->counter_dev = ni_gpct_device_construct(dev, - &ni_gpct_write_register, - &ni_gpct_read_register, - ni_gpct_variant_660x, - ni_660x_num_counters - (dev)); - if (!devpriv->counter_dev) - return -ENOMEM; - for (i = 0; i < NI_660X_MAX_NUM_COUNTERS; ++i) { - s = &dev->subdevices[NI_660X_GPCT_SUBDEV(i)]; - if (i < ni_660x_num_counters(dev)) { - s->type = COMEDI_SUBD_COUNTER; - s->subdev_flags = SDF_READABLE | SDF_WRITABLE | + /* + * Digital I/O subdevice + * + * There are 40 channels but only the first 32 can be digital I/Os. + * The last 8 are dedicated to counters 0 and 1. + * + * Counter 0-3 signals are from the first TIO chip. + * Counter 4-7 signals are from the second TIO chip. + * + * Comedi External + * PFI Chan DIO Chan Counter Signal + * ------- -------- -------------- + * 0 0 + * 1 1 + * 2 2 + * 3 3 + * 4 4 + * 5 5 + * 6 6 + * 7 7 + * 8 8 CTR 7 OUT + * 9 9 CTR 7 AUX + * 10 10 CTR 7 GATE + * 11 11 CTR 7 SOURCE + * 12 12 CTR 6 OUT + * 13 13 CTR 6 AUX + * 14 14 CTR 6 GATE + * 15 15 CTR 6 SOURCE + * 16 16 CTR 5 OUT + * 17 17 CTR 5 AUX + * 18 18 CTR 5 GATE + * 19 19 CTR 5 SOURCE + * 20 20 CTR 4 OUT + * 21 21 CTR 4 AUX + * 22 22 CTR 4 GATE + * 23 23 CTR 4 SOURCE + * 24 24 CTR 3 OUT + * 25 25 CTR 3 AUX + * 26 26 CTR 3 GATE + * 27 27 CTR 3 SOURCE + * 28 28 CTR 2 OUT + * 29 29 CTR 2 AUX + * 30 30 CTR 2 GATE + * 31 31 CTR 2 SOURCE + * 32 CTR 1 OUT + * 33 CTR 1 AUX + * 34 CTR 1 GATE + * 35 CTR 1 SOURCE + * 36 CTR 0 OUT + * 37 CTR 0 AUX + * 38 CTR 0 GATE + * 39 CTR 0 SOURCE + */ + s = &dev->subdevices[subdev++]; + s->type = COMEDI_SUBD_DIO; + s->subdev_flags = SDF_READABLE | SDF_WRITABLE; + s->n_chan = NI660X_NUM_PFI_CHANNELS; + s->maxdata = 1; + s->range_table = &range_digital; + s->insn_bits = ni_660x_dio_insn_bits; + s->insn_config = ni_660x_dio_insn_config; + + /* + * Default the DIO channels as: + * chan 0-7: DIO inputs + * chan 8-39: counter signal inputs + */ + for (i = 0; i < s->n_chan; ++i) { + unsigned int source = (i < 8) ? NI_660X_PFI_OUTPUT_DIO + : NI_660X_PFI_OUTPUT_COUNTER; + + ni_660x_set_pfi_routing(dev, i, source); + ni_660x_select_pfi_output(dev, i, 0); /* high-z */ + } + + /* Counter subdevices (4 NI TIO General Purpose Counters per chip) */ + for (i = 0; i < NI660X_MAX_COUNTERS; ++i) { + s = &dev->subdevices[subdev++]; + if (i < n_counters) { + struct ni_gpct *counter = &gpct_dev->counters[i]; + + counter->chip_index = i / NI660X_COUNTERS_PER_CHIP; + counter->counter_index = i % NI660X_COUNTERS_PER_CHIP; + + s->type = COMEDI_SUBD_COUNTER; + s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL | SDF_CMD_READ; - s->n_chan = 3; - s->maxdata = 0xffffffff; - s->insn_read = ni_tio_insn_read; - s->insn_write = ni_tio_insn_write; - s->insn_config = ni_tio_insn_config; - s->do_cmd = &ni_660x_cmd; - s->len_chanlist = 1; - s->do_cmdtest = ni_tio_cmdtest; - s->cancel = &ni_660x_cancel; - s->poll = &ni_660x_input_poll; + s->n_chan = 3; + s->maxdata = 0xffffffff; + s->insn_read = ni_tio_insn_read; + s->insn_write = ni_tio_insn_write; + s->insn_config = ni_tio_insn_config; + s->len_chanlist = 1; + s->do_cmd = ni_660x_cmd; + s->do_cmdtest = ni_tio_cmdtest; + s->cancel = ni_660x_cancel; + s->poll = ni_660x_input_poll; + s->buf_change = ni_660x_buf_change; s->async_dma_dir = DMA_BIDIRECTIONAL; - s->buf_change = &ni_660x_buf_change; - s->private = &devpriv->counter_dev->counters[i]; + s->private = counter; - devpriv->counter_dev->counters[i].chip_index = - i / counters_per_chip; - devpriv->counter_dev->counters[i].counter_index = - i % counters_per_chip; + ni_tio_init_counter(counter); } else { - s->type = COMEDI_SUBD_UNUSED; + s->type = COMEDI_SUBD_UNUSED; } } - for (i = 0; i < board->n_chips; ++i) - init_tio_chip(dev, i); - - for (i = 0; i < ni_660x_num_counters(dev); ++i) - ni_tio_init_counter(&devpriv->counter_dev->counters[i]); - - for (i = 0; i < NUM_PFI_CHANNELS; ++i) { - if (i < min_counter_pfi_chan) - ni_660x_set_pfi_routing(dev, i, pfi_output_select_do); - else - ni_660x_set_pfi_routing(dev, i, - pfi_output_select_counter); - ni_660x_select_pfi_output(dev, i, pfi_output_select_high_Z); - } - /* to be safe, set counterswap bits on tio chips after all the counter - outputs have been set to high impedance mode */ + + /* + * To be safe, set counterswap bits on tio chips after all the counter + * outputs have been set to high impedance mode. + */ for (i = 0; i < board->n_chips; ++i) set_tio_counterswap(dev, i); @@ -1160,11 +875,11 @@ static int ni_660x_auto_attach(struct comedi_device *dev, return ret; } dev->irq = pcidev->irq; - global_interrupt_config_bits = Global_Int_Enable_Bit; + global_interrupt_config_bits = NI660X_GLOBAL_INT_GLOBAL; if (board->n_chips > 1) - global_interrupt_config_bits |= Cascade_Int_Enable_Bit; - ni_660x_write_register(dev, 0, global_interrupt_config_bits, - NI660X_GLOBAL_INT_CFG); + global_interrupt_config_bits |= NI660X_GLOBAL_INT_CASCADE; + ni_660x_write(dev, 0, global_interrupt_config_bits, + NI660X_GLOBAL_INT_CFG); return 0; } @@ -1173,11 +888,12 @@ static void ni_660x_detach(struct comedi_device *dev) { struct ni_660x_private *devpriv = dev->private; - if (dev->irq) + if (dev->irq) { + ni_660x_write(dev, 0, 0, NI660X_GLOBAL_INT_CFG); free_irq(dev->irq, dev); + } if (devpriv) { - if (devpriv->counter_dev) - ni_gpct_device_destroy(devpriv->counter_dev); + ni_gpct_device_destroy(devpriv->counter_dev); ni_660x_free_mite_rings(dev); mite_detach(devpriv->mite); } @@ -1218,5 +934,5 @@ static struct pci_driver ni_660x_pci_driver = { module_comedi_pci_driver(ni_660x_driver, ni_660x_pci_driver); MODULE_AUTHOR("Comedi http://www.comedi.org"); -MODULE_DESCRIPTION("Comedi low-level driver"); +MODULE_DESCRIPTION("Comedi driver for NI 660x counter/timer boards"); MODULE_LICENSE("GPL"); diff --git a/drivers/staging/comedi/drivers/ni_labpc.h b/drivers/staging/comedi/drivers/ni_labpc.h index 83f878adbd53..be8d5cd3f7f0 100644 --- a/drivers/staging/comedi/drivers/ni_labpc.h +++ b/drivers/staging/comedi/drivers/ni_labpc.h @@ -1,27 +1,22 @@ /* - ni_labpc.h - - Header for ni_labpc.c and ni_labpc_cs.c - - Copyright (C) 2003 Frank Mori Hess <fmhess@users.sourceforge.net> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*/ + * Header for ni_labpc ISA/PCMCIA/PCI drivers + * + * Copyright (C) 2003 Frank Mori Hess <fmhess@users.sourceforge.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ #ifndef _NI_LABPC_H #define _NI_LABPC_H -#define EEPROM_SIZE 256 /* 256 byte eeprom */ -#define NUM_AO_CHAN 2 /* boards have two analog output channels */ - enum transfer_type { fifo_not_empty_transfer, fifo_half_full_transfer, isa_dma_transfer }; diff --git a/drivers/staging/comedi/drivers/ni_labpc_common.c b/drivers/staging/comedi/drivers/ni_labpc_common.c index 863afb28ee28..b0dfb8eed16d 100644 --- a/drivers/staging/comedi/drivers/ni_labpc_common.c +++ b/drivers/staging/comedi/drivers/ni_labpc_common.c @@ -84,8 +84,10 @@ static const struct comedi_lrange range_labpc_ao = { } }; -/* functions that do inb/outb and readb/writeb so we can use - * function pointers to decide which to use */ +/* + * functions that do inb/outb and readb/writeb so we can use + * function pointers to decide which to use + */ static unsigned int labpc_inb(struct comedi_device *dev, unsigned long reg) { return inb(dev->iobase + reg); @@ -656,19 +658,24 @@ static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) /* figure out what method we will use to transfer data */ if (devpriv->dma && - /* dma unsafe at RT priority, - * and too much setup time for CMDF_WAKE_EOS */ - (cmd->flags & (CMDF_WAKE_EOS | CMDF_PRIORITY)) == 0) + (cmd->flags & (CMDF_WAKE_EOS | CMDF_PRIORITY)) == 0) { + /* + * dma unsafe at RT priority, + * and too much setup time for CMDF_WAKE_EOS + */ xfer = isa_dma_transfer; - else if (/* pc-plus has no fifo-half full interrupt */ - board->is_labpc1200 && - /* wake-end-of-scan should interrupt on fifo not empty */ - (cmd->flags & CMDF_WAKE_EOS) == 0 && - /* make sure we are taking more than just a few points */ - (cmd->stop_src != TRIG_COUNT || devpriv->count > 256)) + } else if (board->is_labpc1200 && + (cmd->flags & CMDF_WAKE_EOS) == 0 && + (cmd->stop_src != TRIG_COUNT || devpriv->count > 256)) { + /* + * pc-plus has no fifo-half full interrupt + * wake-end-of-scan should interrupt on fifo not empty + * make sure we are taking more than just a few points + */ xfer = fifo_half_full_transfer; - else + } else { xfer = fifo_not_empty_transfer; + } devpriv->current_transfer = xfer; labpc_ai_set_chan_and_gain(dev, mode, chan, range, aref); @@ -679,9 +686,11 @@ static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) /* manual says to set scan enable bit on second pass */ if (mode == MODE_MULT_CHAN_UP || mode == MODE_MULT_CHAN_DOWN) { devpriv->cmd1 |= CMD1_SCANEN; - /* need a brief delay before enabling scan, or scan - * list will get screwed when you switch - * between scan up to scan down mode - dunno why */ + /* + * Need a brief delay before enabling scan, or scan + * list will get screwed when you switch between + * scan up to scan down mode - dunno why. + */ udelay(1); devpriv->write_byte(dev, devpriv->cmd1, CMD1_REG); } @@ -728,8 +737,10 @@ static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) devpriv->cmd4 = 0; if (cmd->convert_src != TRIG_EXT) devpriv->cmd4 |= CMD4_ECLKRCV; - /* XXX should discard first scan when using interval scanning - * since manual says it is not synced with scan clock */ + /* + * XXX should discard first scan when using interval scanning + * since manual says it is not synced with scan clock. + */ if (!labpc_use_continuous_mode(cmd, mode)) { devpriv->cmd4 |= CMD4_INTSCAN; if (cmd->scan_begin_src == TRIG_EXT) @@ -795,8 +806,10 @@ static int labpc_drain_fifo(struct comedi_device *dev) return 0; } -/* makes sure all data acquired by board is transferred to comedi (used - * when acquisition is terminated by stop_src == TRIG_EXT). */ +/* + * Makes sure all data acquired by board is transferred to comedi (used + * when acquisition is terminated by stop_src == TRIG_EXT). + */ static void labpc_drain_dregs(struct comedi_device *dev) { struct labpc_private *devpriv = dev->private; @@ -907,9 +920,11 @@ static int labpc_ao_insn_write(struct comedi_device *dev, channel = CR_CHAN(insn->chanspec); - /* turn off pacing of analog output channel */ - /* note: hardware bug in daqcard-1200 means pacing cannot - * be independently enabled/disabled for its the two channels */ + /* + * Turn off pacing of analog output channel. + * NOTE: hardware bug in daqcard-1200 means pacing cannot + * be independently enabled/disabled for its the two channels. + */ spin_lock_irqsave(&dev->spinlock, flags); devpriv->cmd2 &= ~CMD2_LDAC(channel); devpriv->write_byte(dev, devpriv->cmd2, CMD2_REG); @@ -1261,7 +1276,7 @@ int labpc_common_attach(struct comedi_device *dev, if (board->has_ao) { s->type = COMEDI_SUBD_AO; s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_GROUND; - s->n_chan = NUM_AO_CHAN; + s->n_chan = 2; s->maxdata = 0x0fff; s->range_table = &range_labpc_ao; s->insn_write = labpc_ao_insn_write; @@ -1307,12 +1322,12 @@ int labpc_common_attach(struct comedi_device *dev, s->type = COMEDI_SUBD_UNUSED; } - /* EEPROM */ + /* EEPROM (256 bytes) */ s = &dev->subdevices[4]; if (board->is_labpc1200) { s->type = COMEDI_SUBD_MEMORY; s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; - s->n_chan = EEPROM_SIZE; + s->n_chan = 256; s->maxdata = 0xff; s->insn_write = labpc_eeprom_insn_write; diff --git a/drivers/staging/comedi/drivers/ni_labpc_cs.c b/drivers/staging/comedi/drivers/ni_labpc_cs.c index a1c69ac075d5..3d4d0b9ad4e1 100644 --- a/drivers/staging/comedi/drivers/ni_labpc_cs.c +++ b/drivers/staging/comedi/drivers/ni_labpc_cs.c @@ -1,57 +1,50 @@ /* - comedi/drivers/ni_labpc_cs.c - Driver for National Instruments daqcard-1200 boards - Copyright (C) 2001, 2002, 2003 Frank Mori Hess <fmhess@users.sourceforge.net> - - PCMCIA crap is adapted from dummy_cs.c 1.31 2001/08/24 12:13:13 - from the pcmcia package. - The initial developer of the pcmcia dummy_cs.c code is David A. Hinds - <dahinds@users.sourceforge.net>. Portions created by David A. Hinds - are Copyright (C) 1999 David A. Hinds. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*/ -/* -Driver: ni_labpc_cs -Description: National Instruments Lab-PC (& compatibles) -Author: Frank Mori Hess <fmhess@users.sourceforge.net> -Devices: [National Instruments] DAQCard-1200 (daqcard-1200) -Status: works - -Thanks go to Fredrik Lingvall for much testing and perseverance in -helping to debug daqcard-1200 support. - -The 1200 series boards have onboard calibration dacs for correcting -analog input/output offsets and gains. The proper settings for these -caldacs are stored on the board's eeprom. To read the caldac values -from the eeprom and store them into a file that can be then be used by -comedilib, use the comedi_calibrate program. - -Configuration options: - none - -The daqcard-1200 has quirky chanlist requirements -when scanning multiple channels. Multiple channel scan -sequence must start at highest channel, then decrement down to -channel 0. Chanlists consisting of all one channel -are also legal, and allow you to pace conversions in bursts. - -*/ + * Driver for National Instruments daqcard-1200 boards + * Copyright (C) 2001, 2002, 2003 Frank Mori Hess <fmhess@users.sourceforge.net> + * + * PCMCIA crap is adapted from dummy_cs.c 1.31 2001/08/24 12:13:13 + * from the pcmcia package. + * The initial developer of the pcmcia dummy_cs.c code is David A. Hinds + * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds + * are Copyright (C) 1999 David A. Hinds. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * General Public License for more details. + */ /* - -NI manuals: -340988a (daqcard-1200) - -*/ + * Driver: ni_labpc_cs + * Description: National Instruments Lab-PC (& compatibles) + * Author: Frank Mori Hess <fmhess@users.sourceforge.net> + * Devices: [National Instruments] DAQCard-1200 (daqcard-1200) + * Status: works + * + * Thanks go to Fredrik Lingvall for much testing and perseverance in + * helping to debug daqcard-1200 support. + * + * The 1200 series boards have onboard calibration dacs for correcting + * analog input/output offsets and gains. The proper settings for these + * caldacs are stored on the board's eeprom. To read the caldac values + * from the eeprom and store them into a file that can be then be used by + * comedilib, use the comedi_calibrate program. + * + * Configuration options: none + * + * The daqcard-1200 has quirky chanlist requirements when scanning multiple + * channels. Multiple channel scan sequence must start at highest channel, + * then decrement down to channel 0. Chanlists consisting of all one channel + * are also legal, and allow you to pace conversions in bursts. + * + * NI manuals: + * 340988a (daqcard-1200) + */ #include <linux/module.h> diff --git a/drivers/staging/comedi/drivers/ni_labpc_pci.c b/drivers/staging/comedi/drivers/ni_labpc_pci.c index 77d403801db5..cac089193121 100644 --- a/drivers/staging/comedi/drivers/ni_labpc_pci.c +++ b/drivers/staging/comedi/drivers/ni_labpc_pci.c @@ -51,8 +51,8 @@ static const struct labpc_boardinfo labpc_pci_boards[] = { }; /* ripped from mite.h and mite_setup2() to avoid mite dependency */ -#define MITE_IODWBSR 0xc0 /* IO Device Window Base Size Register */ -#define WENAB (1 << 7) /* window enable */ +#define MITE_IODWBSR 0xc0 /* IO Device Window Base Size Register */ +#define WENAB BIT(7) /* window enable */ static int labpc_pci_mite_init(struct pci_dev *pcidev) { diff --git a/drivers/staging/comedi/drivers/ni_labpc_regs.h b/drivers/staging/comedi/drivers/ni_labpc_regs.h index 2a274a3e4e73..8c52179e36fc 100644 --- a/drivers/staging/comedi/drivers/ni_labpc_regs.h +++ b/drivers/staging/comedi/drivers/ni_labpc_regs.h @@ -9,32 +9,32 @@ * Register map (all registers are 8-bit) */ #define STAT1_REG 0x00 /* R: Status 1 reg */ -#define STAT1_DAVAIL (1 << 0) -#define STAT1_OVERRUN (1 << 1) -#define STAT1_OVERFLOW (1 << 2) -#define STAT1_CNTINT (1 << 3) -#define STAT1_GATA0 (1 << 5) -#define STAT1_EXTGATA0 (1 << 6) +#define STAT1_DAVAIL BIT(0) +#define STAT1_OVERRUN BIT(1) +#define STAT1_OVERFLOW BIT(2) +#define STAT1_CNTINT BIT(3) +#define STAT1_GATA0 BIT(5) +#define STAT1_EXTGATA0 BIT(6) #define CMD1_REG 0x00 /* W: Command 1 reg */ #define CMD1_MA(x) (((x) & 0x7) << 0) -#define CMD1_TWOSCMP (1 << 3) +#define CMD1_TWOSCMP BIT(3) #define CMD1_GAIN(x) (((x) & 0x7) << 4) -#define CMD1_SCANEN (1 << 7) +#define CMD1_SCANEN BIT(7) #define CMD2_REG 0x01 /* W: Command 2 reg */ -#define CMD2_PRETRIG (1 << 0) -#define CMD2_HWTRIG (1 << 1) -#define CMD2_SWTRIG (1 << 2) -#define CMD2_TBSEL (1 << 3) -#define CMD2_2SDAC0 (1 << 4) -#define CMD2_2SDAC1 (1 << 5) -#define CMD2_LDAC(x) (1 << (6 + (x))) +#define CMD2_PRETRIG BIT(0) +#define CMD2_HWTRIG BIT(1) +#define CMD2_SWTRIG BIT(2) +#define CMD2_TBSEL BIT(3) +#define CMD2_2SDAC0 BIT(4) +#define CMD2_2SDAC1 BIT(5) +#define CMD2_LDAC(x) BIT(6 + ((x) & 0x1)) #define CMD3_REG 0x02 /* W: Command 3 reg */ -#define CMD3_DMAEN (1 << 0) -#define CMD3_DIOINTEN (1 << 1) -#define CMD3_DMATCINTEN (1 << 2) -#define CMD3_CNTINTEN (1 << 3) -#define CMD3_ERRINTEN (1 << 4) -#define CMD3_FIFOINTEN (1 << 5) +#define CMD3_DMAEN BIT(0) +#define CMD3_DIOINTEN BIT(1) +#define CMD3_DMATCINTEN BIT(2) +#define CMD3_CNTINTEN BIT(3) +#define CMD3_ERRINTEN BIT(4) +#define CMD3_FIFOINTEN BIT(5) #define ADC_START_CONVERT_REG 0x03 /* W: Start Convert reg */ #define DAC_LSB_REG(x) (0x04 + 2 * (x)) /* W: DAC0/1 LSB reg */ #define DAC_MSB_REG(x) (0x05 + 2 * (x)) /* W: DAC0/1 MSB reg */ @@ -43,32 +43,32 @@ #define DMATC_CLEAR_REG 0x0a /* W: DMA Interrupt Clear reg */ #define TIMER_CLEAR_REG 0x0c /* W: Timer Interrupt Clear reg */ #define CMD6_REG 0x0e /* W: Command 6 reg */ -#define CMD6_NRSE (1 << 0) -#define CMD6_ADCUNI (1 << 1) -#define CMD6_DACUNI(x) (1 << (2 + (x))) -#define CMD6_HFINTEN (1 << 5) -#define CMD6_DQINTEN (1 << 6) -#define CMD6_SCANUP (1 << 7) +#define CMD6_NRSE BIT(0) +#define CMD6_ADCUNI BIT(1) +#define CMD6_DACUNI(x) BIT(2 + ((x) & 0x1)) +#define CMD6_HFINTEN BIT(5) +#define CMD6_DQINTEN BIT(6) +#define CMD6_SCANUP BIT(7) #define CMD4_REG 0x0f /* W: Command 3 reg */ -#define CMD4_INTSCAN (1 << 0) -#define CMD4_EOIRCV (1 << 1) -#define CMD4_ECLKDRV (1 << 2) -#define CMD4_SEDIFF (1 << 3) -#define CMD4_ECLKRCV (1 << 4) +#define CMD4_INTSCAN BIT(0) +#define CMD4_EOIRCV BIT(1) +#define CMD4_ECLKDRV BIT(2) +#define CMD4_SEDIFF BIT(3) +#define CMD4_ECLKRCV BIT(4) #define DIO_BASE_REG 0x10 /* R/W: 8255 DIO base reg */ #define COUNTER_A_BASE_REG 0x14 /* R/W: 8253 Counter A base reg */ #define COUNTER_B_BASE_REG 0x18 /* R/W: 8253 Counter B base reg */ #define CMD5_REG 0x1c /* W: Command 5 reg */ -#define CMD5_WRTPRT (1 << 2) -#define CMD5_DITHEREN (1 << 3) -#define CMD5_CALDACLD (1 << 4) -#define CMD5_SCLK (1 << 5) -#define CMD5_SDATA (1 << 6) -#define CMD5_EEPROMCS (1 << 7) +#define CMD5_WRTPRT BIT(2) +#define CMD5_DITHEREN BIT(3) +#define CMD5_CALDACLD BIT(4) +#define CMD5_SCLK BIT(5) +#define CMD5_SDATA BIT(6) +#define CMD5_EEPROMCS BIT(7) #define STAT2_REG 0x1d /* R: Status 2 reg */ -#define STAT2_PROMOUT (1 << 0) -#define STAT2_OUTA1 (1 << 1) -#define STAT2_FIFONHF (1 << 2) +#define STAT2_PROMOUT BIT(0) +#define STAT2_OUTA1 BIT(1) +#define STAT2_FIFONHF BIT(2) #define INTERVAL_COUNT_REG 0x1e /* W: Interval Counter Data reg */ #define INTERVAL_STROBE_REG 0x1f /* W: Interval Counter Strobe reg */ diff --git a/drivers/staging/comedi/drivers/ni_mio_c_common.c b/drivers/staging/comedi/drivers/ni_mio_c_common.c deleted file mode 100644 index e69de29bb2d1..000000000000 --- a/drivers/staging/comedi/drivers/ni_mio_c_common.c +++ /dev/null diff --git a/drivers/staging/comedi/drivers/ni_mio_common.c b/drivers/staging/comedi/drivers/ni_mio_common.c index dcaf7e89f299..8dabb19519a5 100644 --- a/drivers/staging/comedi/drivers/ni_mio_common.c +++ b/drivers/staging/comedi/drivers/ni_mio_common.c @@ -1,56 +1,53 @@ /* - comedi/drivers/ni_mio_common.c - Hardware driver for DAQ-STC based boards - - COMEDI - Linux Control and Measurement Device Interface - Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org> - Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*/ + * Hardware driver for DAQ-STC based boards + * + * COMEDI - Linux Control and Measurement Device Interface + * Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org> + * Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ /* - This file is meant to be included by another file, e.g., - ni_atmio.c or ni_pcimio.c. - - Interrupt support originally added by Truxton Fulton - <trux@truxton.com> - - References (from ftp://ftp.natinst.com/support/manuals): - - 340747b.pdf AT-MIO E series Register Level Programmer Manual - 341079b.pdf PCI E Series RLPM - 340934b.pdf DAQ-STC reference manual - 67xx and 611x registers (from ftp://ftp.ni.com/support/daq/mhddk/documentation/) - release_ni611x.pdf - release_ni67xx.pdf - Other possibly relevant info: - - 320517c.pdf User manual (obsolete) - 320517f.pdf User manual (new) - 320889a.pdf delete - 320906c.pdf maximum signal ratings - 321066a.pdf about 16x - 321791a.pdf discontinuation of at-mio-16e-10 rev. c - 321808a.pdf about at-mio-16e-10 rev P - 321837a.pdf discontinuation of at-mio-16de-10 rev d - 321838a.pdf about at-mio-16de-10 rev N - - ISSUES: - - - the interrupt routine needs to be cleaned up - - 2006-02-07: S-Series PCI-6143: Support has been added but is not - fully tested as yet. Terry Barnaby, BEAM Ltd. -*/ + * This file is meant to be included by another file, e.g., + * ni_atmio.c or ni_pcimio.c. + * + * Interrupt support originally added by Truxton Fulton <trux@truxton.com> + * + * References (ftp://ftp.natinst.com/support/manuals): + * 340747b.pdf AT-MIO E series Register Level Programmer Manual + * 341079b.pdf PCI E Series RLPM + * 340934b.pdf DAQ-STC reference manual + * + * 67xx and 611x registers (ftp://ftp.ni.com/support/daq/mhddk/documentation/) + * release_ni611x.pdf + * release_ni67xx.pdf + * + * Other possibly relevant info: + * 320517c.pdf User manual (obsolete) + * 320517f.pdf User manual (new) + * 320889a.pdf delete + * 320906c.pdf maximum signal ratings + * 321066a.pdf about 16x + * 321791a.pdf discontinuation of at-mio-16e-10 rev. c + * 321808a.pdf about at-mio-16e-10 rev P + * 321837a.pdf discontinuation of at-mio-16de-10 rev d + * 321838a.pdf about at-mio-16de-10 rev N + * + * ISSUES: + * - the interrupt routine needs to be cleaned up + * + * 2006-02-07: S-Series PCI-6143: Support has been added but is not + * fully tested as yet. Terry Barnaby, BEAM Ltd. + */ #include <linux/interrupt.h> #include <linux/sched.h> @@ -216,19 +213,8 @@ enum ni_common_subdevices { NI_FREQ_OUT_SUBDEV, NI_NUM_SUBDEVICES }; -static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index) -{ - switch (counter_index) { - case 0: - return NI_GPCT0_SUBDEV; - case 1: - return NI_GPCT1_SUBDEV; - default: - break; - } - BUG(); - return NI_GPCT0_SUBDEV; -} + +#define NI_GPCT_SUBDEV(x) (NI_GPCT0_SUBDEV + (x)) enum timebase_nanoseconds { TIMEBASE_1_NS = 50, @@ -242,7 +228,7 @@ enum timebase_nanoseconds { static const int num_adc_stages_611x = 3; -static void ni_writel(struct comedi_device *dev, uint32_t data, int reg) +static void ni_writel(struct comedi_device *dev, unsigned int data, int reg) { if (dev->mmio) writel(data, dev->mmio + reg); @@ -250,7 +236,7 @@ static void ni_writel(struct comedi_device *dev, uint32_t data, int reg) outl(data, dev->iobase + reg); } -static void ni_writew(struct comedi_device *dev, uint16_t data, int reg) +static void ni_writew(struct comedi_device *dev, unsigned int data, int reg) { if (dev->mmio) writew(data, dev->mmio + reg); @@ -258,7 +244,7 @@ static void ni_writew(struct comedi_device *dev, uint16_t data, int reg) outw(data, dev->iobase + reg); } -static void ni_writeb(struct comedi_device *dev, uint8_t data, int reg) +static void ni_writeb(struct comedi_device *dev, unsigned int data, int reg) { if (dev->mmio) writeb(data, dev->mmio + reg); @@ -266,7 +252,7 @@ static void ni_writeb(struct comedi_device *dev, uint8_t data, int reg) outb(data, dev->iobase + reg); } -static uint32_t ni_readl(struct comedi_device *dev, int reg) +static unsigned int ni_readl(struct comedi_device *dev, int reg) { if (dev->mmio) return readl(dev->mmio + reg); @@ -274,7 +260,7 @@ static uint32_t ni_readl(struct comedi_device *dev, int reg) return inl(dev->iobase + reg); } -static uint16_t ni_readw(struct comedi_device *dev, int reg) +static unsigned int ni_readw(struct comedi_device *dev, int reg) { if (dev->mmio) return readw(dev->mmio + reg); @@ -282,7 +268,7 @@ static uint16_t ni_readw(struct comedi_device *dev, int reg) return inw(dev->iobase + reg); } -static uint8_t ni_readb(struct comedi_device *dev, int reg) +static unsigned int ni_readb(struct comedi_device *dev, int reg) { if (dev->mmio) return readb(dev->mmio + reg); @@ -457,7 +443,8 @@ static unsigned int m_series_stc_read(struct comedi_device *dev, } } -static void ni_stc_writew(struct comedi_device *dev, uint16_t data, int reg) +static void ni_stc_writew(struct comedi_device *dev, + unsigned int data, int reg) { struct ni_private *devpriv = dev->private; unsigned long flags; @@ -476,7 +463,8 @@ static void ni_stc_writew(struct comedi_device *dev, uint16_t data, int reg) } } -static void ni_stc_writel(struct comedi_device *dev, uint32_t data, int reg) +static void ni_stc_writel(struct comedi_device *dev, + unsigned int data, int reg) { struct ni_private *devpriv = dev->private; @@ -488,11 +476,11 @@ static void ni_stc_writel(struct comedi_device *dev, uint32_t data, int reg) } } -static uint16_t ni_stc_readw(struct comedi_device *dev, int reg) +static unsigned int ni_stc_readw(struct comedi_device *dev, int reg) { struct ni_private *devpriv = dev->private; unsigned long flags; - uint16_t val; + unsigned int val; if (devpriv->is_m_series) { val = m_series_stc_read(dev, reg); @@ -509,10 +497,10 @@ static uint16_t ni_stc_readw(struct comedi_device *dev, int reg) return val; } -static uint32_t ni_stc_readl(struct comedi_device *dev, int reg) +static unsigned int ni_stc_readl(struct comedi_device *dev, int reg) { struct ni_private *devpriv = dev->private; - uint32_t val; + unsigned int val; if (devpriv->is_m_series) { val = m_series_stc_read(dev, reg); @@ -524,7 +512,8 @@ static uint32_t ni_stc_readl(struct comedi_device *dev, int reg) } static inline void ni_set_bitfield(struct comedi_device *dev, int reg, - unsigned bit_mask, unsigned bit_values) + unsigned int bit_mask, + unsigned int bit_values) { struct ni_private *devpriv = dev->private; unsigned long flags; @@ -556,6 +545,11 @@ static inline void ni_set_bitfield(struct comedi_device *dev, int reg, devpriv->g0_g1_select_reg |= bit_values & bit_mask; ni_writeb(dev, devpriv->g0_g1_select_reg, reg); break; + case NI_M_CDIO_DMA_SEL_REG: + devpriv->cdio_dma_select_reg &= ~bit_mask; + devpriv->cdio_dma_select_reg |= bit_values & bit_mask; + ni_writeb(dev, devpriv->cdio_dma_select_reg, reg); + break; default: dev_err(dev->class_dev, "called with invalid register %d\n", reg); @@ -566,116 +560,35 @@ static inline void ni_set_bitfield(struct comedi_device *dev, int reg, } #ifdef PCIDMA -/* DMA channel setup */ -static inline unsigned ni_stc_dma_channel_select_bitfield(unsigned channel) -{ - if (channel < 4) - return 1 << channel; - if (channel == 4) - return 0x3; - if (channel == 5) - return 0x5; - BUG(); - return 0; -} - -static inline void ni_set_ai_dma_channel(struct comedi_device *dev, - unsigned channel) -{ - unsigned bits = ni_stc_dma_channel_select_bitfield(channel); - - ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG, - NI_E_DMA_AI_SEL_MASK, NI_E_DMA_AI_SEL(bits)); -} - -static inline void ni_set_ai_dma_no_channel(struct comedi_device *dev) -{ - ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG, NI_E_DMA_AI_SEL_MASK, 0); -} - -static inline void ni_set_ao_dma_channel(struct comedi_device *dev, - unsigned channel) -{ - unsigned bits = ni_stc_dma_channel_select_bitfield(channel); - - ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG, - NI_E_DMA_AO_SEL_MASK, NI_E_DMA_AO_SEL(bits)); -} - -static inline void ni_set_ao_dma_no_channel(struct comedi_device *dev) -{ - ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG, NI_E_DMA_AO_SEL_MASK, 0); -} - -static inline void ni_set_gpct_dma_channel(struct comedi_device *dev, - unsigned gpct_index, - unsigned channel) -{ - unsigned bits = ni_stc_dma_channel_select_bitfield(channel); - - ni_set_bitfield(dev, NI_E_DMA_G0_G1_SEL_REG, - NI_E_DMA_G0_G1_SEL_MASK(gpct_index), - NI_E_DMA_G0_G1_SEL(gpct_index, bits)); -} - -static inline void ni_set_gpct_dma_no_channel(struct comedi_device *dev, - unsigned gpct_index) -{ - ni_set_bitfield(dev, NI_E_DMA_G0_G1_SEL_REG, - NI_E_DMA_G0_G1_SEL_MASK(gpct_index), 0); -} - -static inline void ni_set_cdo_dma_channel(struct comedi_device *dev, - unsigned mite_channel) -{ - struct ni_private *devpriv = dev->private; - unsigned long flags; - unsigned bits; - - spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags); - devpriv->cdio_dma_select_reg &= ~NI_M_CDIO_DMA_SEL_CDO_MASK; - /* - * XXX just guessing ni_stc_dma_channel_select_bitfield() - * returns the right bits, under the assumption the cdio dma - * selection works just like ai/ao/gpct. - * Definitely works for dma channels 0 and 1. - */ - bits = ni_stc_dma_channel_select_bitfield(mite_channel); - devpriv->cdio_dma_select_reg |= NI_M_CDIO_DMA_SEL_CDO(bits); - ni_writeb(dev, devpriv->cdio_dma_select_reg, NI_M_CDIO_DMA_SEL_REG); - mmiowb(); - spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags); -} - -static inline void ni_set_cdo_dma_no_channel(struct comedi_device *dev) -{ - struct ni_private *devpriv = dev->private; - unsigned long flags; - spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags); - devpriv->cdio_dma_select_reg &= ~NI_M_CDIO_DMA_SEL_CDO_MASK; - ni_writeb(dev, devpriv->cdio_dma_select_reg, NI_M_CDIO_DMA_SEL_REG); - mmiowb(); - spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags); -} +/* selects the MITE channel to use for DMA */ +#define NI_STC_DMA_CHAN_SEL(x) (((x) < 4) ? BIT(x) : \ + ((x) == 4) ? 0x3 : \ + ((x) == 5) ? 0x5 : 0x0) +/* DMA channel setup */ static int ni_request_ai_mite_channel(struct comedi_device *dev) { struct ni_private *devpriv = dev->private; + struct mite_channel *mite_chan; unsigned long flags; + unsigned int bits; spin_lock_irqsave(&devpriv->mite_channel_lock, flags); - BUG_ON(devpriv->ai_mite_chan); - devpriv->ai_mite_chan = - mite_request_channel(devpriv->mite, devpriv->ai_mite_ring); - if (!devpriv->ai_mite_chan) { + mite_chan = mite_request_channel(devpriv->mite, devpriv->ai_mite_ring); + if (!mite_chan) { spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); dev_err(dev->class_dev, "failed to reserve mite dma channel for analog input\n"); return -EBUSY; } - devpriv->ai_mite_chan->dir = COMEDI_INPUT; - ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel); + mite_chan->dir = COMEDI_INPUT; + devpriv->ai_mite_chan = mite_chan; + + bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel); + ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG, + NI_E_DMA_AI_SEL_MASK, NI_E_DMA_AI_SEL(bits)); + spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); return 0; } @@ -683,37 +596,42 @@ static int ni_request_ai_mite_channel(struct comedi_device *dev) static int ni_request_ao_mite_channel(struct comedi_device *dev) { struct ni_private *devpriv = dev->private; + struct mite_channel *mite_chan; unsigned long flags; + unsigned int bits; spin_lock_irqsave(&devpriv->mite_channel_lock, flags); - BUG_ON(devpriv->ao_mite_chan); - devpriv->ao_mite_chan = - mite_request_channel(devpriv->mite, devpriv->ao_mite_ring); - if (!devpriv->ao_mite_chan) { + mite_chan = mite_request_channel(devpriv->mite, devpriv->ao_mite_ring); + if (!mite_chan) { spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); dev_err(dev->class_dev, "failed to reserve mite dma channel for analog outut\n"); return -EBUSY; } - devpriv->ao_mite_chan->dir = COMEDI_OUTPUT; - ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel); + mite_chan->dir = COMEDI_OUTPUT; + devpriv->ao_mite_chan = mite_chan; + + bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel); + ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG, + NI_E_DMA_AO_SEL_MASK, NI_E_DMA_AO_SEL(bits)); + spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); return 0; } static int ni_request_gpct_mite_channel(struct comedi_device *dev, - unsigned gpct_index, + unsigned int gpct_index, enum comedi_io_direction direction) { struct ni_private *devpriv = dev->private; - unsigned long flags; + struct ni_gpct *counter = &devpriv->counter_dev->counters[gpct_index]; struct mite_channel *mite_chan; + unsigned long flags; + unsigned int bits; spin_lock_irqsave(&devpriv->mite_channel_lock, flags); - BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan); - mite_chan = - mite_request_channel(devpriv->mite, - devpriv->gpct_mite_ring[gpct_index]); + mite_chan = mite_request_channel(devpriv->mite, + devpriv->gpct_mite_ring[gpct_index]); if (!mite_chan) { spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); dev_err(dev->class_dev, @@ -721,37 +639,50 @@ static int ni_request_gpct_mite_channel(struct comedi_device *dev, return -EBUSY; } mite_chan->dir = direction; - ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index], - mite_chan); - ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel); + ni_tio_set_mite_channel(counter, mite_chan); + + bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel); + ni_set_bitfield(dev, NI_E_DMA_G0_G1_SEL_REG, + NI_E_DMA_G0_G1_SEL_MASK(gpct_index), + NI_E_DMA_G0_G1_SEL(gpct_index, bits)); + spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); return 0; } -#endif /* PCIDMA */ - static int ni_request_cdo_mite_channel(struct comedi_device *dev) { -#ifdef PCIDMA struct ni_private *devpriv = dev->private; + struct mite_channel *mite_chan; unsigned long flags; + unsigned int bits; spin_lock_irqsave(&devpriv->mite_channel_lock, flags); - BUG_ON(devpriv->cdo_mite_chan); - devpriv->cdo_mite_chan = - mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring); - if (!devpriv->cdo_mite_chan) { + mite_chan = mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring); + if (!mite_chan) { spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); dev_err(dev->class_dev, "failed to reserve mite dma channel for correlated digital output\n"); return -EBUSY; } - devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT; - ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel); + mite_chan->dir = COMEDI_OUTPUT; + devpriv->cdo_mite_chan = mite_chan; + + /* + * XXX just guessing NI_STC_DMA_CHAN_SEL() + * returns the right bits, under the assumption the cdio dma + * selection works just like ai/ao/gpct. + * Definitely works for dma channels 0 and 1. + */ + bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel); + ni_set_bitfield(dev, NI_M_CDIO_DMA_SEL_REG, + NI_M_CDIO_DMA_SEL_CDO_MASK, + NI_M_CDIO_DMA_SEL_CDO(bits)); + spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); -#endif /* PCIDMA */ return 0; } +#endif /* PCIDMA */ static void ni_release_ai_mite_channel(struct comedi_device *dev) { @@ -761,7 +692,8 @@ static void ni_release_ai_mite_channel(struct comedi_device *dev) spin_lock_irqsave(&devpriv->mite_channel_lock, flags); if (devpriv->ai_mite_chan) { - ni_set_ai_dma_no_channel(dev); + ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG, + NI_E_DMA_AI_SEL_MASK, 0); mite_release_channel(devpriv->ai_mite_chan); devpriv->ai_mite_chan = NULL; } @@ -777,7 +709,8 @@ static void ni_release_ao_mite_channel(struct comedi_device *dev) spin_lock_irqsave(&devpriv->mite_channel_lock, flags); if (devpriv->ao_mite_chan) { - ni_set_ao_dma_no_channel(dev); + ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG, + NI_E_DMA_AO_SEL_MASK, 0); mite_release_channel(devpriv->ao_mite_chan); devpriv->ao_mite_chan = NULL; } @@ -787,7 +720,7 @@ static void ni_release_ao_mite_channel(struct comedi_device *dev) #ifdef PCIDMA static void ni_release_gpct_mite_channel(struct comedi_device *dev, - unsigned gpct_index) + unsigned int gpct_index) { struct ni_private *devpriv = dev->private; unsigned long flags; @@ -797,7 +730,8 @@ static void ni_release_gpct_mite_channel(struct comedi_device *dev, struct mite_channel *mite_chan = devpriv->counter_dev->counters[gpct_index].mite_chan; - ni_set_gpct_dma_no_channel(dev, gpct_index); + ni_set_bitfield(dev, NI_E_DMA_G0_G1_SEL_REG, + NI_E_DMA_G0_G1_SEL_MASK(gpct_index), 0); ni_tio_set_mite_channel(&devpriv-> counter_dev->counters[gpct_index], NULL); @@ -805,30 +739,27 @@ static void ni_release_gpct_mite_channel(struct comedi_device *dev, } spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); } -#endif /* PCIDMA */ static void ni_release_cdo_mite_channel(struct comedi_device *dev) { -#ifdef PCIDMA struct ni_private *devpriv = dev->private; unsigned long flags; spin_lock_irqsave(&devpriv->mite_channel_lock, flags); if (devpriv->cdo_mite_chan) { - ni_set_cdo_dma_no_channel(dev); + ni_set_bitfield(dev, NI_M_CDIO_DMA_SEL_REG, + NI_M_CDIO_DMA_SEL_CDO_MASK, 0); mite_release_channel(devpriv->cdo_mite_chan); devpriv->cdo_mite_chan = NULL; } spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); -#endif /* PCIDMA */ } -#ifdef PCIDMA static void ni_e_series_enable_second_irq(struct comedi_device *dev, - unsigned gpct_index, short enable) + unsigned int gpct_index, short enable) { struct ni_private *devpriv = dev->private; - uint16_t val = 0; + unsigned int val = 0; int reg; if (devpriv->is_m_series || gpct_index > 1) @@ -875,8 +806,10 @@ static void ni_clear_ai_fifo(struct comedi_device *dev) ni_writeb(dev, 0, NI_M_STATIC_AI_CTRL_REG(0)); ni_writeb(dev, 1, NI_M_STATIC_AI_CTRL_REG(0)); #if 0 - /* the NI example code does 3 convert pulses for 625x boards, - but that appears to be wrong in practice. */ + /* + * The NI example code does 3 convert pulses for 625x + * boards, But that appears to be wrong in practice. + */ ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, NISTC_AI_CMD1_REG); ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, @@ -888,8 +821,8 @@ static void ni_clear_ai_fifo(struct comedi_device *dev) } } -static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data, - int addr) +static inline void ni_ao_win_outw(struct comedi_device *dev, + unsigned int data, int addr) { struct ni_private *devpriv = dev->private; unsigned long flags; @@ -900,8 +833,8 @@ static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data, spin_unlock_irqrestore(&devpriv->window_lock, flags); } -static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data, - int addr) +static inline void ni_ao_win_outl(struct comedi_device *dev, + unsigned int data, int addr) { struct ni_private *devpriv = dev->private; unsigned long flags; @@ -925,20 +858,21 @@ static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr) return data; } -/* ni_set_bits( ) allows different parts of the ni_mio_common driver to -* share registers (such as Interrupt_A_Register) without interfering with -* each other. -* -* NOTE: the switch/case statements are optimized out for a constant argument -* so this is actually quite fast--- If you must wrap another function around this -* make it inline to avoid a large speed penalty. -* -* value should only be 1 or 0. -*/ +/* + * ni_set_bits( ) allows different parts of the ni_mio_common driver to + * share registers (such as Interrupt_A_Register) without interfering with + * each other. + * + * NOTE: the switch/case statements are optimized out for a constant argument + * so this is actually quite fast--- If you must wrap another function around + * this make it inline to avoid a large speed penalty. + * + * value should only be 1 or 0. + */ static inline void ni_set_bits(struct comedi_device *dev, int reg, - unsigned bits, unsigned value) + unsigned int bits, unsigned int value) { - unsigned bit_values; + unsigned int bit_values; if (value) bit_values = bits; @@ -956,7 +890,7 @@ static void ni_sync_ai_dma(struct comedi_device *dev) spin_lock_irqsave(&devpriv->mite_channel_lock, flags); if (devpriv->ai_mite_chan) - mite_sync_input_dma(devpriv->ai_mite_chan, s); + mite_sync_dma(devpriv->ai_mite_chan, s); spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); } @@ -972,9 +906,8 @@ static int ni_ai_drain_dma(struct comedi_device *dev) if (devpriv->ai_mite_chan) { for (i = 0; i < timeout; i++) { if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) & - NISTC_AI_STATUS1_FIFO_E) - && mite_bytes_in_transit(devpriv->ai_mite_chan) == - 0) + NISTC_AI_STATUS1_FIFO_E) && + mite_bytes_in_transit(devpriv->ai_mite_chan) == 0) break; udelay(5); } @@ -994,19 +927,6 @@ static int ni_ai_drain_dma(struct comedi_device *dev) return retval; } -static void mite_handle_b_linkc(struct mite_struct *mite, - struct comedi_device *dev) -{ - struct ni_private *devpriv = dev->private; - struct comedi_subdevice *s = dev->write_subdev; - unsigned long flags; - - spin_lock_irqsave(&devpriv->mite_channel_lock, flags); - if (devpriv->ao_mite_chan) - mite_sync_output_dma(devpriv->ao_mite_chan, s); - spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); -} - static int ni_ao_wait_for_dma_load(struct comedi_device *dev) { static const int timeout = 10000; @@ -1018,9 +938,11 @@ static int ni_ao_wait_for_dma_load(struct comedi_device *dev) b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG); if (b_status & NISTC_AO_STATUS1_FIFO_HF) break; - /* if we poll too often, the pci bus activity seems - to slow the dma transfer down */ - udelay(10); + /* + * If we poll too often, the pci bus activity seems + * to slow the dma transfer down. + */ + usleep_range(10, 100); } if (i == timeout) { dev_err(dev->class_dev, "timed out waiting for dma load\n"); @@ -1038,7 +960,7 @@ static void ni_ao_fifo_load(struct comedi_device *dev, struct ni_private *devpriv = dev->private; int i; unsigned short d; - u32 packed_data; + unsigned int packed_data; for (i = 0; i < n; i++) { comedi_buf_read_samples(s, &d, 1); @@ -1128,7 +1050,7 @@ static void ni_ai_fifo_read(struct comedi_device *dev, { struct ni_private *devpriv = dev->private; struct comedi_async *async = s->async; - u32 dl; + unsigned int dl; unsigned short data; int i; @@ -1148,7 +1070,10 @@ static void ni_ai_fifo_read(struct comedi_device *dev, comedi_buf_write_samples(s, &data, 1); } } else if (devpriv->is_6143) { - /* This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */ + /* + * This just reads the FIFO assuming the data is present, + * no checks on the FIFO status are performed. + */ for (i = 0; i < n / 2; i++) { dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG); @@ -1192,16 +1117,13 @@ static void ni_handle_fifo_half_full(struct comedi_device *dev) } #endif -/* - Empties the AI fifo -*/ +/* Empties the AI fifo */ static void ni_handle_fifo_dregs(struct comedi_device *dev) { struct ni_private *devpriv = dev->private; struct comedi_subdevice *s = dev->read_subdev; - u32 dl; + unsigned int dl; unsigned short data; - unsigned short fifo_empty; int i; if (devpriv->is_611x) { @@ -1237,15 +1159,16 @@ static void ni_handle_fifo_dregs(struct comedi_device *dev) } } else { - fifo_empty = ni_stc_readw(dev, NISTC_AI_STATUS1_REG) & - NISTC_AI_STATUS1_FIFO_E; - while (fifo_empty == 0) { + unsigned short fe; /* fifo empty */ + + fe = ni_stc_readw(dev, NISTC_AI_STATUS1_REG) & + NISTC_AI_STATUS1_FIFO_E; + while (fe == 0) { for (i = 0; i < ARRAY_SIZE(devpriv->ai_fifo_buffer); i++) { - fifo_empty = ni_stc_readw(dev, - NISTC_AI_STATUS1_REG) & - NISTC_AI_STATUS1_FIFO_E; - if (fifo_empty) + fe = ni_stc_readw(dev, NISTC_AI_STATUS1_REG) & + NISTC_AI_STATUS1_FIFO_E; + if (fe) break; devpriv->ai_fifo_buffer[i] = ni_readw(dev, NI_E_AI_FIFO_DATA_REG); @@ -1260,7 +1183,7 @@ static void get_last_sample_611x(struct comedi_device *dev) struct ni_private *devpriv = dev->private; struct comedi_subdevice *s = dev->read_subdev; unsigned short data; - u32 dl; + unsigned int dl; if (!devpriv->is_611x) return; @@ -1278,7 +1201,7 @@ static void get_last_sample_6143(struct comedi_device *dev) struct ni_private *devpriv = dev->private; struct comedi_subdevice *s = dev->read_subdev; unsigned short data; - u32 dl; + unsigned int dl; if (!devpriv->is_6143) return; @@ -1365,42 +1288,23 @@ static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status) ni_stc_writew(dev, ack, NISTC_INTA_ACK_REG); } -static void handle_a_interrupt(struct comedi_device *dev, unsigned short status, - unsigned ai_mite_status) +static void handle_a_interrupt(struct comedi_device *dev, + struct comedi_subdevice *s, + unsigned short status) { - struct comedi_subdevice *s = dev->read_subdev; struct comedi_cmd *cmd = &s->async->cmd; - /* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */ - if (s->type == COMEDI_SUBD_UNUSED) - return; - -#ifdef PCIDMA - if (ai_mite_status & CHSR_LINKC) - ni_sync_ai_dma(dev); - - if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY | - CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR | - CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) { - dev_err(dev->class_dev, - "unknown mite interrupt (ai_mite_status=%08x)\n", - ai_mite_status); - s->async->events |= COMEDI_CB_ERROR; - /* disable_irq(dev->irq); */ - } -#endif - /* test for all uncommon interrupt events at the same time */ if (status & (NISTC_AI_STATUS1_ERR | NISTC_AI_STATUS1_SC_TC | NISTC_AI_STATUS1_START1)) { if (status == 0xffff) { dev_err(dev->class_dev, "Card removed?\n"); - /* we probably aren't even running a command now, - * so it's a good idea to be careful. */ - if (comedi_is_subdevice_running(s)) { + /* + * We probably aren't even running a command now, + * so it's a good idea to be careful. + */ + if (comedi_is_subdevice_running(s)) s->async->events |= COMEDI_CB_ERROR; - comedi_handle_events(dev, s); - } return; } if (status & NISTC_AI_STATUS1_ERR) { @@ -1412,8 +1316,6 @@ static void handle_a_interrupt(struct comedi_device *dev, unsigned short status, s->async->events |= COMEDI_CB_ERROR; if (status & NISTC_AI_STATUS1_OVER) s->async->events |= COMEDI_CB_OVERFLOW; - - comedi_handle_events(dev, s); return; } if (status & NISTC_AI_STATUS1_SC_TC) { @@ -1425,8 +1327,11 @@ static void handle_a_interrupt(struct comedi_device *dev, unsigned short status, if (status & NISTC_AI_STATUS1_FIFO_HF) { int i; static const int timeout = 10; - /* pcmcia cards (at least 6036) seem to stop producing interrupts if we - *fail to get the fifo less than half full, so loop to be sure.*/ + /* + * PCMCIA cards (at least 6036) seem to stop producing + * interrupts if we fail to get the fifo less than half + * full, so loop to be sure. + */ for (i = 0; i < timeout; ++i) { ni_handle_fifo_half_full(dev); if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) & @@ -1438,8 +1343,6 @@ static void handle_a_interrupt(struct comedi_device *dev, unsigned short status, if (status & NISTC_AI_STATUS1_STOP) ni_handle_eos(dev, s); - - comedi_handle_events(dev, s); } static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status) @@ -1465,29 +1368,9 @@ static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status) } static void handle_b_interrupt(struct comedi_device *dev, - unsigned short b_status, unsigned ao_mite_status) + struct comedi_subdevice *s, + unsigned short b_status) { - struct comedi_subdevice *s = dev->write_subdev; - /* unsigned short ack=0; */ - -#ifdef PCIDMA - /* Currently, mite.c requires us to handle LINKC */ - if (ao_mite_status & CHSR_LINKC) { - struct ni_private *devpriv = dev->private; - - mite_handle_b_linkc(devpriv->mite, dev); - } - - if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY | - CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR | - CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) { - dev_err(dev->class_dev, - "unknown mite interrupt (ao_mite_status=%08x)\n", - ao_mite_status); - s->async->events |= COMEDI_CB_ERROR; - } -#endif - if (b_status == 0xffff) return; if (b_status & NISTC_AO_STATUS1_OVERRUN) { @@ -1515,8 +1398,6 @@ static void handle_b_interrupt(struct comedi_device *dev, } } #endif - - comedi_handle_events(dev, s); } static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s, @@ -1606,8 +1487,11 @@ static int ni_ao_setup_MITE_dma(struct comedi_device *dev) if (devpriv->is_611x || devpriv->is_6713) { mite_prep_dma(devpriv->ao_mite_chan, 32, 32); } else { - /* doing 32 instead of 16 bit wide transfers from memory - makes the mite do 32 bit pci transfers, doubling pci bandwidth. */ + /* + * Doing 32 instead of 16 bit wide transfers from + * memory makes the mite do 32 bit pci transfers, + * doubling pci bandwidth. + */ mite_prep_dma(devpriv->ao_mite_chan, 16, 32); } mite_dma_arm(devpriv->ao_mite_chan); @@ -1622,16 +1506,15 @@ static int ni_ao_setup_MITE_dma(struct comedi_device *dev) #endif /* PCIDMA */ /* - used for both cancel ioctl and board initialization - - this is pretty harsh for a cancel, but it works... + * used for both cancel ioctl and board initialization + * + * this is pretty harsh for a cancel, but it works... */ - static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s) { struct ni_private *devpriv = dev->private; - unsigned ai_personal; - unsigned ai_out_ctrl; + unsigned int ai_personal; + unsigned int ai_out_ctrl; ni_release_ai_mite_channel(dev); /* ai configuration */ @@ -1736,12 +1619,12 @@ static void ni_m_series_load_channelgain_list(struct comedi_device *dev, unsigned int chan, range, aref; unsigned int i; unsigned int dither; - unsigned range_code; + unsigned int range_code; ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG); if ((list[0] & CR_ALT_SOURCE)) { - unsigned bypass_bits; + unsigned int bypass_bits; chan = CR_CHAN(list[0]); range = CR_RANGE(list[0]); @@ -1760,7 +1643,7 @@ static void ni_m_series_load_channelgain_list(struct comedi_device *dev, ni_writel(dev, 0, NI_M_CFG_BYPASS_FIFO_REG); } for (i = 0; i < n_chan; i++) { - unsigned config_bits = 0; + unsigned int config_bits = 0; chan = CR_CHAN(list[i]); aref = CR_AREF(list[i]); @@ -1842,8 +1725,8 @@ static void ni_load_channelgain_list(struct comedi_device *dev, return; } if (n_chan == 1 && !devpriv->is_611x && !devpriv->is_6143) { - if (devpriv->changain_state - && devpriv->changain_spec == list[0]) { + if (devpriv->changain_state && + devpriv->changain_spec == list[0]) { /* ready to go. */ return; } @@ -1857,8 +1740,8 @@ static void ni_load_channelgain_list(struct comedi_device *dev, /* Set up Calibration mode if required */ if (devpriv->is_6143) { - if ((list[0] & CR_ALT_SOURCE) - && !devpriv->ai_calib_source_enabled) { + if ((list[0] & CR_ALT_SOURCE) && + !devpriv->ai_calib_source_enabled) { /* Strobe Relay enable bit */ ni_writew(dev, devpriv->ai_calib_source | NI6143_CALIB_CHAN_RELAY_ON, @@ -1866,9 +1749,10 @@ static void ni_load_channelgain_list(struct comedi_device *dev, ni_writew(dev, devpriv->ai_calib_source, NI6143_CALIB_CHAN_REG); devpriv->ai_calib_source_enabled = 1; - msleep_interruptible(100); /* Allow relays to change */ - } else if (!(list[0] & CR_ALT_SOURCE) - && devpriv->ai_calib_source_enabled) { + /* Allow relays to change */ + msleep_interruptible(100); + } else if (!(list[0] & CR_ALT_SOURCE) && + devpriv->ai_calib_source_enabled) { /* Strobe Relay disable bit */ ni_writew(dev, devpriv->ai_calib_source | NI6143_CALIB_CHAN_RELAY_OFF, @@ -1876,7 +1760,8 @@ static void ni_load_channelgain_list(struct comedi_device *dev, ni_writew(dev, devpriv->ai_calib_source, NI6143_CALIB_CHAN_REG); devpriv->ai_calib_source_enabled = 0; - msleep_interruptible(100); /* Allow relays to change */ + /* Allow relays to change */ + msleep_interruptible(100); } } @@ -1949,7 +1834,7 @@ static int ni_ai_insn_read(struct comedi_device *dev, struct ni_private *devpriv = dev->private; unsigned int mask = (s->maxdata + 1) >> 1; int i, n; - unsigned signbits; + unsigned int signbits; unsigned int d; unsigned long dl; @@ -1997,7 +1882,11 @@ static int ni_ai_insn_read(struct comedi_device *dev, ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, NISTC_AI_CMD1_REG); - /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */ + /* + * The 6143 has 32-bit FIFOs. You need to strobe a + * bit to move a single 16bit stranded sample into + * the FIFO. + */ dl = 0; for (i = 0; i < NI_TIMEOUT; i++) { if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & @@ -2035,7 +1924,8 @@ static int ni_ai_insn_read(struct comedi_device *dev, data[n] = dl; } else { d = ni_readw(dev, NI_E_AI_FIFO_DATA_REG); - d += signbits; /* subtle: needs to be short addition */ + /* subtle: needs to be short addition */ + d += signbits; data[n] = d; } } @@ -2043,8 +1933,8 @@ static int ni_ai_insn_read(struct comedi_device *dev, return insn->n; } -static int ni_ns_to_timer(const struct comedi_device *dev, unsigned nanosec, - unsigned int flags) +static int ni_ns_to_timer(const struct comedi_device *dev, + unsigned int nanosec, unsigned int flags) { struct ni_private *devpriv = dev->private; int divider; @@ -2064,14 +1954,14 @@ static int ni_ns_to_timer(const struct comedi_device *dev, unsigned nanosec, return divider - 1; } -static unsigned ni_timer_to_ns(const struct comedi_device *dev, int timer) +static unsigned int ni_timer_to_ns(const struct comedi_device *dev, int timer) { struct ni_private *devpriv = dev->private; return devpriv->clock_ns * (timer + 1); } -static void ni_cmd_set_mite_transfer(struct mite_dma_descriptor_ring *ring, +static void ni_cmd_set_mite_transfer(struct mite_ring *ring, struct comedi_subdevice *sdev, const struct comedi_cmd *cmd, unsigned int max_count) { @@ -2102,8 +1992,8 @@ static void ni_cmd_set_mite_transfer(struct mite_dma_descriptor_ring *ring, #endif } -static unsigned ni_min_ai_scan_period_ns(struct comedi_device *dev, - unsigned num_channels) +static unsigned int ni_min_ai_scan_period_ns(struct comedi_device *dev, + unsigned int num_channels) { const struct ni_board_struct *board = dev->board_ptr; struct ni_private *devpriv = dev->private; @@ -2294,7 +2184,7 @@ static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) int start_stop_select = 0; unsigned int stop_count; int interrupt_a_enable = 0; - unsigned ai_trig; + unsigned int ai_trig; if (dev->irq == 0) { dev_err(dev->class_dev, "cannot run command without an irq\n"); @@ -2307,8 +2197,10 @@ static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) /* start configuration */ ni_stc_writew(dev, NISTC_RESET_AI_CFG_START, NISTC_RESET_REG); - /* disable analog triggering for now, since it - * interferes with the use of pfi0 */ + /* + * Disable analog triggering for now, since it interferes + * with the use of pfi0. + */ devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_ENA; ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG); @@ -2369,7 +2261,10 @@ static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) if (stop_count == 0) { devpriv->ai_cmd2 |= NISTC_AI_CMD2_END_ON_EOS; interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP; - /* this is required to get the last sample for chanlist_len > 1, not sure why */ + /* + * This is required to get the last sample for + * chanlist_len > 1, not sure why. + */ if (cmd->chanlist_len > 1) start_stop_select |= NISTC_AI_STOP_POLARITY | NISTC_AI_STOP_EDGE; @@ -2489,7 +2384,7 @@ static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) switch (devpriv->aimode) { case AIMODE_HALF_FULL: - /*generate FIFO interrupts and DMA requests on half-full */ + /* FIFO interrupts and DMA requests on half-full */ #ifdef PCIDMA ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF_E, NISTC_AI_MODE3_REG); @@ -2880,9 +2775,11 @@ static int ni_ao_inttrig(struct comedi_device *dev, if (trig_num != cmd->start_arg) return -EINVAL; - /* Null trig at beginning prevent ao start trigger from executing more than - once per command (and doing things like trying to allocate the ao dma channel - multiple times) */ + /* + * Null trig at beginning prevent ao start trigger from executing more + * than once per command (and doing things like trying to allocate the + * ao dma channel multiple times). + */ s->async->inttrig = NULL; ni_set_bits(dev, NISTC_INTB_ENA_REG, @@ -2951,7 +2848,7 @@ static void ni_ao_cmd_personalize(struct comedi_device *dev, const struct comedi_cmd *cmd) { const struct ni_board_struct *board = dev->board_ptr; - unsigned bits; + unsigned int bits; ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG); @@ -2999,6 +2896,7 @@ static void ni_ao_cmd_set_trigger(struct comedi_device *dev, const struct comedi_cmd *cmd) { struct ni_private *devpriv = dev->private; + unsigned int trigsel; ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG); @@ -3012,39 +2910,20 @@ static void ni_ao_cmd_set_trigger(struct comedi_device *dev, } ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG); - { - unsigned int trigsel = devpriv->ao_trigger_select; - - switch (cmd->start_src) { - case TRIG_INT: - case TRIG_NOW: - trigsel &= ~(NISTC_AO_TRIG_START1_POLARITY | - NISTC_AO_TRIG_START1_SEL_MASK); - trigsel |= NISTC_AO_TRIG_START1_EDGE | - NISTC_AO_TRIG_START1_SYNC; - break; - case TRIG_EXT: - trigsel = NISTC_AO_TRIG_START1_SEL( - CR_CHAN(cmd->start_arg) + 1); - if (cmd->start_arg & CR_INVERT) - /* - * 0=active high, 1=active low. - * see daq-stc 3-24 (p186) - */ - trigsel |= NISTC_AO_TRIG_START1_POLARITY; - if (cmd->start_arg & CR_EDGE) - /* 0=edge detection disabled, 1=enabled */ - trigsel |= NISTC_AO_TRIG_START1_EDGE; - break; - default: - BUG(); - break; - } - - devpriv->ao_trigger_select = trigsel; - ni_stc_writew(dev, devpriv->ao_trigger_select, - NISTC_AO_TRIG_SEL_REG); + if (cmd->start_src == TRIG_INT) { + trigsel = NISTC_AO_TRIG_START1_EDGE | + NISTC_AO_TRIG_START1_SYNC; + } else { /* TRIG_EXT */ + trigsel = NISTC_AO_TRIG_START1_SEL(CR_CHAN(cmd->start_arg) + 1); + /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */ + if (cmd->start_arg & CR_INVERT) + trigsel |= NISTC_AO_TRIG_START1_POLARITY; + /* 0=edge detection disabled, 1=enabled */ + if (cmd->start_arg & CR_EDGE) + trigsel |= NISTC_AO_TRIG_START1_EDGE; } + ni_stc_writew(dev, trigsel, NISTC_AO_TRIG_SEL_REG); + /* AO_Delayed_START1 = 0, we do not support delayed start...yet */ /* sync */ @@ -3149,8 +3028,9 @@ static void ni_ao_cmd_set_update(struct comedi_device *dev, NISTC_AO_MODE1_UPDATE_SRC_POLARITY ); - switch (cmd->scan_begin_src) { - case TRIG_TIMER: + if (cmd->scan_begin_src == TRIG_TIMER) { + unsigned int trigvar; + devpriv->ao_cmd2 &= ~NISTC_AO_CMD2_BC_GATE_ENA; /* @@ -3181,34 +3061,25 @@ static void ni_ao_cmd_set_update(struct comedi_device *dev, * eseries/ni67xx and tMSeries.h for mseries. */ - { - unsigned trigvar = ni_ns_to_timer(dev, - cmd->scan_begin_arg, - CMDF_ROUND_NEAREST); + trigvar = ni_ns_to_timer(dev, cmd->scan_begin_arg, + CMDF_ROUND_NEAREST); - /* - * Wait N TB3 ticks after the start trigger before - * clocking(N must be >=2). - */ - /* following line: 2-1 per STC */ - ni_stc_writel(dev, 1, NISTC_AO_UI_LOADA_REG); - ni_stc_writew(dev, NISTC_AO_CMD1_UI_LOAD, - NISTC_AO_CMD1_REG); - /* following line: N-1 per STC */ - ni_stc_writel(dev, trigvar - 1, NISTC_AO_UI_LOADA_REG); - } - break; - case TRIG_EXT: + /* + * Wait N TB3 ticks after the start trigger before + * clocking (N must be >=2). + */ + /* following line: 2-1 per STC */ + ni_stc_writel(dev, 1, NISTC_AO_UI_LOADA_REG); + ni_stc_writew(dev, NISTC_AO_CMD1_UI_LOAD, NISTC_AO_CMD1_REG); + /* following line: N-1 per STC */ + ni_stc_writel(dev, trigvar - 1, NISTC_AO_UI_LOADA_REG); + } else { /* TRIG_EXT */ /* FIXME: assert scan_begin_arg != 0, ret failure otherwise */ devpriv->ao_cmd2 |= NISTC_AO_CMD2_BC_GATE_ENA; devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC( CR_CHAN(cmd->scan_begin_arg)); if (cmd->scan_begin_arg & CR_INVERT) devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC_POLARITY; - break; - default: - BUG(); - break; } ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG); @@ -3231,7 +3102,7 @@ static void ni_ao_cmd_set_channels(struct comedi_device *dev, { struct ni_private *devpriv = dev->private; const struct comedi_cmd *cmd = &s->async->cmd; - unsigned bits = 0; + unsigned int bits = 0; ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG); @@ -3474,7 +3345,6 @@ static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s) devpriv->ao_mode3 = NISTC_AO_MODE3_LAST_GATE_DISABLE; else devpriv->ao_mode3 = 0; - devpriv->ao_trigger_select = 0; ni_stc_writew(dev, 0, NISTC_AO_PERSONAL_REG); ni_stc_writew(dev, 0, NISTC_AO_CMD1_REG); @@ -3550,6 +3420,7 @@ static int ni_dio_insn_bits(struct comedi_device *dev, return insn->n; } +#ifdef PCIDMA static int ni_m_series_dio_insn_config(struct comedi_device *dev, struct comedi_subdevice *s, struct comedi_insn *insn, @@ -3652,13 +3523,11 @@ static int ni_cdo_inttrig(struct comedi_device *dev, unsigned int trig_num) { struct comedi_cmd *cmd = &s->async->cmd; - const unsigned timeout = 1000; + const unsigned int timeout = 1000; int retval = 0; - unsigned i; -#ifdef PCIDMA + unsigned int i; struct ni_private *devpriv = dev->private; unsigned long flags; -#endif if (trig_num != cmd->start_arg) return -EINVAL; @@ -3668,7 +3537,6 @@ static int ni_cdo_inttrig(struct comedi_device *dev, /* read alloc the entire buffer */ comedi_buf_read_alloc(s, s->async->prealloc_bufsz); -#ifdef PCIDMA spin_lock_irqsave(&devpriv->mite_channel_lock, flags); if (devpriv->cdo_mite_chan) { mite_prep_dma(devpriv->cdo_mite_chan, 32, 32); @@ -3680,7 +3548,7 @@ static int ni_cdo_inttrig(struct comedi_device *dev, spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); if (retval < 0) return retval; -#endif + /* * XXX not sure what interrupt C group does * wait for dma to fill output fifo @@ -3690,7 +3558,7 @@ static int ni_cdo_inttrig(struct comedi_device *dev, if (ni_readl(dev, NI_M_CDIO_STATUS_REG) & NI_M_CDIO_STATUS_CDO_FIFO_FULL) break; - udelay(10); + usleep_range(10, 100); } if (i == timeout) { dev_err(dev->class_dev, "dma failed to fill cdo fifo!\n"); @@ -3708,7 +3576,7 @@ static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s) { struct ni_private *devpriv = dev->private; const struct comedi_cmd *cmd = &s->async->cmd; - unsigned cdo_mode_bits; + unsigned int cdo_mode_bits; int retval; ni_writel(dev, NI_M_CDO_CMD_RESET, NI_M_CDIO_CMD_REG); @@ -3759,28 +3627,14 @@ static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s) static void handle_cdio_interrupt(struct comedi_device *dev) { struct ni_private *devpriv = dev->private; - unsigned cdio_status; + unsigned int cdio_status; struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV]; -#ifdef PCIDMA unsigned long flags; -#endif - if (!devpriv->is_m_series) - return; -#ifdef PCIDMA spin_lock_irqsave(&devpriv->mite_channel_lock, flags); - if (devpriv->cdo_mite_chan) { - unsigned cdo_mite_status = - mite_get_status(devpriv->cdo_mite_chan); - if (cdo_mite_status & CHSR_LINKC) { - writel(CHOR_CLRLC, - devpriv->mite->mite_io_addr + - MITE_CHOR(devpriv->cdo_mite_chan->channel)); - } - mite_sync_output_dma(devpriv->cdo_mite_chan, s); - } + if (devpriv->cdo_mite_chan) + mite_ack_linkc(devpriv->cdo_mite_chan, s, true); spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); -#endif cdio_status = ni_readl(dev, NI_M_CDIO_STATUS_REG); if (cdio_status & NI_M_CDIO_STATUS_CDO_ERROR) { @@ -3796,6 +3650,7 @@ static void handle_cdio_interrupt(struct comedi_device *dev) } comedi_handle_events(dev, s); } +#endif /* PCIDMA */ static int ni_serial_hw_readwrite8(struct comedi_device *dev, struct comedi_subdevice *s, @@ -3813,7 +3668,7 @@ static int ni_serial_hw_readwrite8(struct comedi_device *dev, status1 = ni_stc_readw(dev, NISTC_STATUS1_REG); if (status1 & NISTC_STATUS1_SERIO_IN_PROG) { err = -EBUSY; - goto Error; + goto error; } devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_START; @@ -3829,7 +3684,7 @@ static int ni_serial_hw_readwrite8(struct comedi_device *dev, dev_err(dev->class_dev, "SPI serial I/O didn't finish in time!\n"); err = -ETIME; - goto Error; + goto error; } } @@ -3842,7 +3697,7 @@ static int ni_serial_hw_readwrite8(struct comedi_device *dev, if (data_in) *data_in = ni_stc_readw(dev, NISTC_DIO_SERIAL_IN_REG); -Error: +error: ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG); return err; @@ -3860,16 +3715,20 @@ static int ni_serial_sw_readwrite8(struct comedi_device *dev, udelay((devpriv->serial_interval_ns + 999) / 1000); for (mask = 0x80; mask; mask >>= 1) { - /* Output current bit; note that we cannot touch s->state - because it is a per-subdevice field, and serial is - a separate subdevice from DIO. */ + /* + * Output current bit; note that we cannot touch s->state + * because it is a per-subdevice field, and serial is + * a separate subdevice from DIO. + */ devpriv->dio_output &= ~NISTC_DIO_SDOUT; if (data_out & mask) devpriv->dio_output |= NISTC_DIO_SDOUT; ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG); - /* Assert SDCLK (active low, inverted), wait for half of - the delay, deassert SDCLK, and wait for the other half. */ + /* + * Assert SDCLK (active low, inverted), wait for half of + * the delay, deassert SDCLK, and wait for the other half. + */ devpriv->dio_control |= NISTC_DIO_SDCLK; ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG); @@ -3897,7 +3756,7 @@ static int ni_serial_insn_config(struct comedi_device *dev, unsigned int *data) { struct ni_private *devpriv = dev->private; - unsigned clk_fout = devpriv->clock_and_fout; + unsigned int clk_fout = devpriv->clock_and_fout; int err = insn->n; unsigned char byte_out, byte_in = 0; @@ -3916,8 +3775,10 @@ static int ni_serial_insn_config(struct comedi_device *dev, data[1] = SERIAL_DISABLED; devpriv->serial_interval_ns = data[1]; } else if (data[1] <= SERIAL_600NS) { - /* Warning: this clock speed is too fast to reliably - control SCXI. */ + /* + * Warning: this clock speed is too fast to reliably + * control SCXI. + */ devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE; clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE; clk_fout &= ~NISTC_CLK_FOUT_DIO_SER_OUT_DIV2; @@ -3933,10 +3794,12 @@ static int ni_serial_insn_config(struct comedi_device *dev, devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_TIMEBASE; clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE | NISTC_CLK_FOUT_DIO_SER_OUT_DIV2; - /* Note: NISTC_CLK_FOUT_DIO_SER_OUT_DIV2 only affects - 600ns/1.2us. If you turn divide_by_2 off with the - slow clock, you will still get 10us, except then - all your delays are wrong. */ + /* + * Note: NISTC_CLK_FOUT_DIO_SER_OUT_DIV2 only affects + * 600ns/1.2us. If you turn divide_by_2 off with the + * slow clock, you will still get 10us, except then + * all your delays are wrong. + */ data[1] = SERIAL_10US; devpriv->serial_interval_ns = data[1]; } else { @@ -4046,15 +3909,11 @@ static unsigned int ni_gpct_to_stc_register(struct comedi_device *dev, return regmap->mio_reg; } -static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits, +static void ni_gpct_write_register(struct ni_gpct *counter, unsigned int bits, enum ni_gpct_register reg) { struct comedi_device *dev = counter->counter_dev->dev; unsigned int stc_register = ni_gpct_to_stc_register(dev, reg); - static const unsigned gpct_interrupt_a_enable_mask = - NISTC_INTA_ENA_G0_GATE | NISTC_INTA_ENA_G0_TC; - static const unsigned gpct_interrupt_b_enable_mask = - NISTC_INTB_ENA_G1_GATE | NISTC_INTB_ENA_G1_TC; if (stc_register == 0) return; @@ -4082,25 +3941,22 @@ static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits, /* 16 bit registers */ case NITIO_G0_INT_ENA: - BUG_ON(bits & ~gpct_interrupt_a_enable_mask); ni_set_bitfield(dev, stc_register, - gpct_interrupt_a_enable_mask, bits); + NISTC_INTA_ENA_G0_GATE | NISTC_INTA_ENA_G0_TC, + bits); break; case NITIO_G1_INT_ENA: - BUG_ON(bits & ~gpct_interrupt_b_enable_mask); ni_set_bitfield(dev, stc_register, - gpct_interrupt_b_enable_mask, bits); + NISTC_INTB_ENA_G1_GATE | NISTC_INTB_ENA_G1_TC, + bits); break; - case NITIO_G01_RESET: - BUG_ON(bits & ~(NISTC_RESET_G0 | NISTC_RESET_G1)); - /* fall-through */ default: ni_stc_writew(dev, bits, stc_register); } } -static unsigned ni_gpct_read_register(struct ni_gpct *counter, - enum ni_gpct_register reg) +static unsigned int ni_gpct_read_register(struct ni_gpct *counter, + enum ni_gpct_register reg) { struct comedi_device *dev = counter->counter_dev->dev; unsigned int stc_register = ni_gpct_to_stc_register(dev, reg); @@ -4227,7 +4083,7 @@ static int ni_m_series_pwm_config(struct comedi_device *dev, unsigned int *data) { struct ni_private *devpriv = dev->private; - unsigned up_count, down_count; + unsigned int up_count, down_count; switch (data[0]) { case INSN_CONFIG_PWM_OUTPUT: @@ -4287,7 +4143,7 @@ static int ni_6143_pwm_config(struct comedi_device *dev, unsigned int *data) { struct ni_private *devpriv = dev->private; - unsigned up_count, down_count; + unsigned int up_count, down_count; switch (data[0]) { case INSN_CONFIG_PWM_OUTPUT: @@ -4343,13 +4199,13 @@ static int ni_6143_pwm_config(struct comedi_device *dev, static int pack_mb88341(int addr, int val, int *bitstring) { /* - Fujitsu MB 88341 - Note that address bits are reversed. Thanks to - Ingo Keen for noticing this. - - Note also that the 88341 expects address values from - 1-12, whereas we use channel numbers 0-11. The NI - docs use 1-12, also, so be careful here. + * Fujitsu MB 88341 + * Note that address bits are reversed. Thanks to + * Ingo Keen for noticing this. + * + * Note also that the 88341 expects address values from + * 1-12, whereas we use channel numbers 0-11. The NI + * docs use 1-12, also, so be careful here. */ addr++; *bitstring = ((addr & 0x1) << 11) | @@ -4495,12 +4351,12 @@ static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s) s->n_chan = n_chans; if (diffbits) { - unsigned int *maxdata_list; + unsigned int *maxdata_list = devpriv->caldac_maxdata_list; if (n_chans > MAX_N_CALDACS) dev_err(dev->class_dev, "BUG! MAX_N_CALDACS too small\n"); - s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list; + s->maxdata_list = maxdata_list; chan = 0; for (i = 0; i < n_dacs; i++) { type = board->caldac[i]; @@ -4574,8 +4430,8 @@ static int ni_m_series_eeprom_insn_read(struct comedi_device *dev, return 1; } -static unsigned ni_old_get_pfi_routing(struct comedi_device *dev, - unsigned chan) +static unsigned int ni_old_get_pfi_routing(struct comedi_device *dev, + unsigned int chan) { /* pre-m-series boards have fixed signals on pfi pins */ switch (chan) { @@ -4607,7 +4463,7 @@ static unsigned ni_old_get_pfi_routing(struct comedi_device *dev, } static int ni_old_set_pfi_routing(struct comedi_device *dev, - unsigned chan, unsigned source) + unsigned int chan, unsigned int source) { /* pre-m-series boards have fixed signals on pfi pins */ if (source != ni_old_get_pfi_routing(dev, chan)) @@ -4615,21 +4471,21 @@ static int ni_old_set_pfi_routing(struct comedi_device *dev, return 2; } -static unsigned ni_m_series_get_pfi_routing(struct comedi_device *dev, - unsigned chan) +static unsigned int ni_m_series_get_pfi_routing(struct comedi_device *dev, + unsigned int chan) { struct ni_private *devpriv = dev->private; - const unsigned array_offset = chan / 3; + const unsigned int array_offset = chan / 3; return NI_M_PFI_OUT_SEL_TO_SRC(chan, devpriv->pfi_output_select_reg[array_offset]); } static int ni_m_series_set_pfi_routing(struct comedi_device *dev, - unsigned chan, unsigned source) + unsigned int chan, unsigned int source) { struct ni_private *devpriv = dev->private; - unsigned index = chan / 3; + unsigned int index = chan / 3; unsigned short val = devpriv->pfi_output_select_reg[index]; if ((source & 0x1f) != source) @@ -4643,7 +4499,8 @@ static int ni_m_series_set_pfi_routing(struct comedi_device *dev, return 2; } -static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan) +static unsigned int ni_get_pfi_routing(struct comedi_device *dev, + unsigned int chan) { struct ni_private *devpriv = dev->private; @@ -4652,8 +4509,8 @@ static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan) : ni_old_get_pfi_routing(dev, chan); } -static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan, - unsigned source) +static int ni_set_pfi_routing(struct comedi_device *dev, + unsigned int chan, unsigned int source) { struct ni_private *devpriv = dev->private; @@ -4663,11 +4520,11 @@ static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan, } static int ni_config_filter(struct comedi_device *dev, - unsigned pfi_channel, + unsigned int pfi_channel, enum ni_pfi_filter_select filter) { struct ni_private *devpriv = dev->private; - unsigned bits; + unsigned int bits; if (!devpriv->is_m_series) return -ENOTSUPP; @@ -4818,9 +4675,12 @@ static int cs5529_ai_insn_read(struct comedi_device *dev, unsigned int channel_select; const unsigned int INTERNAL_REF = 0x1000; - /* Set calibration adc source. Docs lie, reference select bits 8 to 11 + /* + * Set calibration adc source. Docs lie, reference select bits 8 to 11 * do nothing. bit 12 seems to chooses internal reference voltage, bit - * 13 causes the adc input to go overrange (maybe reads external reference?) */ + * 13 causes the adc input to go overrange (maybe reads external + * reference?) + */ if (insn->chanspec & CR_ALT_SOURCE) channel_select = INTERNAL_REF; else @@ -4875,27 +4735,28 @@ static int init_cs5529(struct comedi_device *dev) * Find best multiplier/divider to try and get the PLL running at 80 MHz * given an arbitrary frequency input clock. */ -static int ni_mseries_get_pll_parameters(unsigned reference_period_ns, - unsigned *freq_divider, - unsigned *freq_multiplier, - unsigned *actual_period_ns) -{ - unsigned div; - unsigned best_div = 1; - unsigned mult; - unsigned best_mult = 1; - static const unsigned pico_per_nano = 1000; - - const unsigned reference_picosec = reference_period_ns * pico_per_nano; - /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to - * 20 MHz for most timing clocks */ - static const unsigned target_picosec = 12500; - static const unsigned fudge_factor_80_to_20Mhz = 4; +static int ni_mseries_get_pll_parameters(unsigned int reference_period_ns, + unsigned int *freq_divider, + unsigned int *freq_multiplier, + unsigned int *actual_period_ns) +{ + unsigned int div; + unsigned int best_div = 1; + unsigned int mult; + unsigned int best_mult = 1; + static const unsigned int pico_per_nano = 1000; + const unsigned int reference_picosec = reference_period_ns * + pico_per_nano; + /* + * m-series wants the phased-locked loop to output 80MHz, which is + * divided by 4 to 20 MHz for most timing clocks + */ + static const unsigned int target_picosec = 12500; int best_period_picosec = 0; for (div = 1; div <= NI_M_PLL_MAX_DIVISOR; ++div) { for (mult = 1; mult <= NI_M_PLL_MAX_MULTIPLIER; ++mult) { - unsigned new_period_ps = + unsigned int new_period_ps = (reference_picosec * div) / mult; if (abs(new_period_ps - target_picosec) < abs(best_period_picosec - target_picosec)) { @@ -4910,29 +4771,33 @@ static int ni_mseries_get_pll_parameters(unsigned reference_period_ns, *freq_divider = best_div; *freq_multiplier = best_mult; - *actual_period_ns = DIV_ROUND_CLOSEST(best_period_picosec * - fudge_factor_80_to_20Mhz, + /* return the actual period (* fudge factor for 80 to 20 MHz) */ + *actual_period_ns = DIV_ROUND_CLOSEST(best_period_picosec * 4, pico_per_nano); return 0; } static int ni_mseries_set_pll_master_clock(struct comedi_device *dev, - unsigned source, unsigned period_ns) + unsigned int source, + unsigned int period_ns) { struct ni_private *devpriv = dev->private; - static const unsigned min_period_ns = 50; - static const unsigned max_period_ns = 1000; - static const unsigned timeout = 1000; - unsigned pll_control_bits; - unsigned freq_divider; - unsigned freq_multiplier; - unsigned rtsi; - unsigned i; + static const unsigned int min_period_ns = 50; + static const unsigned int max_period_ns = 1000; + static const unsigned int timeout = 1000; + unsigned int pll_control_bits; + unsigned int freq_divider; + unsigned int freq_multiplier; + unsigned int rtsi; + unsigned int i; int retval; if (source == NI_MIO_PLL_PXI10_CLOCK) period_ns = 100; - /* these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */ + /* + * These limits are somewhat arbitrary, but NI advertises 1 to 20MHz + * range so we'll use that. + */ if (period_ns < min_period_ns || period_ns > max_period_ns) { dev_err(dev->class_dev, "%s: you must specify an input clock frequency between %i and %i nanosec for the phased-lock loop\n", @@ -4982,7 +4847,7 @@ static int ni_mseries_set_pll_master_clock(struct comedi_device *dev, ni_writew(dev, pll_control_bits, NI_M_PLL_CTRL_REG); devpriv->clock_source = source; - /* it seems to typically take a few hundred microseconds for PLL to lock */ + /* it takes a few hundred microseconds for PLL to lock */ for (i = 0; i < timeout; ++i) { if (ni_readw(dev, NI_M_PLL_STATUS_REG) & NI_M_PLL_STATUS_LOCKED) break; @@ -4998,7 +4863,7 @@ static int ni_mseries_set_pll_master_clock(struct comedi_device *dev, } static int ni_set_master_clock(struct comedi_device *dev, - unsigned source, unsigned period_ns) + unsigned int source, unsigned int period_ns) { struct ni_private *devpriv = dev->private; @@ -5043,7 +4908,7 @@ static int ni_set_master_clock(struct comedi_device *dev, } static int ni_valid_rtsi_output_source(struct comedi_device *dev, - unsigned chan, unsigned source) + unsigned int chan, unsigned int source) { struct ni_private *devpriv = dev->private; @@ -5078,7 +4943,7 @@ static int ni_valid_rtsi_output_source(struct comedi_device *dev, } static int ni_set_rtsi_routing(struct comedi_device *dev, - unsigned chan, unsigned src) + unsigned int chan, unsigned int src) { struct ni_private *devpriv = dev->private; @@ -5098,7 +4963,8 @@ static int ni_set_rtsi_routing(struct comedi_device *dev, return 2; } -static unsigned ni_get_rtsi_routing(struct comedi_device *dev, unsigned chan) +static unsigned int ni_get_rtsi_routing(struct comedi_device *dev, + unsigned int chan) { struct ni_private *devpriv = dev->private; @@ -5262,10 +5128,10 @@ static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s) static irqreturn_t ni_E_interrupt(int irq, void *d) { struct comedi_device *dev = d; + struct comedi_subdevice *s_ai = dev->read_subdev; + struct comedi_subdevice *s_ao = dev->write_subdev; unsigned short a_status; unsigned short b_status; - unsigned int ai_mite_status = 0; - unsigned int ao_mite_status = 0; unsigned long flags; #ifdef PCIDMA struct ni_private *devpriv = dev->private; @@ -5273,7 +5139,7 @@ static irqreturn_t ni_E_interrupt(int irq, void *d) if (!dev->attached) return IRQ_NONE; - smp_mb(); /* make sure dev->attached is checked before handler does anything else. */ + smp_mb(); /* make sure dev->attached is checked */ /* lock to avoid race with comedi_poll */ spin_lock_irqsave(&dev->spinlock, flags); @@ -5284,34 +5150,33 @@ static irqreturn_t ni_E_interrupt(int irq, void *d) unsigned long flags_too; spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too); - if (devpriv->ai_mite_chan) { - ai_mite_status = mite_get_status(devpriv->ai_mite_chan); - if (ai_mite_status & CHSR_LINKC) - writel(CHOR_CLRLC, - devpriv->mite->mite_io_addr + - MITE_CHOR(devpriv-> - ai_mite_chan->channel)); - } - if (devpriv->ao_mite_chan) { - ao_mite_status = mite_get_status(devpriv->ao_mite_chan); - if (ao_mite_status & CHSR_LINKC) - writel(CHOR_CLRLC, - devpriv->mite->mite_io_addr + - MITE_CHOR(devpriv-> - ao_mite_chan->channel)); - } + if (s_ai && devpriv->ai_mite_chan) + mite_ack_linkc(devpriv->ai_mite_chan, s_ai, false); + if (s_ao && devpriv->ao_mite_chan) + mite_ack_linkc(devpriv->ao_mite_chan, s_ao, false); spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too); } #endif ack_a_interrupt(dev, a_status); ack_b_interrupt(dev, b_status); - if ((a_status & NISTC_AI_STATUS1_INTA) || (ai_mite_status & CHSR_INT)) - handle_a_interrupt(dev, a_status, ai_mite_status); - if ((b_status & NISTC_AO_STATUS1_INTB) || (ao_mite_status & CHSR_INT)) - handle_b_interrupt(dev, b_status, ao_mite_status); + if (s_ai) { + if (a_status & NISTC_AI_STATUS1_INTA) + handle_a_interrupt(dev, s_ai, a_status); + /* handle any interrupt or dma events */ + comedi_handle_events(dev, s_ai); + } + if (s_ao) { + if (b_status & NISTC_AO_STATUS1_INTB) + handle_b_interrupt(dev, s_ao, b_status); + /* handle any interrupt or dma events */ + comedi_handle_events(dev, s_ao); + } handle_gpct_interrupt(dev, 0); handle_gpct_interrupt(dev, 1); - handle_cdio_interrupt(dev); +#ifdef PCIDMA + if (devpriv->is_m_series) + handle_cdio_interrupt(dev); +#endif spin_unlock_irqrestore(&dev->spinlock, flags); return IRQ_HANDLED; @@ -5333,7 +5198,7 @@ static int ni_alloc_private(struct comedi_device *dev) } static int ni_E_init(struct comedi_device *dev, - unsigned interrupt_pin, unsigned irq_polarity) + unsigned int interrupt_pin, unsigned int irq_polarity) { const struct ni_board_struct *board = dev->board_ptr; struct ni_private *devpriv = dev->private; @@ -5450,6 +5315,7 @@ static int ni_E_init(struct comedi_device *dev, s->maxdata = 1; s->range_table = &range_digital; if (devpriv->is_m_series) { +#ifdef PCIDMA s->subdev_flags |= SDF_LSAMPL; s->insn_bits = ni_m_series_dio_insn_bits; s->insn_config = ni_m_series_dio_insn_config; @@ -5469,6 +5335,7 @@ static int ni_E_init(struct comedi_device *dev, NI_M_CDI_CMD_RESET, NI_M_CDIO_CMD_REG); ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG); +#endif /* PCIDMA */ } else { s->insn_bits = ni_dio_insn_bits; s->insn_config = ni_dio_insn_config; @@ -5675,8 +5542,6 @@ static void mio_common_detach(struct comedi_device *dev) { struct ni_private *devpriv = dev->private; - if (devpriv) { - if (devpriv->counter_dev) - ni_gpct_device_destroy(devpriv->counter_dev); - } + if (devpriv) + ni_gpct_device_destroy(devpriv->counter_dev); } diff --git a/drivers/staging/comedi/drivers/ni_pcidio.c b/drivers/staging/comedi/drivers/ni_pcidio.c index 7112c3fec8bb..02a532990979 100644 --- a/drivers/staging/comedi/drivers/ni_pcidio.c +++ b/drivers/staging/comedi/drivers/ni_pcidio.c @@ -284,12 +284,12 @@ static const struct nidio_board nidio_boards[] = { }; struct nidio96_private { - struct mite_struct *mite; + struct mite *mite; int boardtype; int dio; unsigned short OpModeBits; struct mite_channel *di_mite_chan; - struct mite_dma_descriptor_ring *di_mite_ring; + struct mite_ring *di_mite_ring; spinlock_t mite_channel_lock; }; @@ -324,8 +324,6 @@ static void ni_pcidio_release_di_mite_channel(struct comedi_device *dev) spin_lock_irqsave(&devpriv->mite_channel_lock, flags); if (devpriv->di_mite_chan) { - mite_dma_disarm(devpriv->di_mite_chan); - mite_dma_reset(devpriv->di_mite_chan); mite_release_channel(devpriv->di_mite_chan); devpriv->di_mite_chan = NULL; writeb(primary_DMAChannel_bits(0) | @@ -370,7 +368,7 @@ static int ni_pcidio_poll(struct comedi_device *dev, struct comedi_subdevice *s) spin_lock_irqsave(&dev->spinlock, irq_flags); spin_lock(&devpriv->mite_channel_lock); if (devpriv->di_mite_chan) - mite_sync_input_dma(devpriv->di_mite_chan, s); + mite_sync_dma(devpriv->di_mite_chan, s); spin_unlock(&devpriv->mite_channel_lock); count = comedi_buf_n_bytes_ready(s); spin_unlock_irqrestore(&dev->spinlock, irq_flags); @@ -383,12 +381,10 @@ static irqreturn_t nidio_interrupt(int irq, void *d) struct nidio96_private *devpriv = dev->private; struct comedi_subdevice *s = dev->read_subdev; struct comedi_async *async = s->async; - struct mite_struct *mite = devpriv->mite; unsigned int auxdata; int flags; int status; int work = 0; - unsigned int m_status = 0; /* interrupcions parasites */ if (!dev->attached) { @@ -403,24 +399,9 @@ static irqreturn_t nidio_interrupt(int irq, void *d) flags = readb(dev->mmio + Group_1_Flags); spin_lock(&devpriv->mite_channel_lock); - if (devpriv->di_mite_chan) - m_status = mite_get_status(devpriv->di_mite_chan); - - if (m_status & CHSR_INT) { - if (m_status & CHSR_LINKC) { - writel(CHOR_CLRLC, - mite->mite_io_addr + - MITE_CHOR(devpriv->di_mite_chan->channel)); - mite_sync_input_dma(devpriv->di_mite_chan, s); - /* XXX need to byteswap */ - } - if (m_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_DRDY | - CHSR_DRQ1 | CHSR_MRDY)) { - dev_dbg(dev->class_dev, - "unknown mite interrupt, disabling IRQ\n"); - async->events |= COMEDI_CB_ERROR; - disable_irq(dev->irq); - } + if (devpriv->di_mite_chan) { + mite_ack_linkc(devpriv->di_mite_chan, s, false); + /* XXX need to byteswap sync'ed dma */ } spin_unlock(&devpriv->mite_channel_lock); @@ -916,14 +897,10 @@ static int nidio_auto_attach(struct comedi_device *dev, spin_lock_init(&devpriv->mite_channel_lock); - devpriv->mite = mite_alloc(pcidev); + devpriv->mite = mite_attach(dev, false); /* use win0 */ if (!devpriv->mite) return -ENOMEM; - ret = mite_setup(dev, devpriv->mite); - if (ret < 0) - return ret; - devpriv->di_mite_ring = mite_alloc_ring(devpriv->mite); if (!devpriv->di_mite_ring) return -ENOMEM; diff --git a/drivers/staging/comedi/drivers/ni_pcimio.c b/drivers/staging/comedi/drivers/ni_pcimio.c index 231e37d6b7c6..344aa343e5e1 100644 --- a/drivers/staging/comedi/drivers/ni_pcimio.c +++ b/drivers/staging/comedi/drivers/ni_pcimio.c @@ -1061,6 +1061,8 @@ static int pcimio_dio_change(struct comedi_device *dev, static void m_series_init_eeprom_buffer(struct comedi_device *dev) { struct ni_private *devpriv = dev->private; + struct mite *mite = devpriv->mite; + resource_size_t daq_phys_addr; static const int Start_Cal_EEPROM = 0x400; static const unsigned window_size = 10; static const int serial_number_eeprom_offset = 0x4; @@ -1070,15 +1072,17 @@ static void m_series_init_eeprom_buffer(struct comedi_device *dev) unsigned old_iodwcr1_bits; int i; - old_iodwbsr_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWBSR); - old_iodwbsr1_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWBSR_1); - old_iodwcr1_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWCR_1); - writel(0x0, devpriv->mite->mite_io_addr + MITE_IODWBSR); - writel(((0x80 | window_size) | devpriv->mite->daq_phys_addr), - devpriv->mite->mite_io_addr + MITE_IODWBSR_1); - writel(0x1 | old_iodwcr1_bits, - devpriv->mite->mite_io_addr + MITE_IODWCR_1); - writel(0xf, devpriv->mite->mite_io_addr + 0x30); + /* IO Window 1 needs to be temporarily mapped to read the eeprom */ + daq_phys_addr = pci_resource_start(mite->pcidev, 1); + + old_iodwbsr_bits = readl(mite->mmio + MITE_IODWBSR); + old_iodwbsr1_bits = readl(mite->mmio + MITE_IODWBSR_1); + old_iodwcr1_bits = readl(mite->mmio + MITE_IODWCR_1); + writel(0x0, mite->mmio + MITE_IODWBSR); + writel(((0x80 | window_size) | daq_phys_addr), + mite->mmio + MITE_IODWBSR_1); + writel(0x1 | old_iodwcr1_bits, mite->mmio + MITE_IODWCR_1); + writel(0xf, mite->mmio + 0x30); BUG_ON(serial_number_eeprom_length > sizeof(devpriv->serial_number)); for (i = 0; i < serial_number_eeprom_length; ++i) { @@ -1090,10 +1094,10 @@ static void m_series_init_eeprom_buffer(struct comedi_device *dev) for (i = 0; i < M_SERIES_EEPROM_SIZE; ++i) devpriv->eeprom_buffer[i] = ni_readb(dev, Start_Cal_EEPROM + i); - writel(old_iodwbsr1_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR_1); - writel(old_iodwbsr_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR); - writel(old_iodwcr1_bits, devpriv->mite->mite_io_addr + MITE_IODWCR_1); - writel(0x0, devpriv->mite->mite_io_addr + 0x30); + writel(old_iodwbsr1_bits, mite->mmio + MITE_IODWBSR_1); + writel(old_iodwbsr_bits, mite->mmio + MITE_IODWBSR); + writel(old_iodwcr1_bits, mite->mmio + MITE_IODWCR_1); + writel(0x0, mite->mmio + 0x30); } static void init_6143(struct comedi_device *dev) @@ -1168,7 +1172,7 @@ static int pcimio_auto_attach(struct comedi_device *dev, return ret; devpriv = dev->private; - devpriv->mite = mite_alloc(pcidev); + devpriv->mite = mite_attach(dev, false); /* use win0 */ if (!devpriv->mite) return -ENOMEM; @@ -1193,10 +1197,6 @@ static int pcimio_auto_attach(struct comedi_device *dev, if (board->reg_type == ni_reg_6713) devpriv->is_6713 = 1; - ret = mite_setup(dev, devpriv->mite); - if (ret < 0) - return ret; - devpriv->ai_mite_ring = mite_alloc_ring(devpriv->mite); if (!devpriv->ai_mite_ring) return -ENOMEM; diff --git a/drivers/staging/comedi/drivers/ni_stc.h b/drivers/staging/comedi/drivers/ni_stc.h index 1d5af25b92a8..1966519cb6e5 100644 --- a/drivers/staging/comedi/drivers/ni_stc.h +++ b/drivers/staging/comedi/drivers/ni_stc.h @@ -1,24 +1,23 @@ /* - module/ni_stc.h - Register descriptions for NI DAQ-STC chip - - COMEDI - Linux Control and Measurement Device Interface - Copyright (C) 1998-9 David A. Schleef <ds@schleef.org> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*/ + * Register descriptions for NI DAQ-STC chip + * + * COMEDI - Linux Control and Measurement Device Interface + * Copyright (C) 1998-9 David A. Schleef <ds@schleef.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ /* - References: - DAQ-STC Technical Reference Manual + * References: + * DAQ-STC Technical Reference Manual */ #ifndef _COMEDI_NI_STC_H @@ -958,7 +957,7 @@ struct ni_board_struct { unsigned int ao_maxdata; int ao_fifo_depth; const struct comedi_lrange *ao_range_table; - unsigned ao_speed; + unsigned int ao_speed; int reg_type; unsigned int has_8255:1; @@ -1002,12 +1001,11 @@ struct ni_private { unsigned short ao_mode3; unsigned short ao_cmd1; unsigned short ao_cmd2; - unsigned short ao_trigger_select; struct ni_gpct_device *counter_dev; unsigned short an_trig_etc_reg; - unsigned ai_offset[512]; + unsigned int ai_offset[512]; unsigned long serial_interval_ns; unsigned char serial_hw_mode; @@ -1025,24 +1023,24 @@ struct ni_private { unsigned short g0_g1_select_reg; unsigned short cdio_dma_select_reg; - unsigned clock_ns; - unsigned clock_source; + unsigned int clock_ns; + unsigned int clock_source; unsigned short pwm_up_count; unsigned short pwm_down_count; unsigned short ai_fifo_buffer[0x2000]; - uint8_t eeprom_buffer[M_SERIES_EEPROM_SIZE]; + u8 eeprom_buffer[M_SERIES_EEPROM_SIZE]; __be32 serial_number; - struct mite_struct *mite; + struct mite *mite; struct mite_channel *ai_mite_chan; struct mite_channel *ao_mite_chan; struct mite_channel *cdo_mite_chan; - struct mite_dma_descriptor_ring *ai_mite_ring; - struct mite_dma_descriptor_ring *ao_mite_ring; - struct mite_dma_descriptor_ring *cdo_mite_ring; - struct mite_dma_descriptor_ring *gpct_mite_ring[NUM_GPCT]; + struct mite_ring *ai_mite_ring; + struct mite_ring *ao_mite_ring; + struct mite_ring *cdo_mite_ring; + struct mite_ring *gpct_mite_ring[NUM_GPCT]; /* ni_pcimio board type flags (based on the boardinfo reg_type) */ unsigned int is_m_series:1; diff --git a/drivers/staging/comedi/drivers/ni_tio.c b/drivers/staging/comedi/drivers/ni_tio.c index b74e44ec521a..7043eb0543f6 100644 --- a/drivers/staging/comedi/drivers/ni_tio.c +++ b/drivers/staging/comedi/drivers/ni_tio.c @@ -1,19 +1,18 @@ /* - comedi/drivers/ni_tio.c - Support for NI general purpose counters - - Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*/ + * Support for NI general purpose counters + * + * Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ /* * Module: ni_tio @@ -36,13 +35,10 @@ * DAQ 660x Register-Level Programmer Manual (NI 370505A-01) * DAQ 6601/6602 User Manual (NI 322137B-01) * 340934b.pdf DAQ-STC reference manual + * + * TODO: Support use of both banks X and Y */ -/* -TODO: - Support use of both banks X and Y -*/ - #include <linux/module.h> #include <linux/slab.h> @@ -115,20 +111,7 @@ TODO: #define NI_660X_LOGIC_LOW_GATE2_SEL 0x1f #define NI_660X_MAX_UP_DOWN_PIN 7 -static inline unsigned GI_ALT_SYNC(enum ni_gpct_variant variant) -{ - switch (variant) { - case ni_gpct_variant_e_series: - default: - return 0; - case ni_gpct_variant_m_series: - return GI_M_ALT_SYNC; - case ni_gpct_variant_660x: - return GI_660X_ALT_SYNC; - } -} - -static inline unsigned GI_PRESCALE_X2(enum ni_gpct_variant variant) +static inline unsigned int GI_PRESCALE_X2(enum ni_gpct_variant variant) { switch (variant) { case ni_gpct_variant_e_series: @@ -141,7 +124,7 @@ static inline unsigned GI_PRESCALE_X2(enum ni_gpct_variant variant) } } -static inline unsigned GI_PRESCALE_X8(enum ni_gpct_variant variant) +static inline unsigned int GI_PRESCALE_X8(enum ni_gpct_variant variant) { switch (variant) { case ni_gpct_variant_e_series: @@ -154,19 +137,6 @@ static inline unsigned GI_PRESCALE_X8(enum ni_gpct_variant variant) } } -static inline unsigned GI_HW_ARM_SEL_MASK(enum ni_gpct_variant variant) -{ - switch (variant) { - case ni_gpct_variant_e_series: - default: - return 0; - case ni_gpct_variant_m_series: - return GI_M_HW_ARM_SEL_MASK; - case ni_gpct_variant_660x: - return GI_660X_HW_ARM_SEL_MASK; - } -} - static bool ni_tio_has_gate2_registers(const struct ni_gpct_device *counter_dev) { switch (counter_dev->variant) { @@ -179,17 +149,45 @@ static bool ni_tio_has_gate2_registers(const struct ni_gpct_device *counter_dev) } } +/** + * ni_tio_write() - Write a TIO register using the driver provided callback. + * @counter: struct ni_gpct counter. + * @value: the value to write + * @reg: the register to write. + */ +void ni_tio_write(struct ni_gpct *counter, unsigned int value, + enum ni_gpct_register reg) +{ + if (reg < NITIO_NUM_REGS) + counter->counter_dev->write(counter, value, reg); +} +EXPORT_SYMBOL_GPL(ni_tio_write); + +/** + * ni_tio_read() - Read a TIO register using the driver provided callback. + * @counter: struct ni_gpct counter. + * @reg: the register to read. + */ +unsigned int ni_tio_read(struct ni_gpct *counter, enum ni_gpct_register reg) +{ + if (reg < NITIO_NUM_REGS) + return counter->counter_dev->read(counter, reg); + return 0; +} +EXPORT_SYMBOL_GPL(ni_tio_read); + static void ni_tio_reset_count_and_disarm(struct ni_gpct *counter) { - unsigned cidx = counter->counter_index; + unsigned int cidx = counter->counter_index; - write_register(counter, GI_RESET(cidx), NITIO_RESET_REG(cidx)); + ni_tio_write(counter, GI_RESET(cidx), NITIO_RESET_REG(cidx)); } -static uint64_t ni_tio_clock_period_ps(const struct ni_gpct *counter, - unsigned generic_clock_source) +static int ni_tio_clock_period_ps(const struct ni_gpct *counter, + unsigned int generic_clock_source, + u64 *period_ps) { - uint64_t clock_period_ps; + u64 clock_period_ps; switch (generic_clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK) { case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS: @@ -222,19 +220,80 @@ static uint64_t ni_tio_clock_period_ps(const struct ni_gpct *counter, clock_period_ps *= 8; break; default: - BUG(); - break; + return -EINVAL; } - return clock_period_ps; + *period_ps = clock_period_ps; + return 0; } -static unsigned ni_tio_clock_src_modifiers(const struct ni_gpct *counter) +static void ni_tio_set_bits_transient(struct ni_gpct *counter, + enum ni_gpct_register reg, + unsigned int mask, unsigned int value, + unsigned int transient) { struct ni_gpct_device *counter_dev = counter->counter_dev; - unsigned cidx = counter->counter_index; - const unsigned counting_mode_bits = + unsigned long flags; + + if (reg < NITIO_NUM_REGS) { + spin_lock_irqsave(&counter_dev->regs_lock, flags); + counter_dev->regs[reg] &= ~mask; + counter_dev->regs[reg] |= (value & mask); + ni_tio_write(counter, counter_dev->regs[reg] | transient, reg); + mmiowb(); + spin_unlock_irqrestore(&counter_dev->regs_lock, flags); + } +} + +/** + * ni_tio_set_bits() - Safely write a counter register. + * @counter: struct ni_gpct counter. + * @reg: the register to write. + * @mask: the bits to change. + * @value: the new bits value. + * + * Used to write to, and update the software copy, a register whose bits may + * be twiddled in interrupt context, or whose software copy may be read in + * interrupt context. + */ +void ni_tio_set_bits(struct ni_gpct *counter, enum ni_gpct_register reg, + unsigned int mask, unsigned int value) +{ + ni_tio_set_bits_transient(counter, reg, mask, value, 0x0); +} +EXPORT_SYMBOL_GPL(ni_tio_set_bits); + +/** + * ni_tio_get_soft_copy() - Safely read the software copy of a counter register. + * @counter: struct ni_gpct counter. + * @reg: the register to read. + * + * Used to get the software copy of a register whose bits might be modified + * in interrupt context, or whose software copy might need to be read in + * interrupt context. + */ +unsigned int ni_tio_get_soft_copy(const struct ni_gpct *counter, + enum ni_gpct_register reg) +{ + struct ni_gpct_device *counter_dev = counter->counter_dev; + unsigned int value = 0; + unsigned long flags; + + if (reg < NITIO_NUM_REGS) { + spin_lock_irqsave(&counter_dev->regs_lock, flags); + value = counter_dev->regs[reg]; + spin_unlock_irqrestore(&counter_dev->regs_lock, flags); + } + return value; +} +EXPORT_SYMBOL_GPL(ni_tio_get_soft_copy); + +static unsigned int ni_tio_clock_src_modifiers(const struct ni_gpct *counter) +{ + struct ni_gpct_device *counter_dev = counter->counter_dev; + unsigned int cidx = counter->counter_index; + unsigned int counting_mode_bits = ni_tio_get_soft_copy(counter, NITIO_CNT_MODE_REG(cidx)); - unsigned bits = 0; + unsigned int bits = 0; if (ni_tio_get_soft_copy(counter, NITIO_INPUT_SEL_REG(cidx)) & GI_SRC_POL_INVERT) @@ -246,14 +305,15 @@ static unsigned ni_tio_clock_src_modifiers(const struct ni_gpct *counter) return bits; } -static unsigned ni_m_series_clock_src_select(const struct ni_gpct *counter) +static int ni_m_series_clock_src_select(const struct ni_gpct *counter, + unsigned int *clk_src) { struct ni_gpct_device *counter_dev = counter->counter_dev; - unsigned cidx = counter->counter_index; - const unsigned second_gate_reg = NITIO_GATE2_REG(cidx); - unsigned clock_source = 0; - unsigned src; - unsigned i; + unsigned int cidx = counter->counter_index; + unsigned int second_gate_reg = NITIO_GATE2_REG(cidx); + unsigned int clock_source = 0; + unsigned int src; + unsigned int i; src = GI_BITS_TO_SRC(ni_tio_get_soft_copy(counter, NITIO_INPUT_SEL_REG(cidx))); @@ -304,19 +364,20 @@ static unsigned ni_m_series_clock_src_select(const struct ni_gpct *counter) } if (i <= NI_M_MAX_PFI_CHAN) break; - BUG(); - break; + return -EINVAL; } clock_source |= ni_tio_clock_src_modifiers(counter); - return clock_source; + *clk_src = clock_source; + return 0; } -static unsigned ni_660x_clock_src_select(const struct ni_gpct *counter) +static int ni_660x_clock_src_select(const struct ni_gpct *counter, + unsigned int *clk_src) { - unsigned clock_source = 0; - unsigned cidx = counter->counter_index; - unsigned src; - unsigned i; + unsigned int clock_source = 0; + unsigned int cidx = counter->counter_index; + unsigned int src; + unsigned int i; src = GI_BITS_TO_SRC(ni_tio_get_soft_copy(counter, NITIO_INPUT_SEL_REG(cidx))); @@ -361,78 +422,88 @@ static unsigned ni_660x_clock_src_select(const struct ni_gpct *counter) } if (i <= NI_660X_MAX_SRC_PIN) break; - BUG(); - break; + return -EINVAL; } clock_source |= ni_tio_clock_src_modifiers(counter); - return clock_source; + *clk_src = clock_source; + return 0; } -static unsigned ni_tio_generic_clock_src_select(const struct ni_gpct *counter) +static int ni_tio_generic_clock_src_select(const struct ni_gpct *counter, + unsigned int *clk_src) { switch (counter->counter_dev->variant) { case ni_gpct_variant_e_series: case ni_gpct_variant_m_series: default: - return ni_m_series_clock_src_select(counter); + return ni_m_series_clock_src_select(counter, clk_src); case ni_gpct_variant_660x: - return ni_660x_clock_src_select(counter); + return ni_660x_clock_src_select(counter, clk_src); } } -static void ni_tio_set_sync_mode(struct ni_gpct *counter, int force_alt_sync) +static void ni_tio_set_sync_mode(struct ni_gpct *counter) { struct ni_gpct_device *counter_dev = counter->counter_dev; - unsigned cidx = counter->counter_index; - const unsigned counting_mode_reg = NITIO_CNT_MODE_REG(cidx); - static const uint64_t min_normal_sync_period_ps = 25000; - unsigned mode; - uint64_t clock_period_ps; - - if (ni_tio_counting_mode_registers_present(counter_dev) == 0) + unsigned int cidx = counter->counter_index; + static const u64 min_normal_sync_period_ps = 25000; + unsigned int mask = 0; + unsigned int bits = 0; + unsigned int reg; + unsigned int mode; + unsigned int clk_src; + u64 ps; + bool force_alt_sync; + + /* only m series and 660x variants have counting mode registers */ + switch (counter_dev->variant) { + case ni_gpct_variant_e_series: + default: return; + case ni_gpct_variant_m_series: + mask = GI_M_ALT_SYNC; + break; + case ni_gpct_variant_660x: + mask = GI_660X_ALT_SYNC; + break; + } - mode = ni_tio_get_soft_copy(counter, counting_mode_reg); + reg = NITIO_CNT_MODE_REG(cidx); + mode = ni_tio_get_soft_copy(counter, reg); switch (mode & GI_CNT_MODE_MASK) { case GI_CNT_MODE_QUADX1: case GI_CNT_MODE_QUADX2: case GI_CNT_MODE_QUADX4: case GI_CNT_MODE_SYNC_SRC: - force_alt_sync = 1; + force_alt_sync = true; break; default: + force_alt_sync = false; break; } - clock_period_ps = ni_tio_clock_period_ps(counter, - ni_tio_generic_clock_src_select(counter)); + ni_tio_generic_clock_src_select(counter, &clk_src); + ni_tio_clock_period_ps(counter, clk_src, &ps); /* * It's not clear what we should do if clock_period is unknown, so we - * are not using the alt sync bit in that case, but allow the caller - * to decide by using the force_alt_sync parameter. + * are not using the alt sync bit in that case. */ - if (force_alt_sync || - (clock_period_ps && clock_period_ps < min_normal_sync_period_ps)) { - ni_tio_set_bits(counter, counting_mode_reg, - GI_ALT_SYNC(counter_dev->variant), - GI_ALT_SYNC(counter_dev->variant)); - } else { - ni_tio_set_bits(counter, counting_mode_reg, - GI_ALT_SYNC(counter_dev->variant), - 0x0); - } + if (force_alt_sync || (ps && ps < min_normal_sync_period_ps)) + bits = mask; + + ni_tio_set_bits(counter, reg, mask, bits); } -static int ni_tio_set_counter_mode(struct ni_gpct *counter, unsigned mode) +static int ni_tio_set_counter_mode(struct ni_gpct *counter, unsigned int mode) { struct ni_gpct_device *counter_dev = counter->counter_dev; - unsigned cidx = counter->counter_index; - unsigned mode_reg_mask; - unsigned mode_reg_values; - unsigned input_select_bits = 0; + unsigned int cidx = counter->counter_index; + unsigned int mode_reg_mask; + unsigned int mode_reg_values; + unsigned int input_select_bits = 0; /* these bits map directly on to the mode register */ - static const unsigned mode_reg_direct_mask = + static const unsigned int mode_reg_direct_mask = NI_GPCT_GATE_ON_BOTH_EDGES_BIT | NI_GPCT_EDGE_GATE_MODE_MASK | NI_GPCT_STOP_MODE_MASK | NI_GPCT_OUTPUT_MODE_MASK | NI_GPCT_HARDWARE_DISARM_MASK | NI_GPCT_LOADING_ON_TC_BIT | @@ -458,7 +529,7 @@ static int ni_tio_set_counter_mode(struct ni_gpct *counter, unsigned mode) mode_reg_mask, mode_reg_values); if (ni_tio_counting_mode_registers_present(counter_dev)) { - unsigned bits = 0; + unsigned int bits = 0; bits |= GI_CNT_MODE(mode >> NI_GPCT_COUNTING_MODE_SHIFT); bits |= GI_INDEX_PHASE((mode >> NI_GPCT_INDEX_PHASE_BITSHIFT)); @@ -467,7 +538,7 @@ static int ni_tio_set_counter_mode(struct ni_gpct *counter, unsigned mode) ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx), GI_CNT_MODE_MASK | GI_INDEX_PHASE_MASK | GI_INDEX_MODE, bits); - ni_tio_set_sync_mode(counter, 0); + ni_tio_set_sync_mode(counter); } ni_tio_set_bits(counter, NITIO_CMD_REG(cidx), GI_CNT_DIR_MASK, @@ -484,65 +555,68 @@ static int ni_tio_set_counter_mode(struct ni_gpct *counter, unsigned mode) return 0; } -int ni_tio_arm(struct ni_gpct *counter, int arm, unsigned start_trigger) +int ni_tio_arm(struct ni_gpct *counter, bool arm, unsigned int start_trigger) { struct ni_gpct_device *counter_dev = counter->counter_dev; - unsigned cidx = counter->counter_index; - unsigned command_transient_bits = 0; + unsigned int cidx = counter->counter_index; + unsigned int transient_bits = 0; if (arm) { + unsigned int mask = 0; + unsigned int bits = 0; + + /* only m series and 660x have counting mode registers */ + switch (counter_dev->variant) { + case ni_gpct_variant_e_series: + default: + break; + case ni_gpct_variant_m_series: + mask = GI_M_HW_ARM_SEL_MASK; + break; + case ni_gpct_variant_660x: + mask = GI_660X_HW_ARM_SEL_MASK; + break; + } + switch (start_trigger) { case NI_GPCT_ARM_IMMEDIATE: - command_transient_bits |= GI_ARM; + transient_bits |= GI_ARM; break; case NI_GPCT_ARM_PAIRED_IMMEDIATE: - command_transient_bits |= GI_ARM | GI_ARM_COPY; + transient_bits |= GI_ARM | GI_ARM_COPY; break; default: + /* + * for m series and 660x, pass-through the least + * significant bits so we can figure out what select + * later + */ + if (mask && (start_trigger & NI_GPCT_ARM_UNKNOWN)) { + bits |= GI_HW_ARM_ENA | + (GI_HW_ARM_SEL(start_trigger) & mask); + } else { + return -EINVAL; + } break; } - if (ni_tio_counting_mode_registers_present(counter_dev)) { - unsigned bits = 0; - unsigned sel_mask; - sel_mask = GI_HW_ARM_SEL_MASK(counter_dev->variant); - - switch (start_trigger) { - case NI_GPCT_ARM_IMMEDIATE: - case NI_GPCT_ARM_PAIRED_IMMEDIATE: - break; - default: - if (start_trigger & NI_GPCT_ARM_UNKNOWN) { - /* - * pass-through the least significant - * bits so we can figure out what - * select later - */ - bits |= GI_HW_ARM_ENA | - (GI_HW_ARM_SEL(start_trigger) & - sel_mask); - } else { - return -EINVAL; - } - break; - } + if (mask) ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx), - GI_HW_ARM_ENA | sel_mask, bits); - } + GI_HW_ARM_ENA | mask, bits); } else { - command_transient_bits |= GI_DISARM; + transient_bits |= GI_DISARM; } ni_tio_set_bits_transient(counter, NITIO_CMD_REG(cidx), - 0, 0, command_transient_bits); + 0, 0, transient_bits); return 0; } EXPORT_SYMBOL_GPL(ni_tio_arm); -static unsigned ni_660x_clk_src(unsigned int clock_source) +static int ni_660x_clk_src(unsigned int clock_source, unsigned int *bits) { - unsigned clk_src = clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK; - unsigned ni_660x_clock; - unsigned i; + unsigned int clk_src = clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK; + unsigned int ni_660x_clock; + unsigned int i; switch (clk_src) { case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS: @@ -583,18 +657,17 @@ static unsigned ni_660x_clk_src(unsigned int clock_source) } if (i <= NI_660X_MAX_SRC_PIN) break; - ni_660x_clock = 0; - BUG(); - break; + return -EINVAL; } - return GI_SRC_SEL(ni_660x_clock); + *bits = GI_SRC_SEL(ni_660x_clock); + return 0; } -static unsigned ni_m_clk_src(unsigned int clock_source) +static int ni_m_clk_src(unsigned int clock_source, unsigned int *bits) { - unsigned clk_src = clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK; - unsigned ni_m_series_clock; - unsigned i; + unsigned int clk_src = clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK; + unsigned int ni_m_series_clock; + unsigned int i; switch (clk_src) { case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS: @@ -641,21 +714,18 @@ static unsigned ni_m_clk_src(unsigned int clock_source) } if (i <= NI_M_MAX_PFI_CHAN) break; - pr_err("invalid clock source 0x%lx\n", - (unsigned long)clock_source); - BUG(); - ni_m_series_clock = 0; - break; + return -EINVAL; } - return GI_SRC_SEL(ni_m_series_clock); + *bits = GI_SRC_SEL(ni_m_series_clock); + return 0; }; static void ni_tio_set_source_subselect(struct ni_gpct *counter, unsigned int clock_source) { struct ni_gpct_device *counter_dev = counter->counter_dev; - unsigned cidx = counter->counter_index; - const unsigned second_gate_reg = NITIO_GATE2_REG(cidx); + unsigned int cidx = counter->counter_index; + unsigned int second_gate_reg = NITIO_GATE2_REG(cidx); if (counter_dev->variant != ni_gpct_variant_m_series) return; @@ -674,8 +744,8 @@ static void ni_tio_set_source_subselect(struct ni_gpct *counter, default: return; } - write_register(counter, counter_dev->regs[second_gate_reg], - second_gate_reg); + ni_tio_write(counter, counter_dev->regs[second_gate_reg], + second_gate_reg); } static int ni_tio_set_clock_src(struct ni_gpct *counter, @@ -683,20 +753,28 @@ static int ni_tio_set_clock_src(struct ni_gpct *counter, unsigned int period_ns) { struct ni_gpct_device *counter_dev = counter->counter_dev; - unsigned cidx = counter->counter_index; - unsigned bits = 0; + unsigned int cidx = counter->counter_index; + unsigned int bits = 0; + int ret; - /* FIXME: validate clock source */ switch (counter_dev->variant) { case ni_gpct_variant_660x: - bits |= ni_660x_clk_src(clock_source); + ret = ni_660x_clk_src(clock_source, &bits); break; case ni_gpct_variant_e_series: case ni_gpct_variant_m_series: default: - bits |= ni_m_clk_src(clock_source); + ret = ni_m_clk_src(clock_source, &bits); break; } + if (ret) { + struct comedi_device *dev = counter_dev->dev; + + dev_err(dev->class_dev, "invalid clock source 0x%x\n", + clock_source); + return ret; + } + if (clock_source & NI_GPCT_INVERT_CLOCK_SRC_BIT) bits |= GI_SRC_POL_INVERT; ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx), @@ -722,28 +800,34 @@ static int ni_tio_set_clock_src(struct ni_gpct *counter, GI_PRESCALE_X8(counter_dev->variant), bits); } counter->clock_period_ps = period_ns * 1000; - ni_tio_set_sync_mode(counter, 0); + ni_tio_set_sync_mode(counter); return 0; } -static void ni_tio_get_clock_src(struct ni_gpct *counter, - unsigned int *clock_source, - unsigned int *period_ns) +static int ni_tio_get_clock_src(struct ni_gpct *counter, + unsigned int *clock_source, + unsigned int *period_ns) { - uint64_t temp64; - - *clock_source = ni_tio_generic_clock_src_select(counter); - temp64 = ni_tio_clock_period_ps(counter, *clock_source); + u64 temp64; + int ret; + + ret = ni_tio_generic_clock_src_select(counter, clock_source); + if (ret) + return ret; + ret = ni_tio_clock_period_ps(counter, *clock_source, &temp64); + if (ret) + return ret; do_div(temp64, 1000); /* ps to ns */ *period_ns = temp64; + return 0; } static int ni_660x_set_gate(struct ni_gpct *counter, unsigned int gate_source) { unsigned int chan = CR_CHAN(gate_source); - unsigned cidx = counter->counter_index; - unsigned gate_sel; - unsigned i; + unsigned int cidx = counter->counter_index; + unsigned int gate_sel; + unsigned int i; switch (chan) { case NI_GPCT_NEXT_SOURCE_GATE_SELECT: @@ -782,9 +866,9 @@ static int ni_660x_set_gate(struct ni_gpct *counter, unsigned int gate_source) static int ni_m_set_gate(struct ni_gpct *counter, unsigned int gate_source) { unsigned int chan = CR_CHAN(gate_source); - unsigned cidx = counter->counter_index; - unsigned gate_sel; - unsigned i; + unsigned int cidx = counter->counter_index; + unsigned int gate_sel; + unsigned int i; switch (chan) { case NI_GPCT_TIMESTAMP_MUX_GATE_SELECT: @@ -824,11 +908,11 @@ static int ni_m_set_gate(struct ni_gpct *counter, unsigned int gate_source) static int ni_660x_set_gate2(struct ni_gpct *counter, unsigned int gate_source) { struct ni_gpct_device *counter_dev = counter->counter_dev; - unsigned cidx = counter->counter_index; + unsigned int cidx = counter->counter_index; unsigned int chan = CR_CHAN(gate_source); - unsigned gate2_reg = NITIO_GATE2_REG(cidx); - unsigned gate2_sel; - unsigned i; + unsigned int gate2_reg = NITIO_GATE2_REG(cidx); + unsigned int gate2_sel; + unsigned int i; switch (chan) { case NI_GPCT_SOURCE_PIN_i_GATE_SELECT: @@ -863,17 +947,17 @@ static int ni_660x_set_gate2(struct ni_gpct *counter, unsigned int gate_source) counter_dev->regs[gate2_reg] |= GI_GATE2_MODE; counter_dev->regs[gate2_reg] &= ~GI_GATE2_SEL_MASK; counter_dev->regs[gate2_reg] |= GI_GATE2_SEL(gate2_sel); - write_register(counter, counter_dev->regs[gate2_reg], gate2_reg); + ni_tio_write(counter, counter_dev->regs[gate2_reg], gate2_reg); return 0; } static int ni_m_set_gate2(struct ni_gpct *counter, unsigned int gate_source) { struct ni_gpct_device *counter_dev = counter->counter_dev; - unsigned cidx = counter->counter_index; + unsigned int cidx = counter->counter_index; unsigned int chan = CR_CHAN(gate_source); - unsigned gate2_reg = NITIO_GATE2_REG(cidx); - unsigned gate2_sel; + unsigned int gate2_reg = NITIO_GATE2_REG(cidx); + unsigned int gate2_sel; /* * FIXME: We don't know what the m-series second gate codes are, @@ -887,20 +971,20 @@ static int ni_m_set_gate2(struct ni_gpct *counter, unsigned int gate_source) counter_dev->regs[gate2_reg] |= GI_GATE2_MODE; counter_dev->regs[gate2_reg] &= ~GI_GATE2_SEL_MASK; counter_dev->regs[gate2_reg] |= GI_GATE2_SEL(gate2_sel); - write_register(counter, counter_dev->regs[gate2_reg], gate2_reg); + ni_tio_write(counter, counter_dev->regs[gate2_reg], gate2_reg); return 0; } -int ni_tio_set_gate_src(struct ni_gpct *counter, unsigned gate_index, - unsigned int gate_source) +int ni_tio_set_gate_src(struct ni_gpct *counter, + unsigned int gate, unsigned int src) { struct ni_gpct_device *counter_dev = counter->counter_dev; - unsigned cidx = counter->counter_index; - unsigned int chan = CR_CHAN(gate_source); - unsigned gate2_reg = NITIO_GATE2_REG(cidx); - unsigned mode = 0; + unsigned int cidx = counter->counter_index; + unsigned int chan = CR_CHAN(src); + unsigned int gate2_reg = NITIO_GATE2_REG(cidx); + unsigned int mode = 0; - switch (gate_index) { + switch (gate) { case 0: if (chan == NI_GPCT_DISABLED_GATE_SELECT) { ni_tio_set_bits(counter, NITIO_MODE_REG(cidx), @@ -908,9 +992,9 @@ int ni_tio_set_gate_src(struct ni_gpct *counter, unsigned gate_index, GI_GATING_DISABLED); return 0; } - if (gate_source & CR_INVERT) + if (src & CR_INVERT) mode |= GI_GATE_POL_INVERT; - if (gate_source & CR_EDGE) + if (src & CR_EDGE) mode |= GI_RISING_EDGE_GATING; else mode |= GI_LEVEL_GATING; @@ -921,9 +1005,9 @@ int ni_tio_set_gate_src(struct ni_gpct *counter, unsigned gate_index, case ni_gpct_variant_e_series: case ni_gpct_variant_m_series: default: - return ni_m_set_gate(counter, gate_source); + return ni_m_set_gate(counter, src); case ni_gpct_variant_660x: - return ni_660x_set_gate(counter, gate_source); + return ni_660x_set_gate(counter, src); } break; case 1: @@ -932,22 +1016,21 @@ int ni_tio_set_gate_src(struct ni_gpct *counter, unsigned gate_index, if (chan == NI_GPCT_DISABLED_GATE_SELECT) { counter_dev->regs[gate2_reg] &= ~GI_GATE2_MODE; - write_register(counter, counter_dev->regs[gate2_reg], - gate2_reg); + ni_tio_write(counter, counter_dev->regs[gate2_reg], + gate2_reg); return 0; } - if (gate_source & CR_INVERT) + if (src & CR_INVERT) counter_dev->regs[gate2_reg] |= GI_GATE2_POL_INVERT; else counter_dev->regs[gate2_reg] &= ~GI_GATE2_POL_INVERT; switch (counter_dev->variant) { case ni_gpct_variant_m_series: - return ni_m_set_gate2(counter, gate_source); + return ni_m_set_gate2(counter, src); case ni_gpct_variant_660x: - return ni_660x_set_gate2(counter, gate_source); + return ni_660x_set_gate2(counter, src); default: - BUG(); - break; + return -EINVAL; } break; default: @@ -957,11 +1040,11 @@ int ni_tio_set_gate_src(struct ni_gpct *counter, unsigned gate_index, } EXPORT_SYMBOL_GPL(ni_tio_set_gate_src); -static int ni_tio_set_other_src(struct ni_gpct *counter, unsigned index, +static int ni_tio_set_other_src(struct ni_gpct *counter, unsigned int index, unsigned int source) { struct ni_gpct_device *counter_dev = counter->counter_dev; - unsigned cidx = counter->counter_index; + unsigned int cidx = counter->counter_index; unsigned int abz_reg, shift, mask; if (counter_dev->variant != ni_gpct_variant_m_series) @@ -987,175 +1070,221 @@ static int ni_tio_set_other_src(struct ni_gpct *counter, unsigned index, counter_dev->regs[abz_reg] &= ~mask; counter_dev->regs[abz_reg] |= (source << shift) & mask; - write_register(counter, counter_dev->regs[abz_reg], abz_reg); + ni_tio_write(counter, counter_dev->regs[abz_reg], abz_reg); return 0; } -static unsigned ni_660x_gate_to_generic_gate(unsigned gate) +static int ni_660x_gate_to_generic_gate(unsigned int gate, unsigned int *src) { - unsigned i; + unsigned int source; + unsigned int i; switch (gate) { case NI_660X_SRC_PIN_I_GATE_SEL: - return NI_GPCT_SOURCE_PIN_i_GATE_SELECT; + source = NI_GPCT_SOURCE_PIN_i_GATE_SELECT; + break; case NI_660X_GATE_PIN_I_GATE_SEL: - return NI_GPCT_GATE_PIN_i_GATE_SELECT; + source = NI_GPCT_GATE_PIN_i_GATE_SELECT; + break; case NI_660X_NEXT_SRC_GATE_SEL: - return NI_GPCT_NEXT_SOURCE_GATE_SELECT; + source = NI_GPCT_NEXT_SOURCE_GATE_SELECT; + break; case NI_660X_NEXT_OUT_GATE_SEL: - return NI_GPCT_NEXT_OUT_GATE_SELECT; + source = NI_GPCT_NEXT_OUT_GATE_SELECT; + break; case NI_660X_LOGIC_LOW_GATE_SEL: - return NI_GPCT_LOGIC_LOW_GATE_SELECT; + source = NI_GPCT_LOGIC_LOW_GATE_SELECT; + break; default: for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) { - if (gate == NI_660X_RTSI_GATE_SEL(i)) - return NI_GPCT_RTSI_GATE_SELECT(i); + if (gate == NI_660X_RTSI_GATE_SEL(i)) { + source = NI_GPCT_RTSI_GATE_SELECT(i); + break; + } } + if (i <= NI_660X_MAX_RTSI_CHAN) + break; for (i = 0; i <= NI_660X_MAX_GATE_PIN; ++i) { - if (gate == NI_660X_PIN_GATE_SEL(i)) - return NI_GPCT_GATE_PIN_GATE_SELECT(i); + if (gate == NI_660X_PIN_GATE_SEL(i)) { + source = NI_GPCT_GATE_PIN_GATE_SELECT(i); + break; + } } - BUG(); - break; + if (i <= NI_660X_MAX_GATE_PIN) + break; + return -EINVAL; } + *src = source; return 0; }; -static unsigned ni_m_gate_to_generic_gate(unsigned gate) +static int ni_m_gate_to_generic_gate(unsigned int gate, unsigned int *src) { - unsigned i; + unsigned int source; + unsigned int i; switch (gate) { case NI_M_TIMESTAMP_MUX_GATE_SEL: - return NI_GPCT_TIMESTAMP_MUX_GATE_SELECT; + source = NI_GPCT_TIMESTAMP_MUX_GATE_SELECT; + break; case NI_M_AI_START2_GATE_SEL: - return NI_GPCT_AI_START2_GATE_SELECT; + source = NI_GPCT_AI_START2_GATE_SELECT; + break; case NI_M_PXI_STAR_TRIGGER_GATE_SEL: - return NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT; + source = NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT; + break; case NI_M_NEXT_OUT_GATE_SEL: - return NI_GPCT_NEXT_OUT_GATE_SELECT; + source = NI_GPCT_NEXT_OUT_GATE_SELECT; + break; case NI_M_AI_START1_GATE_SEL: - return NI_GPCT_AI_START1_GATE_SELECT; + source = NI_GPCT_AI_START1_GATE_SELECT; + break; case NI_M_NEXT_SRC_GATE_SEL: - return NI_GPCT_NEXT_SOURCE_GATE_SELECT; + source = NI_GPCT_NEXT_SOURCE_GATE_SELECT; + break; case NI_M_ANALOG_TRIG_OUT_GATE_SEL: - return NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT; + source = NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT; + break; case NI_M_LOGIC_LOW_GATE_SEL: - return NI_GPCT_LOGIC_LOW_GATE_SELECT; + source = NI_GPCT_LOGIC_LOW_GATE_SELECT; + break; default: for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) { - if (gate == NI_M_RTSI_GATE_SEL(i)) - return NI_GPCT_RTSI_GATE_SELECT(i); + if (gate == NI_M_RTSI_GATE_SEL(i)) { + source = NI_GPCT_RTSI_GATE_SELECT(i); + break; + } } + if (i <= NI_M_MAX_RTSI_CHAN) + break; for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) { - if (gate == NI_M_PFI_GATE_SEL(i)) - return NI_GPCT_PFI_GATE_SELECT(i); + if (gate == NI_M_PFI_GATE_SEL(i)) { + source = NI_GPCT_PFI_GATE_SELECT(i); + break; + } } - BUG(); - break; + if (i <= NI_M_MAX_PFI_CHAN) + break; + return -EINVAL; } + *src = source; return 0; }; -static unsigned ni_660x_gate2_to_generic_gate(unsigned gate) +static int ni_660x_gate2_to_generic_gate(unsigned int gate, unsigned int *src) { - unsigned i; + unsigned int source; + unsigned int i; switch (gate) { case NI_660X_SRC_PIN_I_GATE2_SEL: - return NI_GPCT_SOURCE_PIN_i_GATE_SELECT; + source = NI_GPCT_SOURCE_PIN_i_GATE_SELECT; + break; case NI_660X_UD_PIN_I_GATE2_SEL: - return NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT; + source = NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT; + break; case NI_660X_NEXT_SRC_GATE2_SEL: - return NI_GPCT_NEXT_SOURCE_GATE_SELECT; + source = NI_GPCT_NEXT_SOURCE_GATE_SELECT; + break; case NI_660X_NEXT_OUT_GATE2_SEL: - return NI_GPCT_NEXT_OUT_GATE_SELECT; + source = NI_GPCT_NEXT_OUT_GATE_SELECT; + break; case NI_660X_SELECTED_GATE2_SEL: - return NI_GPCT_SELECTED_GATE_GATE_SELECT; + source = NI_GPCT_SELECTED_GATE_GATE_SELECT; + break; case NI_660X_LOGIC_LOW_GATE2_SEL: - return NI_GPCT_LOGIC_LOW_GATE_SELECT; + source = NI_GPCT_LOGIC_LOW_GATE_SELECT; + break; default: for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) { - if (gate == NI_660X_RTSI_GATE2_SEL(i)) - return NI_GPCT_RTSI_GATE_SELECT(i); + if (gate == NI_660X_RTSI_GATE2_SEL(i)) { + source = NI_GPCT_RTSI_GATE_SELECT(i); + break; + } } + if (i <= NI_660X_MAX_RTSI_CHAN) + break; for (i = 0; i <= NI_660X_MAX_UP_DOWN_PIN; ++i) { - if (gate == NI_660X_UD_PIN_GATE2_SEL(i)) - return NI_GPCT_UP_DOWN_PIN_GATE_SELECT(i); + if (gate == NI_660X_UD_PIN_GATE2_SEL(i)) { + source = NI_GPCT_UP_DOWN_PIN_GATE_SELECT(i); + break; + } } - BUG(); - break; + if (i <= NI_660X_MAX_UP_DOWN_PIN) + break; + return -EINVAL; } + *src = source; return 0; }; -static unsigned ni_m_gate2_to_generic_gate(unsigned gate) +static int ni_m_gate2_to_generic_gate(unsigned int gate, unsigned int *src) { /* * FIXME: the second gate sources for the m series are undocumented, * so we just return the raw bits for now. */ - switch (gate) { - default: - return gate; - } + *src = gate; return 0; }; -static int ni_tio_get_gate_src(struct ni_gpct *counter, unsigned gate_index, +static int ni_tio_get_gate_src(struct ni_gpct *counter, unsigned int gate_index, unsigned int *gate_source) { struct ni_gpct_device *counter_dev = counter->counter_dev; - unsigned cidx = counter->counter_index; - unsigned mode = ni_tio_get_soft_copy(counter, NITIO_MODE_REG(cidx)); - unsigned gate2_reg = NITIO_GATE2_REG(cidx); - unsigned gate; + unsigned int cidx = counter->counter_index; + unsigned int mode; + unsigned int reg; + unsigned int gate; + int ret; + + mode = ni_tio_get_soft_copy(counter, NITIO_MODE_REG(cidx)); + if (((mode & GI_GATING_MODE_MASK) == GI_GATING_DISABLED) || + (gate_index == 1 && + !(counter_dev->regs[NITIO_GATE2_REG(cidx)] & GI_GATE2_MODE))) { + *gate_source = NI_GPCT_DISABLED_GATE_SELECT; + return 0; + } switch (gate_index) { case 0: - if ((mode & GI_GATING_MODE_MASK) == GI_GATING_DISABLED) { - *gate_source = NI_GPCT_DISABLED_GATE_SELECT; - return 0; - } - - gate = GI_BITS_TO_GATE(ni_tio_get_soft_copy(counter, - NITIO_INPUT_SEL_REG(cidx))); + reg = NITIO_INPUT_SEL_REG(cidx); + gate = GI_BITS_TO_GATE(ni_tio_get_soft_copy(counter, reg)); switch (counter_dev->variant) { case ni_gpct_variant_e_series: case ni_gpct_variant_m_series: default: - *gate_source = ni_m_gate_to_generic_gate(gate); + ret = ni_m_gate_to_generic_gate(gate, gate_source); break; case ni_gpct_variant_660x: - *gate_source = ni_660x_gate_to_generic_gate(gate); + ret = ni_660x_gate_to_generic_gate(gate, gate_source); break; } + if (ret) + return ret; if (mode & GI_GATE_POL_INVERT) *gate_source |= CR_INVERT; if ((mode & GI_GATING_MODE_MASK) != GI_LEVEL_GATING) *gate_source |= CR_EDGE; break; case 1: - if ((mode & GI_GATING_MODE_MASK) == GI_GATING_DISABLED || - !(counter_dev->regs[gate2_reg] & GI_GATE2_MODE)) { - *gate_source = NI_GPCT_DISABLED_GATE_SELECT; - return 0; - } - - gate = GI_BITS_TO_GATE2(counter_dev->regs[gate2_reg]); + reg = NITIO_GATE2_REG(cidx); + gate = GI_BITS_TO_GATE2(counter_dev->regs[reg]); switch (counter_dev->variant) { case ni_gpct_variant_e_series: case ni_gpct_variant_m_series: default: - *gate_source = ni_m_gate2_to_generic_gate(gate); + ret = ni_m_gate2_to_generic_gate(gate, gate_source); break; case ni_gpct_variant_660x: - *gate_source = ni_660x_gate2_to_generic_gate(gate); + ret = ni_660x_gate2_to_generic_gate(gate, gate_source); break; } - if (counter_dev->regs[gate2_reg] & GI_GATE2_POL_INVERT) + if (ret) + return ret; + if (counter_dev->regs[reg] & GI_GATE2_POL_INVERT) *gate_source |= CR_INVERT; /* second gate can't have edge/level mode set independently */ if ((mode & GI_GATING_MODE_MASK) != GI_LEVEL_GATING) @@ -1173,45 +1302,52 @@ int ni_tio_insn_config(struct comedi_device *dev, unsigned int *data) { struct ni_gpct *counter = s->private; - unsigned cidx = counter->counter_index; - unsigned status; + unsigned int cidx = counter->counter_index; + unsigned int status; + int ret = 0; switch (data[0]) { case INSN_CONFIG_SET_COUNTER_MODE: - return ni_tio_set_counter_mode(counter, data[1]); + ret = ni_tio_set_counter_mode(counter, data[1]); + break; case INSN_CONFIG_ARM: - return ni_tio_arm(counter, 1, data[1]); + ret = ni_tio_arm(counter, true, data[1]); + break; case INSN_CONFIG_DISARM: - ni_tio_arm(counter, 0, 0); - return 0; + ret = ni_tio_arm(counter, false, 0); + break; case INSN_CONFIG_GET_COUNTER_STATUS: data[1] = 0; - status = read_register(counter, NITIO_SHARED_STATUS_REG(cidx)); + status = ni_tio_read(counter, NITIO_SHARED_STATUS_REG(cidx)); if (status & GI_ARMED(cidx)) { data[1] |= COMEDI_COUNTER_ARMED; if (status & GI_COUNTING(cidx)) data[1] |= COMEDI_COUNTER_COUNTING; } data[2] = COMEDI_COUNTER_ARMED | COMEDI_COUNTER_COUNTING; - return 0; + break; case INSN_CONFIG_SET_CLOCK_SRC: - return ni_tio_set_clock_src(counter, data[1], data[2]); + ret = ni_tio_set_clock_src(counter, data[1], data[2]); + break; case INSN_CONFIG_GET_CLOCK_SRC: - ni_tio_get_clock_src(counter, &data[1], &data[2]); - return 0; + ret = ni_tio_get_clock_src(counter, &data[1], &data[2]); + break; case INSN_CONFIG_SET_GATE_SRC: - return ni_tio_set_gate_src(counter, data[1], data[2]); + ret = ni_tio_set_gate_src(counter, data[1], data[2]); + break; case INSN_CONFIG_GET_GATE_SRC: - return ni_tio_get_gate_src(counter, data[1], &data[2]); + ret = ni_tio_get_gate_src(counter, data[1], &data[2]); + break; case INSN_CONFIG_SET_OTHER_SRC: - return ni_tio_set_other_src(counter, data[1], data[2]); + ret = ni_tio_set_other_src(counter, data[1], data[2]); + break; case INSN_CONFIG_RESET: ni_tio_reset_count_and_disarm(counter); - return 0; - default: break; + default: + return -EINVAL; } - return -EINVAL; + return ret ? ret : insn->n; } EXPORT_SYMBOL_GPL(ni_tio_insn_config); @@ -1219,7 +1355,7 @@ static unsigned int ni_tio_read_sw_save_reg(struct comedi_device *dev, struct comedi_subdevice *s) { struct ni_gpct *counter = s->private; - unsigned cidx = counter->counter_index; + unsigned int cidx = counter->counter_index; unsigned int val; ni_tio_set_bits(counter, NITIO_CMD_REG(cidx), GI_SAVE_TRACE, 0); @@ -1235,9 +1371,9 @@ static unsigned int ni_tio_read_sw_save_reg(struct comedi_device *dev, * will be correct since the count value will definitely have latched * by then. */ - val = read_register(counter, NITIO_SW_SAVE_REG(cidx)); - if (val != read_register(counter, NITIO_SW_SAVE_REG(cidx))) - val = read_register(counter, NITIO_SW_SAVE_REG(cidx)); + val = ni_tio_read(counter, NITIO_SW_SAVE_REG(cidx)); + if (val != ni_tio_read(counter, NITIO_SW_SAVE_REG(cidx))) + val = ni_tio_read(counter, NITIO_SW_SAVE_REG(cidx)); return val; } @@ -1250,7 +1386,7 @@ int ni_tio_insn_read(struct comedi_device *dev, struct ni_gpct *counter = s->private; struct ni_gpct_device *counter_dev = counter->counter_dev; unsigned int channel = CR_CHAN(insn->chanspec); - unsigned cidx = counter->counter_index; + unsigned int cidx = counter->counter_index; int i; for (i = 0; i < insn->n; i++) { @@ -1270,11 +1406,10 @@ int ni_tio_insn_read(struct comedi_device *dev, } EXPORT_SYMBOL_GPL(ni_tio_insn_read); -static unsigned ni_tio_next_load_register(struct ni_gpct *counter) +static unsigned int ni_tio_next_load_register(struct ni_gpct *counter) { - unsigned cidx = counter->counter_index; - const unsigned bits = - read_register(counter, NITIO_SHARED_STATUS_REG(cidx)); + unsigned int cidx = counter->counter_index; + unsigned int bits = ni_tio_read(counter, NITIO_SHARED_STATUS_REG(cidx)); return (bits & GI_NEXT_LOAD_SRC(cidx)) ? NITIO_LOADB_REG(cidx) @@ -1288,9 +1423,9 @@ int ni_tio_insn_write(struct comedi_device *dev, { struct ni_gpct *counter = s->private; struct ni_gpct_device *counter_dev = counter->counter_dev; - const unsigned channel = CR_CHAN(insn->chanspec); - unsigned cidx = counter->counter_index; - unsigned load_reg; + unsigned int channel = CR_CHAN(insn->chanspec); + unsigned int cidx = counter->counter_index; + unsigned int load_reg; if (insn->n < 1) return 0; @@ -1306,19 +1441,19 @@ int ni_tio_insn_write(struct comedi_device *dev, * load register is already selected. */ load_reg = ni_tio_next_load_register(counter); - write_register(counter, data[0], load_reg); + ni_tio_write(counter, data[0], load_reg); ni_tio_set_bits_transient(counter, NITIO_CMD_REG(cidx), 0, 0, GI_LOAD); /* restore load reg */ - write_register(counter, counter_dev->regs[load_reg], load_reg); + ni_tio_write(counter, counter_dev->regs[load_reg], load_reg); break; case 1: counter_dev->regs[NITIO_LOADA_REG(cidx)] = data[0]; - write_register(counter, data[0], NITIO_LOADA_REG(cidx)); + ni_tio_write(counter, data[0], NITIO_LOADA_REG(cidx)); break; case 2: counter_dev->regs[NITIO_LOADB_REG(cidx)] = data[0]; - write_register(counter, data[0], NITIO_LOADB_REG(cidx)); + ni_tio_write(counter, data[0], NITIO_LOADB_REG(cidx)); break; default: return -EINVAL; @@ -1330,13 +1465,13 @@ EXPORT_SYMBOL_GPL(ni_tio_insn_write); void ni_tio_init_counter(struct ni_gpct *counter) { struct ni_gpct_device *counter_dev = counter->counter_dev; - unsigned cidx = counter->counter_index; + unsigned int cidx = counter->counter_index; ni_tio_reset_count_and_disarm(counter); /* initialize counter registers */ counter_dev->regs[NITIO_AUTO_INC_REG(cidx)] = 0x0; - write_register(counter, 0x0, NITIO_AUTO_INC_REG(cidx)); + ni_tio_write(counter, 0x0, NITIO_AUTO_INC_REG(cidx)); ni_tio_set_bits(counter, NITIO_CMD_REG(cidx), ~0, GI_SYNC_GATE); @@ -1344,10 +1479,10 @@ void ni_tio_init_counter(struct ni_gpct *counter) ni_tio_set_bits(counter, NITIO_MODE_REG(cidx), ~0, 0); counter_dev->regs[NITIO_LOADA_REG(cidx)] = 0x0; - write_register(counter, 0x0, NITIO_LOADA_REG(cidx)); + ni_tio_write(counter, 0x0, NITIO_LOADA_REG(cidx)); counter_dev->regs[NITIO_LOADB_REG(cidx)] = 0x0; - write_register(counter, 0x0, NITIO_LOADB_REG(cidx)); + ni_tio_write(counter, 0x0, NITIO_LOADB_REG(cidx)); ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx), ~0, 0); @@ -1356,7 +1491,7 @@ void ni_tio_init_counter(struct ni_gpct *counter) if (ni_tio_has_gate2_registers(counter_dev)) { counter_dev->regs[NITIO_GATE2_REG(cidx)] = 0x0; - write_register(counter, 0x0, NITIO_GATE2_REG(cidx)); + ni_tio_write(counter, 0x0, NITIO_GATE2_REG(cidx)); } ni_tio_set_bits(counter, NITIO_DMA_CFG_REG(cidx), ~0, 0x0); @@ -1367,17 +1502,17 @@ EXPORT_SYMBOL_GPL(ni_tio_init_counter); struct ni_gpct_device * ni_gpct_device_construct(struct comedi_device *dev, - void (*write_register)(struct ni_gpct *counter, - unsigned bits, - enum ni_gpct_register reg), - unsigned (*read_register)(struct ni_gpct *counter, - enum ni_gpct_register reg), + void (*write)(struct ni_gpct *counter, + unsigned int value, + enum ni_gpct_register reg), + unsigned int (*read)(struct ni_gpct *counter, + enum ni_gpct_register reg), enum ni_gpct_variant variant, - unsigned num_counters) + unsigned int num_counters) { struct ni_gpct_device *counter_dev; struct ni_gpct *counter; - unsigned i; + unsigned int i; if (num_counters == 0) return NULL; @@ -1387,8 +1522,8 @@ ni_gpct_device_construct(struct comedi_device *dev, return NULL; counter_dev->dev = dev; - counter_dev->write_register = write_register; - counter_dev->read_register = read_register; + counter_dev->write = write; + counter_dev->read = read; counter_dev->variant = variant; spin_lock_init(&counter_dev->regs_lock); @@ -1413,7 +1548,7 @@ EXPORT_SYMBOL_GPL(ni_gpct_device_construct); void ni_gpct_device_destroy(struct ni_gpct_device *counter_dev) { - if (!counter_dev->counters) + if (!counter_dev) return; kfree(counter_dev->counters); kfree(counter_dev); diff --git a/drivers/staging/comedi/drivers/ni_tio.h b/drivers/staging/comedi/drivers/ni_tio.h index 25aedd0e5867..4978358f9b13 100644 --- a/drivers/staging/comedi/drivers/ni_tio.h +++ b/drivers/staging/comedi/drivers/ni_tio.h @@ -1,29 +1,24 @@ /* - drivers/ni_tio.h - Header file for NI general purpose counter support code (ni_tio.c) - - COMEDI - Linux Control and Measurement Device Interface - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*/ + * Header file for NI general purpose counter support code (ni_tio.c) + * + * COMEDI - Linux Control and Measurement Device Interface + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ #ifndef _COMEDI_NI_TIO_H #define _COMEDI_NI_TIO_H #include "../comedidev.h" -/* forward declarations */ -struct mite_struct; -struct ni_gpct_device; - enum ni_gpct_register { NITIO_G0_AUTO_INC, NITIO_G1_AUTO_INC, @@ -106,35 +101,34 @@ enum ni_gpct_variant { struct ni_gpct { struct ni_gpct_device *counter_dev; - unsigned counter_index; - unsigned chip_index; - uint64_t clock_period_ps; /* clock period in picoseconds */ + unsigned int counter_index; + unsigned int chip_index; + u64 clock_period_ps; /* clock period in picoseconds */ struct mite_channel *mite_chan; - spinlock_t lock; + spinlock_t lock; /* protects 'mite_chan' */ }; struct ni_gpct_device { struct comedi_device *dev; - void (*write_register)(struct ni_gpct *counter, unsigned bits, - enum ni_gpct_register reg); - unsigned (*read_register)(struct ni_gpct *counter, - enum ni_gpct_register reg); + void (*write)(struct ni_gpct *, unsigned int value, + enum ni_gpct_register); + unsigned int (*read)(struct ni_gpct *, enum ni_gpct_register); enum ni_gpct_variant variant; struct ni_gpct *counters; - unsigned num_counters; - unsigned regs[NITIO_NUM_REGS]; - spinlock_t regs_lock; + unsigned int num_counters; + unsigned int regs[NITIO_NUM_REGS]; + spinlock_t regs_lock; /* protects 'regs' */ }; struct ni_gpct_device * ni_gpct_device_construct(struct comedi_device *, - void (*write_register)(struct ni_gpct *, - unsigned bits, - enum ni_gpct_register), - unsigned (*read_register)(struct ni_gpct *, - enum ni_gpct_register), + void (*write)(struct ni_gpct *, + unsigned int value, + enum ni_gpct_register), + unsigned int (*read)(struct ni_gpct *, + enum ni_gpct_register), enum ni_gpct_variant, - unsigned num_counters); + unsigned int num_counters); void ni_gpct_device_destroy(struct ni_gpct_device *); void ni_tio_init_counter(struct ni_gpct *); int ni_tio_insn_read(struct comedi_device *, struct comedi_subdevice *, diff --git a/drivers/staging/comedi/drivers/ni_tio_internal.h b/drivers/staging/comedi/drivers/ni_tio_internal.h index 2bceae493e23..b15b10833c42 100644 --- a/drivers/staging/comedi/drivers/ni_tio_internal.h +++ b/drivers/staging/comedi/drivers/ni_tio_internal.h @@ -1,20 +1,19 @@ /* - drivers/ni_tio_internal.h - Header file for NI general purpose counter support code (ni_tio.c and - ni_tiocmd.c) - - COMEDI - Linux Control and Measurement Device Interface - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*/ + * Header file for NI general purpose counter support code (ni_tio.c and + * ni_tiocmd.c) + * + * COMEDI - Linux Control and Measurement Device Interface + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ #ifndef _COMEDI_NI_TIO_INTERNAL_H #define _COMEDI_NI_TIO_INTERNAL_H @@ -24,68 +23,73 @@ #define NITIO_AUTO_INC_REG(x) (NITIO_G0_AUTO_INC + (x)) #define GI_AUTO_INC_MASK 0xff #define NITIO_CMD_REG(x) (NITIO_G0_CMD + (x)) -#define GI_ARM (1 << 0) -#define GI_SAVE_TRACE (1 << 1) -#define GI_LOAD (1 << 2) -#define GI_DISARM (1 << 4) +#define GI_ARM BIT(0) +#define GI_SAVE_TRACE BIT(1) +#define GI_LOAD BIT(2) +#define GI_DISARM BIT(4) #define GI_CNT_DIR(x) (((x) & 0x3) << 5) -#define GI_CNT_DIR_MASK (3 << 5) -#define GI_WRITE_SWITCH (1 << 7) -#define GI_SYNC_GATE (1 << 8) -#define GI_LITTLE_BIG_ENDIAN (1 << 9) -#define GI_BANK_SWITCH_START (1 << 10) -#define GI_BANK_SWITCH_MODE (1 << 11) -#define GI_BANK_SWITCH_ENABLE (1 << 12) -#define GI_ARM_COPY (1 << 13) -#define GI_SAVE_TRACE_COPY (1 << 14) -#define GI_DISARM_COPY (1 << 15) +#define GI_CNT_DIR_MASK GI_CNT_DIR(3) +#define GI_WRITE_SWITCH BIT(7) +#define GI_SYNC_GATE BIT(8) +#define GI_LITTLE_BIG_ENDIAN BIT(9) +#define GI_BANK_SWITCH_START BIT(10) +#define GI_BANK_SWITCH_MODE BIT(11) +#define GI_BANK_SWITCH_ENABLE BIT(12) +#define GI_ARM_COPY BIT(13) +#define GI_SAVE_TRACE_COPY BIT(14) +#define GI_DISARM_COPY BIT(15) #define NITIO_HW_SAVE_REG(x) (NITIO_G0_HW_SAVE + (x)) #define NITIO_SW_SAVE_REG(x) (NITIO_G0_SW_SAVE + (x)) #define NITIO_MODE_REG(x) (NITIO_G0_MODE + (x)) -#define GI_GATING_DISABLED (0 << 0) -#define GI_LEVEL_GATING (1 << 0) -#define GI_RISING_EDGE_GATING (2 << 0) -#define GI_FALLING_EDGE_GATING (3 << 0) -#define GI_GATING_MODE_MASK (3 << 0) -#define GI_GATE_ON_BOTH_EDGES (1 << 2) -#define GI_EDGE_GATE_STARTS_STOPS (0 << 3) -#define GI_EDGE_GATE_STOPS_STARTS (1 << 3) -#define GI_EDGE_GATE_STARTS (2 << 3) -#define GI_EDGE_GATE_NO_STARTS_OR_STOPS (3 << 3) -#define GI_EDGE_GATE_MODE_MASK (3 << 3) -#define GI_STOP_ON_GATE (0 << 5) -#define GI_STOP_ON_GATE_OR_TC (1 << 5) -#define GI_STOP_ON_GATE_OR_SECOND_TC (2 << 5) -#define GI_STOP_MODE_MASK (3 << 5) -#define GI_LOAD_SRC_SEL (1 << 7) -#define GI_OUTPUT_TC_PULSE (1 << 8) -#define GI_OUTPUT_TC_TOGGLE (2 << 8) -#define GI_OUTPUT_TC_OR_GATE_TOGGLE (3 << 8) -#define GI_OUTPUT_MODE_MASK (3 << 8) -#define GI_NO_HARDWARE_DISARM (0 << 10) -#define GI_DISARM_AT_TC (1 << 10) -#define GI_DISARM_AT_GATE (2 << 10) -#define GI_DISARM_AT_TC_OR_GATE (3 << 10) -#define GI_COUNTING_ONCE_MASK (3 << 10) -#define GI_LOADING_ON_TC (1 << 12) -#define GI_GATE_POL_INVERT (1 << 13) -#define GI_LOADING_ON_GATE (1 << 14) -#define GI_RELOAD_SRC_SWITCHING (1 << 15) +#define GI_GATING_MODE(x) (((x) & 0x3) << 0) +#define GI_GATING_DISABLED GI_GATING_MODE(0) +#define GI_LEVEL_GATING GI_GATING_MODE(1) +#define GI_RISING_EDGE_GATING GI_GATING_MODE(2) +#define GI_FALLING_EDGE_GATING GI_GATING_MODE(3) +#define GI_GATING_MODE_MASK GI_GATING_MODE(3) +#define GI_GATE_ON_BOTH_EDGES BIT(2) +#define GI_EDGE_GATE_MODE(x) (((x) & 0x3) << 3) +#define GI_EDGE_GATE_STARTS_STOPS GI_EDGE_GATE_MODE(0) +#define GI_EDGE_GATE_STOPS_STARTS GI_EDGE_GATE_MODE(1) +#define GI_EDGE_GATE_STARTS GI_EDGE_GATE_MODE(2) +#define GI_EDGE_GATE_NO_STARTS_OR_STOPS GI_EDGE_GATE_MODE(3) +#define GI_EDGE_GATE_MODE_MASK GI_EDGE_GATE_MODE(3) +#define GI_STOP_MODE(x) (((x) & 0x3) << 5) +#define GI_STOP_ON_GATE GI_STOP_MODE(0) +#define GI_STOP_ON_GATE_OR_TC GI_STOP_MODE(1) +#define GI_STOP_ON_GATE_OR_SECOND_TC GI_STOP_MODE(2) +#define GI_STOP_MODE_MASK GI_STOP_MODE(3) +#define GI_LOAD_SRC_SEL BIT(7) +#define GI_OUTPUT_MODE(x) (((x) & 0x3) << 8) +#define GI_OUTPUT_TC_PULSE GI_OUTPUT_MODE(1) +#define GI_OUTPUT_TC_TOGGLE GI_OUTPUT_MODE(2) +#define GI_OUTPUT_TC_OR_GATE_TOGGLE GI_OUTPUT_MODE(3) +#define GI_OUTPUT_MODE_MASK GI_OUTPUT_MODE(3) +#define GI_COUNTING_ONCE(x) (((x) & 0x3) << 10) +#define GI_NO_HARDWARE_DISARM GI_COUNTING_ONCE(0) +#define GI_DISARM_AT_TC GI_COUNTING_ONCE(1) +#define GI_DISARM_AT_GATE GI_COUNTING_ONCE(2) +#define GI_DISARM_AT_TC_OR_GATE GI_COUNTING_ONCE(3) +#define GI_COUNTING_ONCE_MASK GI_COUNTING_ONCE(3) +#define GI_LOADING_ON_TC BIT(12) +#define GI_GATE_POL_INVERT BIT(13) +#define GI_LOADING_ON_GATE BIT(14) +#define GI_RELOAD_SRC_SWITCHING BIT(15) #define NITIO_LOADA_REG(x) (NITIO_G0_LOADA + (x)) #define NITIO_LOADB_REG(x) (NITIO_G0_LOADB + (x)) #define NITIO_INPUT_SEL_REG(x) (NITIO_G0_INPUT_SEL + (x)) -#define GI_READ_ACKS_IRQ (1 << 0) -#define GI_WRITE_ACKS_IRQ (1 << 1) +#define GI_READ_ACKS_IRQ BIT(0) +#define GI_WRITE_ACKS_IRQ BIT(1) #define GI_BITS_TO_SRC(x) (((x) >> 2) & 0x1f) #define GI_SRC_SEL(x) (((x) & 0x1f) << 2) -#define GI_SRC_SEL_MASK (0x1f << 2) +#define GI_SRC_SEL_MASK GI_SRC_SEL(0x1f) #define GI_BITS_TO_GATE(x) (((x) >> 7) & 0x1f) #define GI_GATE_SEL(x) (((x) & 0x1f) << 7) -#define GI_GATE_SEL_MASK (0x1f << 7) -#define GI_GATE_SEL_LOAD_SRC (1 << 12) -#define GI_OR_GATE (1 << 13) -#define GI_OUTPUT_POL_INVERT (1 << 14) -#define GI_SRC_POL_INVERT (1 << 15) +#define GI_GATE_SEL_MASK GI_GATE_SEL(0x1f) +#define GI_GATE_SEL_LOAD_SRC BIT(12) +#define GI_OR_GATE BIT(13) +#define GI_OUTPUT_POL_INVERT BIT(14) +#define GI_SRC_POL_INVERT BIT(15) #define NITIO_CNT_MODE_REG(x) (NITIO_G0_CNT_MODE + (x)) #define GI_CNT_MODE(x) (((x) & 0x7) << 0) #define GI_CNT_MODE_NORMAL GI_CNT_MODE(0) @@ -94,152 +98,84 @@ #define GI_CNT_MODE_QUADX4 GI_CNT_MODE(3) #define GI_CNT_MODE_TWO_PULSE GI_CNT_MODE(4) #define GI_CNT_MODE_SYNC_SRC GI_CNT_MODE(6) -#define GI_CNT_MODE_MASK (7 << 0) -#define GI_INDEX_MODE (1 << 4) +#define GI_CNT_MODE_MASK GI_CNT_MODE(7) +#define GI_INDEX_MODE BIT(4) #define GI_INDEX_PHASE(x) (((x) & 0x3) << 5) -#define GI_INDEX_PHASE_MASK (3 << 5) -#define GI_HW_ARM_ENA (1 << 7) +#define GI_INDEX_PHASE_MASK GI_INDEX_PHASE(3) +#define GI_HW_ARM_ENA BIT(7) #define GI_HW_ARM_SEL(x) ((x) << 8) -#define GI_660X_HW_ARM_SEL_MASK (0x7 << 8) -#define GI_M_HW_ARM_SEL_MASK (0x1f << 8) -#define GI_660X_PRESCALE_X8 (1 << 12) -#define GI_M_PRESCALE_X8 (1 << 13) -#define GI_660X_ALT_SYNC (1 << 13) -#define GI_M_ALT_SYNC (1 << 14) -#define GI_660X_PRESCALE_X2 (1 << 14) -#define GI_M_PRESCALE_X2 (1 << 15) +#define GI_660X_HW_ARM_SEL_MASK GI_HW_ARM_SEL(0x7) +#define GI_M_HW_ARM_SEL_MASK GI_HW_ARM_SEL(0x1f) +#define GI_660X_PRESCALE_X8 BIT(12) +#define GI_M_PRESCALE_X8 BIT(13) +#define GI_660X_ALT_SYNC BIT(13) +#define GI_M_ALT_SYNC BIT(14) +#define GI_660X_PRESCALE_X2 BIT(14) +#define GI_M_PRESCALE_X2 BIT(15) #define NITIO_GATE2_REG(x) (NITIO_G0_GATE2 + (x)) -#define GI_GATE2_MODE (1 << 0) +#define GI_GATE2_MODE BIT(0) #define GI_BITS_TO_GATE2(x) (((x) >> 7) & 0x1f) #define GI_GATE2_SEL(x) (((x) & 0x1f) << 7) -#define GI_GATE2_SEL_MASK (0x1f << 7) -#define GI_GATE2_POL_INVERT (1 << 13) -#define GI_GATE2_SUBSEL (1 << 14) -#define GI_SRC_SUBSEL (1 << 15) +#define GI_GATE2_SEL_MASK GI_GATE2_SEL(0x1f) +#define GI_GATE2_POL_INVERT BIT(13) +#define GI_GATE2_SUBSEL BIT(14) +#define GI_SRC_SUBSEL BIT(15) #define NITIO_SHARED_STATUS_REG(x) (NITIO_G01_STATUS + ((x) / 2)) -#define GI_SAVE(x) (((x) % 2) ? (1 << 1) : (1 << 0)) -#define GI_COUNTING(x) (((x) % 2) ? (1 << 3) : (1 << 2)) -#define GI_NEXT_LOAD_SRC(x) (((x) % 2) ? (1 << 5) : (1 << 4)) -#define GI_STALE_DATA(x) (((x) % 2) ? (1 << 7) : (1 << 6)) -#define GI_ARMED(x) (((x) % 2) ? (1 << 9) : (1 << 8)) -#define GI_NO_LOAD_BETWEEN_GATES(x) (((x) % 2) ? (1 << 11) : (1 << 10)) -#define GI_TC_ERROR(x) (((x) % 2) ? (1 << 13) : (1 << 12)) -#define GI_GATE_ERROR(x) (((x) % 2) ? (1 << 15) : (1 << 14)) +#define GI_SAVE(x) (((x) % 2) ? BIT(1) : BIT(0)) +#define GI_COUNTING(x) (((x) % 2) ? BIT(3) : BIT(2)) +#define GI_NEXT_LOAD_SRC(x) (((x) % 2) ? BIT(5) : BIT(4)) +#define GI_STALE_DATA(x) (((x) % 2) ? BIT(7) : BIT(6)) +#define GI_ARMED(x) (((x) % 2) ? BIT(9) : BIT(8)) +#define GI_NO_LOAD_BETWEEN_GATES(x) (((x) % 2) ? BIT(11) : BIT(10)) +#define GI_TC_ERROR(x) (((x) % 2) ? BIT(13) : BIT(12)) +#define GI_GATE_ERROR(x) (((x) % 2) ? BIT(15) : BIT(14)) #define NITIO_RESET_REG(x) (NITIO_G01_RESET + ((x) / 2)) -#define GI_RESET(x) (1 << (2 + ((x) % 2))) +#define GI_RESET(x) BIT(2 + ((x) % 2)) #define NITIO_STATUS1_REG(x) (NITIO_G01_STATUS1 + ((x) / 2)) #define NITIO_STATUS2_REG(x) (NITIO_G01_STATUS2 + ((x) / 2)) -#define GI_OUTPUT(x) (((x) % 2) ? (1 << 1) : (1 << 0)) -#define GI_HW_SAVE(x) (((x) % 2) ? (1 << 13) : (1 << 12)) -#define GI_PERMANENT_STALE(x) (((x) % 2) ? (1 << 15) : (1 << 14)) +#define GI_OUTPUT(x) (((x) % 2) ? BIT(1) : BIT(0)) +#define GI_HW_SAVE(x) (((x) % 2) ? BIT(13) : BIT(12)) +#define GI_PERMANENT_STALE(x) (((x) % 2) ? BIT(15) : BIT(14)) #define NITIO_DMA_CFG_REG(x) (NITIO_G0_DMA_CFG + (x)) -#define GI_DMA_ENABLE (1 << 0) -#define GI_DMA_WRITE (1 << 1) -#define GI_DMA_INT_ENA (1 << 2) -#define GI_DMA_RESET (1 << 3) -#define GI_DMA_BANKSW_ERROR (1 << 4) +#define GI_DMA_ENABLE BIT(0) +#define GI_DMA_WRITE BIT(1) +#define GI_DMA_INT_ENA BIT(2) +#define GI_DMA_RESET BIT(3) +#define GI_DMA_BANKSW_ERROR BIT(4) #define NITIO_DMA_STATUS_REG(x) (NITIO_G0_DMA_STATUS + (x)) -#define GI_DMA_READBANK (1 << 13) -#define GI_DRQ_ERROR (1 << 14) -#define GI_DRQ_STATUS (1 << 15) +#define GI_DMA_READBANK BIT(13) +#define GI_DRQ_ERROR BIT(14) +#define GI_DRQ_STATUS BIT(15) #define NITIO_ABZ_REG(x) (NITIO_G0_ABZ + (x)) #define NITIO_INT_ACK_REG(x) (NITIO_G0_INT_ACK + (x)) -#define GI_GATE_ERROR_CONFIRM(x) (((x) % 2) ? (1 << 1) : (1 << 5)) -#define GI_TC_ERROR_CONFIRM(x) (((x) % 2) ? (1 << 2) : (1 << 6)) -#define GI_TC_INTERRUPT_ACK (1 << 14) -#define GI_GATE_INTERRUPT_ACK (1 << 15) +#define GI_GATE_ERROR_CONFIRM(x) (((x) % 2) ? BIT(1) : BIT(5)) +#define GI_TC_ERROR_CONFIRM(x) (((x) % 2) ? BIT(2) : BIT(6)) +#define GI_TC_INTERRUPT_ACK BIT(14) +#define GI_GATE_INTERRUPT_ACK BIT(15) #define NITIO_STATUS_REG(x) (NITIO_G0_STATUS + (x)) -#define GI_GATE_INTERRUPT (1 << 2) -#define GI_TC (1 << 3) -#define GI_INTERRUPT (1 << 15) +#define GI_GATE_INTERRUPT BIT(2) +#define GI_TC BIT(3) +#define GI_INTERRUPT BIT(15) #define NITIO_INT_ENA_REG(x) (NITIO_G0_INT_ENA + (x)) -#define GI_TC_INTERRUPT_ENABLE(x) (((x) % 2) ? (1 << 9) : (1 << 6)) -#define GI_GATE_INTERRUPT_ENABLE(x) (((x) % 2) ? (1 << 10) : (1 << 8)) - -static inline void write_register(struct ni_gpct *counter, unsigned bits, - enum ni_gpct_register reg) -{ - BUG_ON(reg >= NITIO_NUM_REGS); - counter->counter_dev->write_register(counter, bits, reg); -} - -static inline unsigned read_register(struct ni_gpct *counter, - enum ni_gpct_register reg) -{ - BUG_ON(reg >= NITIO_NUM_REGS); - return counter->counter_dev->read_register(counter, reg); -} +#define GI_TC_INTERRUPT_ENABLE(x) (((x) % 2) ? BIT(9) : BIT(6)) +#define GI_GATE_INTERRUPT_ENABLE(x) (((x) % 2) ? BIT(10) : BIT(8)) -static inline int ni_tio_counting_mode_registers_present(const struct - ni_gpct_device - *counter_dev) -{ - switch (counter_dev->variant) { - case ni_gpct_variant_e_series: - return 0; - case ni_gpct_variant_m_series: - case ni_gpct_variant_660x: - return 1; - default: - BUG(); - break; - } - return 0; -} - -static inline void ni_tio_set_bits_transient(struct ni_gpct *counter, - enum ni_gpct_register - register_index, unsigned bit_mask, - unsigned bit_values, - unsigned transient_bit_values) -{ - struct ni_gpct_device *counter_dev = counter->counter_dev; - unsigned long flags; - - BUG_ON(register_index >= NITIO_NUM_REGS); - spin_lock_irqsave(&counter_dev->regs_lock, flags); - counter_dev->regs[register_index] &= ~bit_mask; - counter_dev->regs[register_index] |= (bit_values & bit_mask); - write_register(counter, - counter_dev->regs[register_index] | transient_bit_values, - register_index); - mmiowb(); - spin_unlock_irqrestore(&counter_dev->regs_lock, flags); -} +void ni_tio_write(struct ni_gpct *, unsigned int value, enum ni_gpct_register); +unsigned int ni_tio_read(struct ni_gpct *, enum ni_gpct_register); -/* ni_tio_set_bits( ) is for safely writing to registers whose bits may be - * twiddled in interrupt context, or whose software copy may be read in - * interrupt context. - */ -static inline void ni_tio_set_bits(struct ni_gpct *counter, - enum ni_gpct_register register_index, - unsigned bit_mask, unsigned bit_values) +static inline bool +ni_tio_counting_mode_registers_present(const struct ni_gpct_device *counter_dev) { - ni_tio_set_bits_transient(counter, register_index, bit_mask, bit_values, - 0x0); + /* m series and 660x variants have counting mode registers */ + return counter_dev->variant != ni_gpct_variant_e_series; } -/* ni_tio_get_soft_copy( ) is for safely reading the software copy of a register -whose bits might be modified in interrupt context, or whose software copy -might need to be read in interrupt context. -*/ -static inline unsigned ni_tio_get_soft_copy(const struct ni_gpct *counter, - enum ni_gpct_register - register_index) -{ - struct ni_gpct_device *counter_dev = counter->counter_dev; - unsigned long flags; - unsigned value; - - BUG_ON(register_index >= NITIO_NUM_REGS); - spin_lock_irqsave(&counter_dev->regs_lock, flags); - value = counter_dev->regs[register_index]; - spin_unlock_irqrestore(&counter_dev->regs_lock, flags); - return value; -} +void ni_tio_set_bits(struct ni_gpct *, enum ni_gpct_register reg, + unsigned int mask, unsigned int value); +unsigned int ni_tio_get_soft_copy(const struct ni_gpct *, + enum ni_gpct_register reg); -int ni_tio_arm(struct ni_gpct *counter, int arm, unsigned start_trigger); -int ni_tio_set_gate_src(struct ni_gpct *counter, unsigned gate_index, - unsigned int gate_source); +int ni_tio_arm(struct ni_gpct *, bool arm, unsigned int start_trigger); +int ni_tio_set_gate_src(struct ni_gpct *, unsigned int gate, unsigned int src); #endif /* _COMEDI_NI_TIO_INTERNAL_H */ diff --git a/drivers/staging/comedi/drivers/ni_tiocmd.c b/drivers/staging/comedi/drivers/ni_tiocmd.c index 823e47910004..9007c57544bf 100644 --- a/drivers/staging/comedi/drivers/ni_tiocmd.c +++ b/drivers/staging/comedi/drivers/ni_tiocmd.c @@ -1,19 +1,18 @@ /* - comedi/drivers/ni_tiocmd.c - Command support for NI general purpose counters - - Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*/ + * Command support for NI general purpose counters + * + * Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ /* * Module: ni_tiocmd @@ -36,13 +35,10 @@ * DAQ 660x Register-Level Programmer Manual (NI 370505A-01) * DAQ 6601/6602 User Manual (NI 322137B-01) * 340934b.pdf DAQ-STC reference manual + * + * TODO: Support use of both banks X and Y */ -/* -TODO: - Support use of both banks X and Y -*/ - #include <linux/module.h> #include "ni_tio_internal.h" #include "mite.h" @@ -51,9 +47,9 @@ static void ni_tio_configure_dma(struct ni_gpct *counter, bool enable, bool read) { struct ni_gpct_device *counter_dev = counter->counter_dev; - unsigned cidx = counter->counter_index; - unsigned mask; - unsigned bits; + unsigned int cidx = counter->counter_index; + unsigned int mask; + unsigned int bits; mask = GI_READ_ACKS_IRQ | GI_WRITE_ACKS_IRQ; bits = 0; @@ -103,7 +99,7 @@ static int ni_tio_input_inttrig(struct comedi_device *dev, spin_unlock_irqrestore(&counter->lock, flags); if (ret < 0) return ret; - ret = ni_tio_arm(counter, 1, NI_GPCT_ARM_IMMEDIATE); + ret = ni_tio_arm(counter, true, NI_GPCT_ARM_IMMEDIATE); s->async->inttrig = NULL; return ret; @@ -113,7 +109,7 @@ static int ni_tio_input_cmd(struct comedi_subdevice *s) { struct ni_gpct *counter = s->private; struct ni_gpct_device *counter_dev = counter->counter_dev; - unsigned cidx = counter->counter_index; + unsigned int cidx = counter->counter_index; struct comedi_async *async = s->async; struct comedi_cmd *cmd = &async->cmd; int ret = 0; @@ -129,9 +125,6 @@ static int ni_tio_input_cmd(struct comedi_subdevice *s) case ni_gpct_variant_e_series: mite_prep_dma(counter->mite_chan, 16, 32); break; - default: - BUG(); - break; } ni_tio_set_bits(counter, NITIO_CMD_REG(cidx), GI_SAVE_TRACE, 0); ni_tio_configure_dma(counter, true, true); @@ -143,9 +136,9 @@ static int ni_tio_input_cmd(struct comedi_subdevice *s) mite_dma_arm(counter->mite_chan); if (cmd->start_src == TRIG_NOW) - ret = ni_tio_arm(counter, 1, NI_GPCT_ARM_IMMEDIATE); + ret = ni_tio_arm(counter, true, NI_GPCT_ARM_IMMEDIATE); else if (cmd->start_src == TRIG_EXT) - ret = ni_tio_arm(counter, 1, cmd->start_arg); + ret = ni_tio_arm(counter, true, cmd->start_arg); } return ret; } @@ -163,9 +156,9 @@ static int ni_tio_cmd_setup(struct comedi_subdevice *s) { struct comedi_cmd *cmd = &s->async->cmd; struct ni_gpct *counter = s->private; - unsigned cidx = counter->counter_index; + unsigned int cidx = counter->counter_index; int set_gate_source = 0; - unsigned gate_source; + unsigned int gate_source; int retval = 0; if (cmd->scan_begin_src == TRIG_EXT) { @@ -289,10 +282,10 @@ EXPORT_SYMBOL_GPL(ni_tio_cmdtest); int ni_tio_cancel(struct ni_gpct *counter) { - unsigned cidx = counter->counter_index; + unsigned int cidx = counter->counter_index; unsigned long flags; - ni_tio_arm(counter, 0, 0); + ni_tio_arm(counter, false, 0); spin_lock_irqsave(&counter->lock, flags); if (counter->mite_chan) mite_dma_disarm(counter->mite_chan); @@ -305,9 +298,6 @@ int ni_tio_cancel(struct ni_gpct *counter) } EXPORT_SYMBOL_GPL(ni_tio_cancel); - /* During buffered input counter operation for e-series, the gate - interrupt is acked automatically by the dma controller, due to the - Gi_Read/Write_Acknowledges_IRQ bits in the input select register. */ static int should_ack_gate(struct ni_gpct *counter) { unsigned long flags; @@ -315,12 +305,19 @@ static int should_ack_gate(struct ni_gpct *counter) switch (counter->counter_dev->variant) { case ni_gpct_variant_m_series: - /* not sure if 660x really supports gate - interrupts (the bits are not listed - in register-level manual) */ case ni_gpct_variant_660x: + /* + * not sure if 660x really supports gate interrupts + * (the bits are not listed in register-level manual) + */ return 1; case ni_gpct_variant_e_series: + /* + * During buffered input counter operation for e-series, + * the gate interrupt is acked automatically by the dma + * controller, due to the Gi_Read/Write_Acknowledges_IRQ + * bits in the input select register. + */ spin_lock_irqsave(&counter->lock, flags); { if (!counter->mite_chan || @@ -338,15 +335,14 @@ static int should_ack_gate(struct ni_gpct *counter) static void ni_tio_acknowledge_and_confirm(struct ni_gpct *counter, int *gate_error, int *tc_error, - int *perm_stale_data, - int *stale_data) + int *perm_stale_data) { - unsigned cidx = counter->counter_index; - const unsigned short gxx_status = read_register(counter, + unsigned int cidx = counter->counter_index; + const unsigned short gxx_status = ni_tio_read(counter, NITIO_SHARED_STATUS_REG(cidx)); - const unsigned short gi_status = read_register(counter, + const unsigned short gi_status = ni_tio_read(counter, NITIO_STATUS_REG(cidx)); - unsigned ack = 0; + unsigned int ack = 0; if (gate_error) *gate_error = 0; @@ -354,15 +350,15 @@ static void ni_tio_acknowledge_and_confirm(struct ni_gpct *counter, *tc_error = 0; if (perm_stale_data) *perm_stale_data = 0; - if (stale_data) - *stale_data = 0; if (gxx_status & GI_GATE_ERROR(cidx)) { ack |= GI_GATE_ERROR_CONFIRM(cidx); if (gate_error) { - /*660x don't support automatic acknowledgment - of gate interrupt via dma read/write - and report bogus gate errors */ + /* + * 660x don't support automatic acknowledgment + * of gate interrupt via dma read/write + * and report bogus gate errors + */ if (counter->counter_dev->variant != ni_gpct_variant_660x) *gate_error = 1; @@ -380,14 +376,10 @@ static void ni_tio_acknowledge_and_confirm(struct ni_gpct *counter, ack |= GI_GATE_INTERRUPT_ACK; } if (ack) - write_register(counter, ack, NITIO_INT_ACK_REG(cidx)); + ni_tio_write(counter, ack, NITIO_INT_ACK_REG(cidx)); if (ni_tio_get_soft_copy(counter, NITIO_MODE_REG(cidx)) & GI_LOADING_ON_GATE) { - if (gxx_status & GI_STALE_DATA(cidx)) { - if (stale_data) - *stale_data = 1; - } - if (read_register(counter, NITIO_STATUS2_REG(cidx)) & + if (ni_tio_read(counter, NITIO_STATUS2_REG(cidx)) & GI_PERMANENT_STALE(cidx)) { dev_info(counter->counter_dev->dev->class_dev, "%s: Gi_Permanent_Stale_Data detected.\n", @@ -400,22 +392,21 @@ static void ni_tio_acknowledge_and_confirm(struct ni_gpct *counter, void ni_tio_acknowledge(struct ni_gpct *counter) { - ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL); + ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL); } EXPORT_SYMBOL_GPL(ni_tio_acknowledge); void ni_tio_handle_interrupt(struct ni_gpct *counter, struct comedi_subdevice *s) { - unsigned cidx = counter->counter_index; - unsigned gpct_mite_status; + unsigned int cidx = counter->counter_index; unsigned long flags; int gate_error; int tc_error; int perm_stale_data; ni_tio_acknowledge_and_confirm(counter, &gate_error, &tc_error, - &perm_stale_data, NULL); + &perm_stale_data); if (gate_error) { dev_notice(counter->counter_dev->dev->class_dev, "%s: Gi_Gate_Error detected.\n", __func__); @@ -426,7 +417,7 @@ void ni_tio_handle_interrupt(struct ni_gpct *counter, switch (counter->counter_dev->variant) { case ni_gpct_variant_m_series: case ni_gpct_variant_660x: - if (read_register(counter, NITIO_DMA_STATUS_REG(cidx)) & + if (ni_tio_read(counter, NITIO_DMA_STATUS_REG(cidx)) & GI_DRQ_ERROR) { dev_notice(counter->counter_dev->dev->class_dev, "%s: Gi_DRQ_Error detected.\n", __func__); @@ -437,16 +428,8 @@ void ni_tio_handle_interrupt(struct ni_gpct *counter, break; } spin_lock_irqsave(&counter->lock, flags); - if (!counter->mite_chan) { - spin_unlock_irqrestore(&counter->lock, flags); - return; - } - gpct_mite_status = mite_get_status(counter->mite_chan); - if (gpct_mite_status & CHSR_LINKC) - writel(CHOR_CLRLC, - counter->mite_chan->mite->mite_io_addr + - MITE_CHOR(counter->mite_chan->channel)); - mite_sync_input_dma(counter->mite_chan, s); + if (counter->mite_chan) + mite_ack_linkc(counter->mite_chan, s, true); spin_unlock_irqrestore(&counter->lock, flags); } EXPORT_SYMBOL_GPL(ni_tio_handle_interrupt); diff --git a/drivers/staging/comedi/drivers/plx9052.h b/drivers/staging/comedi/drivers/plx9052.h index fbcf25069807..2892e6528967 100644 --- a/drivers/staging/comedi/drivers/plx9052.h +++ b/drivers/staging/comedi/drivers/plx9052.h @@ -1,22 +1,21 @@ /* - comedi/drivers/plx9052.h - Definitions for the PLX-9052 PCI interface chip - - Copyright (C) 2002 MEV Ltd. <http://www.mev.co.uk/> - - COMEDI - Linux Control and Measurement Device Interface - Copyright (C) 2000 David A. Schleef <ds@schleef.org> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*/ + * Definitions for the PLX-9052 PCI interface chip + * + * Copyright (C) 2002 MEV Ltd. <http://www.mev.co.uk/> + * + * COMEDI - Linux Control and Measurement Device Interface + * Copyright (C) 2000 David A. Schleef <ds@schleef.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ #ifndef _PLX9052_H_ #define _PLX9052_H_ @@ -25,55 +24,56 @@ * INTCSR - Interrupt Control/Status register */ #define PLX9052_INTCSR 0x4c -#define PLX9052_INTCSR_LI1ENAB (1 << 0) /* LI1 enabled */ -#define PLX9052_INTCSR_LI1POL (1 << 1) /* LI1 active high */ -#define PLX9052_INTCSR_LI1STAT (1 << 2) /* LI1 active */ -#define PLX9052_INTCSR_LI2ENAB (1 << 3) /* LI2 enabled */ -#define PLX9052_INTCSR_LI2POL (1 << 4) /* LI2 active high */ -#define PLX9052_INTCSR_LI2STAT (1 << 5) /* LI2 active */ -#define PLX9052_INTCSR_PCIENAB (1 << 6) /* PCIINT enabled */ -#define PLX9052_INTCSR_SOFTINT (1 << 7) /* generate soft int */ -#define PLX9052_INTCSR_LI1SEL (1 << 8) /* LI1 edge */ -#define PLX9052_INTCSR_LI2SEL (1 << 9) /* LI2 edge */ -#define PLX9052_INTCSR_LI1CLRINT (1 << 10) /* LI1 clear int */ -#define PLX9052_INTCSR_LI2CLRINT (1 << 11) /* LI2 clear int */ -#define PLX9052_INTCSR_ISAMODE (1 << 12) /* ISA interface mode */ +#define PLX9052_INTCSR_LI1ENAB BIT(0) /* LI1 enabled */ +#define PLX9052_INTCSR_LI1POL BIT(1) /* LI1 active high */ +#define PLX9052_INTCSR_LI1STAT BIT(2) /* LI1 active */ +#define PLX9052_INTCSR_LI2ENAB BIT(3) /* LI2 enabled */ +#define PLX9052_INTCSR_LI2POL BIT(4) /* LI2 active high */ +#define PLX9052_INTCSR_LI2STAT BIT(5) /* LI2 active */ +#define PLX9052_INTCSR_PCIENAB BIT(6) /* PCIINT enabled */ +#define PLX9052_INTCSR_SOFTINT BIT(7) /* generate soft int */ +#define PLX9052_INTCSR_LI1SEL BIT(8) /* LI1 edge */ +#define PLX9052_INTCSR_LI2SEL BIT(9) /* LI2 edge */ +#define PLX9052_INTCSR_LI1CLRINT BIT(10) /* LI1 clear int */ +#define PLX9052_INTCSR_LI2CLRINT BIT(11) /* LI2 clear int */ +#define PLX9052_INTCSR_ISAMODE BIT(12) /* ISA interface mode */ /* * CNTRL - User I/O, Direct Slave Response, Serial EEPROM, and * Initialization Control register */ #define PLX9052_CNTRL 0x50 -#define PLX9052_CNTRL_WAITO (1 << 0) /* UIO0 or WAITO# select */ -#define PLX9052_CNTRL_UIO0_DIR (1 << 1) /* UIO0 direction */ -#define PLX9052_CNTRL_UIO0_DATA (1 << 2) /* UIO0 data */ -#define PLX9052_CNTRL_LLOCKO (1 << 3) /* UIO1 or LLOCKo# select */ -#define PLX9052_CNTRL_UIO1_DIR (1 << 4) /* UIO1 direction */ -#define PLX9052_CNTRL_UIO1_DATA (1 << 5) /* UIO1 data */ -#define PLX9052_CNTRL_CS2 (1 << 6) /* UIO2 or CS2# select */ -#define PLX9052_CNTRL_UIO2_DIR (1 << 7) /* UIO2 direction */ -#define PLX9052_CNTRL_UIO2_DATA (1 << 8) /* UIO2 data */ -#define PLX9052_CNTRL_CS3 (1 << 9) /* UIO3 or CS3# select */ -#define PLX9052_CNTRL_UIO3_DIR (1 << 10) /* UIO3 direction */ -#define PLX9052_CNTRL_UIO3_DATA (1 << 11) /* UIO3 data */ -#define PLX9052_CNTRL_PCIBAR01 (0 << 12) /* bar 0 (mem) and 1 (I/O) */ -#define PLX9052_CNTRL_PCIBAR0 (1 << 12) /* bar 0 (mem) only */ -#define PLX9052_CNTRL_PCIBAR1 (2 << 12) /* bar 1 (I/O) only */ -#define PLX9052_CNTRL_PCI2_1_FEATURES (1 << 14) /* PCI r2.1 features enabled */ -#define PLX9052_CNTRL_PCI_R_W_FLUSH (1 << 15) /* read w/write flush mode */ -#define PLX9052_CNTRL_PCI_R_NO_FLUSH (1 << 16) /* read no flush mode */ -#define PLX9052_CNTRL_PCI_R_NO_WRITE (1 << 17) /* read no write mode */ -#define PLX9052_CNTRL_PCI_W_RELEASE (1 << 18) /* write release bus mode */ -#define PLX9052_CNTRL_RETRY_CLKS(x) (((x) & 0xf) << 19) /* slave retry clks */ -#define PLX9052_CNTRL_LOCK_ENAB (1 << 23) /* slave LOCK# enable */ +#define PLX9052_CNTRL_WAITO BIT(0) /* UIO0 or WAITO# select */ +#define PLX9052_CNTRL_UIO0_DIR BIT(1) /* UIO0 direction */ +#define PLX9052_CNTRL_UIO0_DATA BIT(2) /* UIO0 data */ +#define PLX9052_CNTRL_LLOCKO BIT(3) /* UIO1 or LLOCKo# select */ +#define PLX9052_CNTRL_UIO1_DIR BIT(4) /* UIO1 direction */ +#define PLX9052_CNTRL_UIO1_DATA BIT(5) /* UIO1 data */ +#define PLX9052_CNTRL_CS2 BIT(6) /* UIO2 or CS2# select */ +#define PLX9052_CNTRL_UIO2_DIR BIT(7) /* UIO2 direction */ +#define PLX9052_CNTRL_UIO2_DATA BIT(8) /* UIO2 data */ +#define PLX9052_CNTRL_CS3 BIT(9) /* UIO3 or CS3# select */ +#define PLX9052_CNTRL_UIO3_DIR BIT(10) /* UIO3 direction */ +#define PLX9052_CNTRL_UIO3_DATA BIT(11) /* UIO3 data */ +#define PLX9052_CNTRL_PCIBAR(x) (((x) & 0x3) << 12) +#define PLX9052_CNTRL_PCIBAR01 PLX9052_CNTRL_PCIBAR(0) /* mem and IO */ +#define PLX9052_CNTRL_PCIBAR0 PLX9052_CNTRL_PCIBAR(1) /* mem only */ +#define PLX9052_CNTRL_PCIBAR1 PLX9052_CNTRL_PCIBAR(2) /* IO only */ +#define PLX9052_CNTRL_PCI2_1_FEATURES BIT(14) /* PCI v2.1 features enabled */ +#define PLX9052_CNTRL_PCI_R_W_FLUSH BIT(15) /* read w/write flush mode */ +#define PLX9052_CNTRL_PCI_R_NO_FLUSH BIT(16) /* read no flush mode */ +#define PLX9052_CNTRL_PCI_R_NO_WRITE BIT(17) /* read no write mode */ +#define PLX9052_CNTRL_PCI_W_RELEASE BIT(18) /* write release bus mode */ +#define PLX9052_CNTRL_RETRY_CLKS(x) (((x) & 0xf) << 19) /* retry clks */ +#define PLX9052_CNTRL_LOCK_ENAB BIT(23) /* slave LOCK# enable */ #define PLX9052_CNTRL_EEPROM_MASK (0x1f << 24) /* EEPROM bits */ -#define PLX9052_CNTRL_EEPROM_CLK (1 << 24) /* EEPROM clock */ -#define PLX9052_CNTRL_EEPROM_CS (1 << 25) /* EEPROM chip select */ -#define PLX9052_CNTRL_EEPROM_DOUT (1 << 26) /* EEPROM write bit */ -#define PLX9052_CNTRL_EEPROM_DIN (1 << 27) /* EEPROM read bit */ -#define PLX9052_CNTRL_EEPROM_PRESENT (1 << 28) /* EEPROM present */ -#define PLX9052_CNTRL_RELOAD_CFG (1 << 29) /* reload configuration */ -#define PLX9052_CNTRL_PCI_RESET (1 << 30) /* PCI adapter reset */ -#define PLX9052_CNTRL_MASK_REV (1 << 31) /* mask revision */ +#define PLX9052_CNTRL_EEPROM_CLK BIT(24) /* EEPROM clock */ +#define PLX9052_CNTRL_EEPROM_CS BIT(25) /* EEPROM chip select */ +#define PLX9052_CNTRL_EEPROM_DOUT BIT(26) /* EEPROM write bit */ +#define PLX9052_CNTRL_EEPROM_DIN BIT(27) /* EEPROM read bit */ +#define PLX9052_CNTRL_EEPROM_PRESENT BIT(28) /* EEPROM present */ +#define PLX9052_CNTRL_RELOAD_CFG BIT(29) /* reload configuration */ +#define PLX9052_CNTRL_PCI_RESET BIT(30) /* PCI adapter reset */ +#define PLX9052_CNTRL_MASK_REV BIT(31) /* mask revision */ #endif /* _PLX9052_H_ */ diff --git a/drivers/staging/comedi/drivers/plx9080.h b/drivers/staging/comedi/drivers/plx9080.h index f5cd6d5004bd..8d1aee00b19f 100644 --- a/drivers/staging/comedi/drivers/plx9080.h +++ b/drivers/staging/comedi/drivers/plx9080.h @@ -88,7 +88,7 @@ enum marb_bits { /* direct slave LLOCKo# enable */ MARB_DS_LLOCK_ENABLE = 0x00400000, MARB_PCI_REQUEST_MODE = 0x00800000, - MARB_PCIv21_MODE = 0x01000000, /* pci specification v2.1 mode */ + MARB_PCIV21_MODE = 0x01000000, /* pci specification v2.1 mode */ MARB_PCI_READ_NO_WRITE_MODE = 0x02000000, MARB_PCI_READ_WITH_WRITE_FLUSH_MODE = 0x04000000, /* gate local bus latency timer with BREQ */ diff --git a/drivers/staging/comedi/drivers/z8536.h b/drivers/staging/comedi/drivers/z8536.h index 7be53109cc8d..47eadbf4dcc0 100644 --- a/drivers/staging/comedi/drivers/z8536.h +++ b/drivers/staging/comedi/drivers/z8536.h @@ -24,11 +24,12 @@ #define Z8536_CFG_CTRL_PCE_CT3E BIT(4) /* Port C & C/T 3 Enable */ #define Z8536_CFG_CTRL_PLC BIT(3) /* Port A/B Link Control */ #define Z8536_CFG_CTRL_PAE BIT(2) /* Port A Enable */ -#define Z8536_CFG_CTRL_LC_INDEP (0 << 0)/* C/Ts Independent */ -#define Z8536_CFG_CTRL_LC_GATE (1 << 0)/* C/T 1 Out Gates C/T 2 */ -#define Z8536_CFG_CTRL_LC_TRIG (2 << 0)/* C/T 1 Out Triggers C/T 2 */ -#define Z8536_CFG_CTRL_LC_CLK (3 << 0)/* C/T 1 Out Clocks C/T 2 */ -#define Z8536_CFG_CTRL_LC_MASK (3 << 0)/* C/T Link Control mask */ +#define Z8536_CFG_CTRL_LC(x) (((x) & 0x3) << 0) /* Link Control */ +#define Z8536_CFG_CTRL_LC_INDEP Z8536_CFG_CTRL_LC(0)/* Independent */ +#define Z8536_CFG_CTRL_LC_GATE Z8536_CFG_CTRL_LC(1)/* 1 Gates 2 */ +#define Z8536_CFG_CTRL_LC_TRIG Z8536_CFG_CTRL_LC(2)/* 1 Triggers 2 */ +#define Z8536_CFG_CTRL_LC_CLK Z8536_CFG_CTRL_LC(3)/* 1 Clocks 2 */ +#define Z8536_CFG_CTRL_LC_MASK Z8536_CFG_CTRL_LC(3) /* Interrupt Vector registers */ #define Z8536_PA_INT_VECT_REG 0x02 @@ -43,15 +44,16 @@ #define Z8536_CT2_CMDSTAT_REG 0x0b #define Z8536_CT3_CMDSTAT_REG 0x0c #define Z8536_CT_CMDSTAT_REG(x) (0x0a + (x)) -#define Z8536_CMD_NULL (0 << 5)/* Null Code */ -#define Z8536_CMD_CLR_IP_IUS (1 << 5)/* Clear IP & IUS */ -#define Z8536_CMD_SET_IUS (2 << 5)/* Set IUS */ -#define Z8536_CMD_CLR_IUS (3 << 5)/* Clear IUS */ -#define Z8536_CMD_SET_IP (4 << 5)/* Set IP */ -#define Z8536_CMD_CLR_IP (5 << 5)/* Clear IP */ -#define Z8536_CMD_SET_IE (6 << 5)/* Set IE */ -#define Z8536_CMD_CLR_IE (7 << 5)/* Clear IE */ -#define Z8536_CMD_MASK (7 << 5) +#define Z8536_CMD(x) (((x) & 0x7) << 5) +#define Z8536_CMD_NULL Z8536_CMD(0) /* Null Code */ +#define Z8536_CMD_CLR_IP_IUS Z8536_CMD(1) /* Clear IP & IUS */ +#define Z8536_CMD_SET_IUS Z8536_CMD(2) /* Set IUS */ +#define Z8536_CMD_CLR_IUS Z8536_CMD(3) /* Clear IUS */ +#define Z8536_CMD_SET_IP Z8536_CMD(4) /* Set IP */ +#define Z8536_CMD_CLR_IP Z8536_CMD(5) /* Clear IP */ +#define Z8536_CMD_SET_IE Z8536_CMD(6) /* Set IE */ +#define Z8536_CMD_CLR_IE Z8536_CMD(7) /* Clear IE */ +#define Z8536_CMD_MASK Z8536_CMD(7) #define Z8536_STAT_IUS BIT(7) /* Interrupt Under Service */ #define Z8536_STAT_IE BIT(6) /* Interrupt Enable */ @@ -105,46 +107,51 @@ #define Z8536_CT_MODE_ETE BIT(4) /* External Trigger Enable */ #define Z8536_CT_MODE_EGE BIT(3) /* External Gate Enable */ #define Z8536_CT_MODE_REB BIT(2) /* Retrigger Enable Bit */ -#define Z8536_CT_MODE_DCS_PULSE (0 << 0)/* Duty Cycle - Pulse */ -#define Z8536_CT_MODE_DCS_ONESHOT (1 << 0)/* Duty Cycle - One-Shot */ -#define Z8536_CT_MODE_DCS_SQRWAVE (2 << 0)/* Duty Cycle - Square Wave */ -#define Z8536_CT_MODE_DCS_DO_NOT_USE (3 << 0)/* Duty Cycle - Do Not Use */ -#define Z8536_CT_MODE_DCS_MASK (3 << 0)/* Duty Cycle mask */ +#define Z8536_CT_MODE_DCS(x) (((x) & 0x3) << 0) /* Duty Cycle */ +#define Z8536_CT_MODE_DCS_PULSE Z8536_CT_MODE_DCS(0) /* Pulse */ +#define Z8536_CT_MODE_DCS_ONESHOT Z8536_CT_MODE_DCS(1) /* One-Shot */ +#define Z8536_CT_MODE_DCS_SQRWAVE Z8536_CT_MODE_DCS(2) /* Square Wave */ +#define Z8536_CT_MODE_DCS_DO_NOT_USE Z8536_CT_MODE_DCS(3) /* Do Not Use */ +#define Z8536_CT_MODE_DCS_MASK Z8536_CT_MODE_DCS(3) /* Port A/B Mode Specification registers */ #define Z8536_PA_MODE_REG 0x20 #define Z8536_PB_MODE_REG 0x28 -#define Z8536_PAB_MODE_PTS_BIT (0 << 6)/* Bit Port */ -#define Z8536_PAB_MODE_PTS_INPUT (1 << 6)/* Input Port */ -#define Z8536_PAB_MODE_PTS_OUTPUT (2 << 6)/* Output Port */ -#define Z8536_PAB_MODE_PTS_BIDIR (3 << 6)/* Bidirectional Port */ -#define Z8536_PAB_MODE_PTS_MASK (3 << 6)/* Port Type Select mask */ +#define Z8536_PAB_MODE_PTS(x) (((x) & 0x3) << 6) /* Port type */ +#define Z8536_PAB_MODE_PTS_BIT Z8536_PAB_MODE_PTS(0 << 6)/* Bit */ +#define Z8536_PAB_MODE_PTS_INPUT Z8536_PAB_MODE_PTS(1 << 6)/* Input */ +#define Z8536_PAB_MODE_PTS_OUTPUT Z8536_PAB_MODE_PTS(2 << 6)/* Output */ +#define Z8536_PAB_MODE_PTS_BIDIR Z8536_PAB_MODE_PTS(3 << 6)/* Bidir */ +#define Z8536_PAB_MODE_PTS_MASK Z8536_PAB_MODE_PTS(3 << 6) #define Z8536_PAB_MODE_ITB BIT(5) /* Interrupt on Two Bytes */ #define Z8536_PAB_MODE_SB BIT(4) /* Single Buffered mode */ #define Z8536_PAB_MODE_IMO BIT(3) /* Interrupt on Match Only */ -#define Z8536_PAB_MODE_PMS_DISABLE (0 << 1)/* Disable Pattern Match */ -#define Z8536_PAB_MODE_PMS_AND (1 << 1)/* "AND" mode */ -#define Z8536_PAB_MODE_PMS_OR (2 << 1)/* "OR" mode */ -#define Z8536_PAB_MODE_PMS_OR_PEV (3 << 1)/* "OR-Priority" mode */ -#define Z8536_PAB_MODE_PMS_MASK (3 << 1)/* Pattern Mode mask */ +#define Z8536_PAB_MODE_PMS(x) (((x) & 0x3) << 1) /* Pattern Mode */ +#define Z8536_PAB_MODE_PMS_DISABLE Z8536_PAB_MODE_PMS(0)/* Disabled */ +#define Z8536_PAB_MODE_PMS_AND Z8536_PAB_MODE_PMS(1)/* "AND" */ +#define Z8536_PAB_MODE_PMS_OR Z8536_PAB_MODE_PMS(2)/* "OR" */ +#define Z8536_PAB_MODE_PMS_OR_PEV Z8536_PAB_MODE_PMS(3)/* "OR-Priority" */ +#define Z8536_PAB_MODE_PMS_MASK Z8536_PAB_MODE_PMS(3) #define Z8536_PAB_MODE_LPM BIT(0) /* Latch on Pattern Match */ #define Z8536_PAB_MODE_DTE BIT(0) /* Deskew Timer Enabled */ /* Port A/B Handshake Specification registers */ #define Z8536_PA_HANDSHAKE_REG 0x21 #define Z8536_PB_HANDSHAKE_REG 0x29 -#define Z8536_PAB_HANDSHAKE_HST_INTER (0 << 6)/* Interlocked Handshake */ -#define Z8536_PAB_HANDSHAKE_HST_STROBED (1 << 6)/* Strobed Handshake */ -#define Z8536_PAB_HANDSHAKE_HST_PULSED (2 << 6)/* Pulsed Handshake */ -#define Z8536_PAB_HANDSHAKE_HST_3WIRE (3 << 6)/* Three-Wire Handshake */ -#define Z8536_PAB_HANDSHAKE_HST_MASK (3 << 6)/* Handshake Type mask */ -#define Z8536_PAB_HANDSHAKE_RWS_DISABLE (0 << 3)/* Req/Wait Disabled */ -#define Z8536_PAB_HANDSHAKE_RWS_OUTWAIT (1 << 3)/* Output Wait */ -#define Z8536_PAB_HANDSHAKE_RWS_INWAIT (3 << 3)/* Input Wait */ -#define Z8536_PAB_HANDSHAKE_RWS_SPREQ (4 << 3)/* Special Request */ -#define Z8536_PAB_HANDSHAKE_RWS_OUTREQ (5 << 4)/* Output Request */ -#define Z8536_PAB_HANDSHAKE_RWS_INREQ (7 << 3)/* Input Request */ -#define Z8536_PAB_HANDSHAKE_RWS_MASK (7 << 3)/* Req/Wait mask */ +#define Z8536_PAB_HANDSHAKE_HST(x) (((x) & 0x3) << 6) /* Handshake Type */ +#define Z8536_PAB_HANDSHAKE_HST_INTER Z8536_PAB_HANDSHAKE_HST(0)/*Interlock*/ +#define Z8536_PAB_HANDSHAKE_HST_STROBED Z8536_PAB_HANDSHAKE_HST(1)/* Strobed */ +#define Z8536_PAB_HANDSHAKE_HST_PULSED Z8536_PAB_HANDSHAKE_HST(2)/* Pulsed */ +#define Z8536_PAB_HANDSHAKE_HST_3WIRE Z8536_PAB_HANDSHAKE_HST(3)/* 3-Wire */ +#define Z8536_PAB_HANDSHAKE_HST_MASK Z8536_PAB_HANDSHAKE_HST(3) +#define Z8536_PAB_HANDSHAKE_RWS(x) (((x) & 0x7) << 3) /* Req/Wait */ +#define Z8536_PAB_HANDSHAKE_RWS_DISABLE Z8536_PAB_HANDSHAKE_RWS(0)/* Disabled */ +#define Z8536_PAB_HANDSHAKE_RWS_OUTWAIT Z8536_PAB_HANDSHAKE_RWS(1)/* Out Wait */ +#define Z8536_PAB_HANDSHAKE_RWS_INWAIT Z8536_PAB_HANDSHAKE_RWS(3)/* In Wait */ +#define Z8536_PAB_HANDSHAKE_RWS_SPREQ Z8536_PAB_HANDSHAKE_RWS(4)/* Special */ +#define Z8536_PAB_HANDSHAKE_RWS_OUTREQ Z8536_PAB_HANDSHAKE_RWS(5)/* Out Req */ +#define Z8536_PAB_HANDSHAKE_RWS_INREQ Z8536_PAB_HANDSHAKE_RWS(7)/* In Req */ +#define Z8536_PAB_HANDSHAKE_RWS_MASK Z8536_PAB_HANDSHAKE_RWS(7) #define Z8536_PAB_HANDSHAKE_DESKEW(x) ((x) << 0)/* Deskew Time */ #define Z8536_PAB_HANDSHAKE_DESKEW_MASK (3 << 0)/* Deskew Time mask */ |
