diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2019-11-27 10:00:33 -0800 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2019-11-27 10:00:33 -0800 |
commit | dc5fa4656864d3391cdf13512ffa0733ef72fcdc (patch) | |
tree | dd4ce7719e83af33966952bee9e9bb6984d502fb /drivers/pinctrl/intel/pinctrl-intel.c | |
parent | 3d9e3501a064eff90274f1ce927fe71ca1ff4205 (diff) | |
parent | ae75b53e08b95cd189879b00f6a47cbdaab1f0eb (diff) | |
download | blackbird-op-linux-dc5fa4656864d3391cdf13512ffa0733ef72fcdc.tar.gz blackbird-op-linux-dc5fa4656864d3391cdf13512ffa0733ef72fcdc.zip |
Merge tag 'pinctrl-v5.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This is the bulk of pin control changes for v5.5.
It is pretty much business as usual, the most interesting thing I
think is the pin controller for a new Intel chip called Lightning
Mountain, which is according to news reports some kind of embedded
network processor and what is surprising about it is that Intel have
decided to use device tree to describe the system rather than ACPI
that they have traditionally favored.
Core changes:
- Avoid taking direct references to device tree-supplied device
names: these may changed at runtime under certain circumstances to
kstrdup them.
GPIO related:
- Work is ongoing to move to passing the irqchip along as a templated
struct gpio_irq_chip when adding a standard gpiolib-based irqchip
to a GPIO controller, a few patches in this cycle switches a few
pin control drivers over to using this method.
New hardware support:
- Intel Lightning Mountain SoC pin controller and GPIO support, a
first Intel platform to use device tree rather than ACPI to
configure the system. News reports says that this SoC is a network
processor.
- Qualcomm MSM8976 and MSM8956
- Qualcomm PMIC GPIO now also supports PM6150 and PM6150L
- Qualcomm SPMI MPP and SPMI GPIO for PM8950 and PMI8950
- Rockchip RK3308
- Renesas R8A77961
- Allwinner Meson-A1
Driver improvements:
- get_multiple and set_multiple support for the AT91-PIO4 driver.
- Convert Qualcomm SSBI GPIO to use the hierarchical IRQ helpers in
the GPIOlib irqchip"
* tag 'pinctrl-v5.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (93 commits)
pinctrl: ingenic: Add OTG VBUS pin for the JZ4770
pinctrl: ingenic: Handle PIN_CONFIG_OUTPUT config
pinctrl: Fix Kconfig indentation
pinctrl: lewisburg: Update pin list according to v1.1v6
MAINTAINERS: Replace my email by one @kernel.org
pinctrl: armada-37xx: Fix irq mask access in armada_37xx_irq_set_type()
dt-bindings: pinctrl: intel: Add for new SoC
pinctrl: Add pinmux & GPIO controller driver for a new SoC
pinctrl: rza1: remove unnecessary static inline function
pinctrl: meson: add pinctrl driver support for Meson-A1 SoC
pinctrl: meson: add a new callback for SoCs fixup
pinctrl: nomadik: db8500: Add mc0_a_2 pin group without direction control
dt-bindings: pinctrl: Convert generic pin mux and config properties to schema
pinctrl: cherryview: Missed type change to unsigned int
pinctrl: intel: Missed type change to unsigned int
pinctrl: use devm_platform_ioremap_resource() to simplify code
pinctrl: just return if no valid maps
dt-bindings: pinctrl: qcom-pmic-mpp: Add support for PM/PMI8950
pinctrl: qcom: spmi-mpp: Add PM/PMI8950 compatible strings
dt-bindings: pinctrl: qcom-pmic-gpio: Add support for PM/PMI8950
...
Diffstat (limited to 'drivers/pinctrl/intel/pinctrl-intel.c')
-rw-r--r-- | drivers/pinctrl/intel/pinctrl-intel.c | 119 |
1 files changed, 63 insertions, 56 deletions
diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 83981ad66a71..4860bc9a4e48 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -1131,7 +1131,7 @@ static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl, pending &= enabled; for_each_set_bit(gpp_offset, &pending, padgrp->size) { - unsigned irq; + unsigned int irq; irq = irq_find_mapping(gc->irq.domain, padgrp->gpio_base + gpp_offset); @@ -1181,7 +1181,7 @@ static int intel_gpio_add_pin_ranges(struct intel_pinctrl *pctrl, return ret; } -static unsigned intel_gpio_ngpio(const struct intel_pinctrl *pctrl) +static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl) { const struct intel_community *community; unsigned int ngpio = 0; @@ -1595,16 +1595,65 @@ intel_gpio_is_requested(struct gpio_chip *chip, int base, unsigned int size) return requested; } -static u32 -intel_gpio_update_pad_mode(void __iomem *hostown, u32 mask, u32 value) +static bool intel_gpio_update_reg(void __iomem *reg, u32 mask, u32 value) { u32 curr, updated; - curr = readl(hostown); + curr = readl(reg); + updated = (curr & ~mask) | (value & mask); - writel(updated, hostown); + if (curr == updated) + return false; + + writel(updated, reg); + return true; +} + +static void intel_restore_hostown(struct intel_pinctrl *pctrl, unsigned int c, + void __iomem *base, unsigned int gpp, u32 saved) +{ + const struct intel_community *community = &pctrl->communities[c]; + const struct intel_padgroup *padgrp = &community->gpps[gpp]; + struct device *dev = pctrl->dev; + u32 requested; + + if (padgrp->gpio_base < 0) + return; - return curr; + requested = intel_gpio_is_requested(&pctrl->chip, padgrp->gpio_base, padgrp->size); + if (!intel_gpio_update_reg(base + gpp * 4, requested, saved)) + return; + + dev_dbg(dev, "restored hostown %u/%u %#08x\n", c, gpp, readl(base + gpp * 4)); +} + +static void intel_restore_intmask(struct intel_pinctrl *pctrl, unsigned int c, + void __iomem *base, unsigned int gpp, u32 saved) +{ + struct device *dev = pctrl->dev; + + if (!intel_gpio_update_reg(base + gpp * 4, ~0U, saved)) + return; + + dev_dbg(dev, "restored mask %u/%u %#08x\n", c, gpp, readl(base + gpp * 4)); +} + +static void intel_restore_padcfg(struct intel_pinctrl *pctrl, unsigned int pin, + unsigned int reg, u32 saved) +{ + u32 mask = (reg == PADCFG0) ? PADCFG0_GPIORXSTATE : 0; + unsigned int n = reg / sizeof(u32); + struct device *dev = pctrl->dev; + void __iomem *padcfg; + + padcfg = intel_get_padcfg(pctrl, pin, reg); + if (!padcfg) + return; + + if (!intel_gpio_update_reg(padcfg, ~mask, saved)) + return; + + dev_dbg(dev, "restored pin %u padcfg%u %#08x\n", pin, n, readl(padcfg)); } int intel_pinctrl_resume_noirq(struct device *dev) @@ -1620,37 +1669,13 @@ int intel_pinctrl_resume_noirq(struct device *dev) pads = pctrl->context.pads; for (i = 0; i < pctrl->soc->npins; i++) { const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; - void __iomem *padcfg; - u32 val; if (!intel_pinctrl_should_save(pctrl, desc->number)) continue; - padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0); - val = readl(padcfg) & ~PADCFG0_GPIORXSTATE; - if (val != pads[i].padcfg0) { - writel(pads[i].padcfg0, padcfg); - dev_dbg(dev, "restored pin %u padcfg0 %#08x\n", - desc->number, readl(padcfg)); - } - - padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1); - val = readl(padcfg); - if (val != pads[i].padcfg1) { - writel(pads[i].padcfg1, padcfg); - dev_dbg(dev, "restored pin %u padcfg1 %#08x\n", - desc->number, readl(padcfg)); - } - - padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2); - if (padcfg) { - val = readl(padcfg); - if (val != pads[i].padcfg2) { - writel(pads[i].padcfg2, padcfg); - dev_dbg(dev, "restored pin %u padcfg2 %#08x\n", - desc->number, readl(padcfg)); - } - } + intel_restore_padcfg(pctrl, desc->number, PADCFG0, pads[i].padcfg0); + intel_restore_padcfg(pctrl, desc->number, PADCFG1, pads[i].padcfg1); + intel_restore_padcfg(pctrl, desc->number, PADCFG2, pads[i].padcfg2); } communities = pctrl->context.communities; @@ -1660,30 +1685,12 @@ int intel_pinctrl_resume_noirq(struct device *dev) unsigned int gpp; base = community->regs + community->ie_offset; - for (gpp = 0; gpp < community->ngpps; gpp++) { - writel(communities[i].intmask[gpp], base + gpp * 4); - dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp, - readl(base + gpp * 4)); - } + for (gpp = 0; gpp < community->ngpps; gpp++) + intel_restore_intmask(pctrl, i, base, gpp, communities[i].intmask[gpp]); base = community->regs + community->hostown_offset; - for (gpp = 0; gpp < community->ngpps; gpp++) { - const struct intel_padgroup *padgrp = &community->gpps[gpp]; - u32 requested = 0, value = 0; - u32 saved = communities[i].hostown[gpp]; - - if (padgrp->gpio_base < 0) - continue; - - requested = intel_gpio_is_requested(&pctrl->chip, - padgrp->gpio_base, padgrp->size); - value = intel_gpio_update_pad_mode(base + gpp * 4, - requested, saved); - if ((value ^ saved) & requested) { - dev_warn(dev, "restore hostown %d/%u %#8x->%#8x\n", - i, gpp, value, saved); - } - } + for (gpp = 0; gpp < community->ngpps; gpp++) + intel_restore_hostown(pctrl, i, base, gpp, communities[i].hostown[gpp]); } return 0; |