diff options
| author | Adam Kropelin <akropel1@rochester.rr.com> | 2005-09-16 19:28:18 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2005-09-17 11:50:03 -0700 |
| commit | c2fa4f4ad8ddf4b9fac344f1da7a25d4868f08f5 (patch) | |
| tree | 7ba8491513cc179748531a9c2e0ed1ba6b3ea80f /drivers/pci | |
| parent | d648daca1170945600756b31866d0362a67f2aae (diff) | |
| download | blackbird-op-linux-c2fa4f4ad8ddf4b9fac344f1da7a25d4868f08f5.tar.gz blackbird-op-linux-c2fa4f4ad8ddf4b9fac344f1da7a25d4868f08f5.zip | |
[PATCH] pciehp: Use dword accessors for PCI_ROM_ADDRESS
PCI_ROM_ADDRESS is a 32 bit register and as such should be accessed
using pci_bus_{read,write}_config_dword(). A recent audit of drivers/
turned up several cases of byte- and word-sized accesses. The harmful
ones were fixed by Linus directly. This patches up one of the remaining
harmless-but-still-wrong cases caught in the dragnet.
Signed-off-by: Adam Kropelin <akropel1@rochester.rr.com>
Cc: <kristen.c.accardi@intel.com>
Cc: Greg KH <greg@kroah.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/hotplug/pciehp_ctrl.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/drivers/pci/hotplug/pciehp_ctrl.c b/drivers/pci/hotplug/pciehp_ctrl.c index 0e0947601526..898f6da6f0de 100644 --- a/drivers/pci/hotplug/pciehp_ctrl.c +++ b/drivers/pci/hotplug/pciehp_ctrl.c @@ -2526,7 +2526,6 @@ configure_new_function(struct controller *ctrl, struct pci_func *func, int cloop; u8 temp_byte; u8 class_code; - u16 temp_word; u32 rc; u32 temp_register; u32 base; @@ -2682,8 +2681,7 @@ configure_new_function(struct controller *ctrl, struct pci_func *func, } /* End of base register loop */ /* disable ROM base Address */ - temp_word = 0x00L; - rc = pci_bus_write_config_word (pci_bus, devfn, PCI_ROM_ADDRESS, temp_word); + rc = pci_bus_write_config_dword (pci_bus, devfn, PCI_ROM_ADDRESS, 0x00); /* Set HP parameters (Cache Line Size, Latency Timer) */ rc = pciehprm_set_hpp(ctrl, func, PCI_HEADER_TYPE_NORMAL); |
