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| author | Murali Karicheri <m-karicheri2@ti.com> | 2014-07-21 12:58:41 -0400 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2014-07-22 16:03:54 -0600 |
| commit | a1c0ae9c24627a12c781ebd9947a6442861f6168 (patch) | |
| tree | 14cbf117ff087c445a53364130ab6d33b5f791bc /drivers/pci/host/pcie-designware.h | |
| parent | 47ff3de911a728cdf9ecc6ad777131902cff62b4 (diff) | |
| download | blackbird-op-linux-a1c0ae9c24627a12c781ebd9947a6442861f6168.tar.gz blackbird-op-linux-a1c0ae9c24627a12c781ebd9947a6442861f6168.zip | |
PCI: designware: Add config access-related pcie_host_ops for v3.65 hardware
DesignWare v3.65 hardware requires application space registers to be
configured to access the remote EP config space.
To support this, add rd_other_conf() and wr_other_conf() to pcie_host_ops.
[bhelgaas: changelog]
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Pratyush Anand <pratyush.anand@st.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
CC: Russell King <linux@arm.linux.org.uk>
CC: Grant Likely <grant.likely@linaro.org>
CC: Rob Herring <robh+dt@kernel.org>
CC: Richard Zhu <r65037@freescale.com>
CC: Kishon Vijay Abraham I <kishon@ti.com>
CC: Marek Vasut <marex@denx.de>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Pawel Moll <pawel.moll@arm.com>
CC: Mark Rutland <mark.rutland@arm.com>
CC: Ian Campbell <ijc+devicetree@hellion.org.uk>
CC: Kumar Gala <galak@codeaurora.org>
CC: Randy Dunlap <rdunlap@infradead.org>
CC: Grant Likely <grant.likely@linaro.org>
Diffstat (limited to 'drivers/pci/host/pcie-designware.h')
| -rw-r--r-- | drivers/pci/host/pcie-designware.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h index add652717a60..93062229850e 100644 --- a/drivers/pci/host/pcie-designware.h +++ b/drivers/pci/host/pcie-designware.h @@ -65,6 +65,10 @@ struct pcie_host_ops { u32 val, void __iomem *dbi_base); int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val); int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val); + int (*rd_other_conf)(struct pcie_port *pp, struct pci_bus *bus, + unsigned int devfn, int where, int size, u32 *val); + int (*wr_other_conf)(struct pcie_port *pp, struct pci_bus *bus, + unsigned int devfn, int where, int size, u32 val); int (*link_up)(struct pcie_port *pp); void (*host_init)(struct pcie_port *pp); }; |
