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authorCatalin Marinas <catalin.marinas@arm.com>2006-03-07 14:42:27 +0000
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-03-07 14:42:27 +0000
commit6a0e243069b09a323255f6e847c87d531961cd96 (patch)
tree575a7194c86b2b3e1b9db30e283a2f5705e89e99 /drivers/parisc/superio.c
parentd11d9b2dd2c43dd99a491df8a83ae28401db0044 (diff)
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[ARM] 3352/1: DSB required for the completion of a TLB maintenance operation
Patch from Catalin Marinas Chapter B2.7.3 in the latest ARM ARM (with v6 information) states that the completion of a TLB maintenance operation is only guaranteed by the execution of a DSB (Data Syncronization Barrier, formerly Data Write Barrier or Drain Write Buffer). Note that a DSB is only needed in the flush_tlb_kernel_* functions since the completion is guaranteed by a mode change (i.e. switching back to user mode) for the flush_tlb_user_* functions. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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