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| author | Suzuki K Poulose <suzuki.poulose@arm.com> | 2017-08-02 10:22:16 -0600 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2017-08-28 16:05:49 +0200 |
| commit | f2e931a2deab1ab426085f0357285410644f2945 (patch) | |
| tree | b61f1b5849575d47e3cb71f3d7bb9e0ab99ef611 /drivers/hwtracing/coresight/coresight-tmc.h | |
| parent | ebab6a7db2c599b5c29d033f3a20f86016d9a9b8 (diff) | |
| download | blackbird-op-linux-f2e931a2deab1ab426085f0357285410644f2945.tar.gz blackbird-op-linux-f2e931a2deab1ab426085f0357285410644f2945.zip | |
coresight tmc: Support for save-restore in ETR
The Coresight SoC 600 TMC ETR supports save-restore feature,
where the values of the RRP/RWP and STS.Full are retained
when it leaves the Disabled state. Hence, we must program the
RRP/RWP and STS.Full to a proper value. For now, set the RRP/RWP
to the base address of the buffer and clear the STS.Full register.
This can be later exploited for proper save-restore of ETR
trace contexts (e.g, perf).
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/hwtracing/coresight/coresight-tmc.h')
| -rw-r--r-- | drivers/hwtracing/coresight/coresight-tmc.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index f39caa6a45c3..d0da43a14246 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -119,6 +119,15 @@ enum tmc_mem_intf_width { #define TMC_ETR_SG (0x1U << 0) /* ETR has separate read/write cache encodings */ #define TMC_ETR_AXI_ARCACHE (0x1U << 1) +/* + * TMC_ETR_SAVE_RESTORE - Values of RRP/RWP/STS.Full are + * retained when TMC leaves Disabled state, allowing us to continue + * the tracing from a point where we stopped. This also implies that + * the RRP/RWP/STS.Full should always be programmed to the correct + * value. Unfortunately this is not advertised by the hardware, + * so we have to rely on PID of the IP to detect the functionality. + */ +#define TMC_ETR_SAVE_RESTORE (0x1U << 2) /** * struct tmc_drvdata - specifics associated to an TMC component |
