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authorVille Syrjälä <ville.syrjala@linux.intel.com>2013-12-09 18:54:13 +0200
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-12-11 23:52:13 +0100
commitb1c560d13d1aab194b467ca33d0be6ca6e829ee5 (patch)
tree90fe547d9c667014ce431b96a62657d1417cbbaf /drivers/gpu
parent3dda20a974e013a4985560904c0e491a70a25251 (diff)
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drm/i915: Extract p2 divider correctly for gen2 LVDS dual channel
In order to determine the correct p2 divider for LVDS on gen2, we need to check the CLKB mode from the LVDS port register to determine if we're dealing with single or dual channel LVDS. Cc: Bruno Prémont <bonbons@linux-vserver.org> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Tested-by: Bruno Prémont <bonbons@linux-vserver.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c9
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7b1b18d8f45c..8c4e384b8ae1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7951,12 +7951,17 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
else
i9xx_clock(refclk, &clock);
} else {
- bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
+ u32 lvds = I915_READ(LVDS);
+ bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
if (is_lvds) {
clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
DPLL_FPA01_P1_POST_DIV_SHIFT);
- clock.p2 = 14;
+
+ if (lvds & LVDS_CLKB_POWER_UP)
+ clock.p2 = 7;
+ else
+ clock.p2 = 14;
} else {
if (dpll & PLL_P1_DIVIDE_BY_TWO)
clock.p1 = 2;
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