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authorJordan Crouse <jcrouse@codeaurora.org>2016-11-28 12:28:28 -0700
committerRob Clark <robdclark@gmail.com>2016-11-28 15:14:12 -0500
commitae53a829d5c9715b651ee33e266eaa4454e7f2ad (patch)
tree1dcf37dc0cdaec9a9a90c22631f2e33f222c6115 /drivers/gpu/drm/msm/adreno/a4xx_gpu.c
parentc4a8d4756061f72cba52af1e3035c07769cee679 (diff)
downloadblackbird-op-linux-ae53a829d5c9715b651ee33e266eaa4454e7f2ad.tar.gz
blackbird-op-linux-ae53a829d5c9715b651ee33e266eaa4454e7f2ad.zip
drm/msm: gpu Add new gpu register read/write functions
Add some new functions to manipulate GPU registers. gpu_read64 and gpu_write64 can read/write a 64 bit value to two 32 bit registers. For 4XX and older these are normally perfcounter registers, but future targets will use 64 bit addressing so there will be many more spots where a 64 bit read and write are needed. gpu_rmw() does a read/modify/write on a 32 bit register given a mask and bits to OR in. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
Diffstat (limited to 'drivers/gpu/drm/msm/adreno/a4xx_gpu.c')
-rw-r--r--drivers/gpu/drm/msm/adreno/a4xx_gpu.c12
1 files changed, 2 insertions, 10 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
index 2abf2627f822..5858fb3bad0d 100644
--- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
@@ -520,16 +520,8 @@ static int a4xx_pm_suspend(struct msm_gpu *gpu) {
static int a4xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
{
- uint32_t hi, lo, tmp;
-
- tmp = gpu_read(gpu, REG_A4XX_RBBM_PERFCTR_CP_0_HI);
- do {
- hi = tmp;
- lo = gpu_read(gpu, REG_A4XX_RBBM_PERFCTR_CP_0_LO);
- tmp = gpu_read(gpu, REG_A4XX_RBBM_PERFCTR_CP_0_HI);
- } while (tmp != hi);
-
- *value = (((uint64_t)hi) << 32) | lo;
+ *value = gpu_read64(gpu, REG_A4XX_RBBM_PERFCTR_CP_0_LO,
+ REG_A4XX_RBBM_PERFCTR_CP_0_HI);
return 0;
}
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