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| author | Tero Kristo <t-kristo@ti.com> | 2014-10-03 16:57:14 +0300 |
|---|---|---|
| committer | Paul Walmsley <paul@pwsan.com> | 2014-11-13 09:26:45 -0700 |
| commit | 2e1a7b014f9c3d61fbf12b429f0479242264dbec (patch) | |
| tree | cecb7c3739740f991c03eda4f0fbfd075458cd82 /drivers/clk | |
| parent | e3ab6013ab06d3a861ed00c1f8d32aa4e6b66ddd (diff) | |
| download | blackbird-op-linux-2e1a7b014f9c3d61fbf12b429f0479242264dbec.tar.gz blackbird-op-linux-2e1a7b014f9c3d61fbf12b429f0479242264dbec.zip | |
ARM: OMAP3+: DPLL: use determine_rate() and set_rate_and_parent()
Currently, DPLLs are hiding the gory details of switching parent
within set_rate, which confuses the common clock code and is wrong.
Fixed by applying the new determine_rate() and set_rate_and_parent()
functionality to any clock-ops previously using the broken approach.
This patch also removes the broken legacy code.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/ti/dpll.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c index 79791e1bf282..85ac0dd501de 100644 --- a/drivers/clk/ti/dpll.c +++ b/drivers/clk/ti/dpll.c @@ -33,6 +33,9 @@ static const struct clk_ops dpll_m4xen_ck_ops = { .recalc_rate = &omap4_dpll_regm4xen_recalc, .round_rate = &omap4_dpll_regm4xen_round_rate, .set_rate = &omap3_noncore_dpll_set_rate, + .set_parent = &omap3_noncore_dpll_set_parent, + .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, + .determine_rate = &omap4_dpll_regm4xen_determine_rate, .get_parent = &omap2_init_dpll_parent, }; #else @@ -53,6 +56,9 @@ static const struct clk_ops dpll_ck_ops = { .recalc_rate = &omap3_dpll_recalc, .round_rate = &omap2_dpll_round_rate, .set_rate = &omap3_noncore_dpll_set_rate, + .set_parent = &omap3_noncore_dpll_set_parent, + .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, + .determine_rate = &omap3_noncore_dpll_determine_rate, .get_parent = &omap2_init_dpll_parent, }; @@ -61,6 +67,9 @@ static const struct clk_ops dpll_no_gate_ck_ops = { .get_parent = &omap2_init_dpll_parent, .round_rate = &omap2_dpll_round_rate, .set_rate = &omap3_noncore_dpll_set_rate, + .set_parent = &omap3_noncore_dpll_set_parent, + .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, + .determine_rate = &omap3_noncore_dpll_determine_rate, }; #else static const struct clk_ops dpll_core_ck_ops = {}; @@ -97,6 +106,9 @@ static const struct clk_ops omap3_dpll_ck_ops = { .get_parent = &omap2_init_dpll_parent, .recalc_rate = &omap3_dpll_recalc, .set_rate = &omap3_noncore_dpll_set_rate, + .set_parent = &omap3_noncore_dpll_set_parent, + .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, + .determine_rate = &omap3_noncore_dpll_determine_rate, .round_rate = &omap2_dpll_round_rate, }; @@ -106,6 +118,9 @@ static const struct clk_ops omap3_dpll_per_ck_ops = { .get_parent = &omap2_init_dpll_parent, .recalc_rate = &omap3_dpll_recalc, .set_rate = &omap3_dpll4_set_rate, + .set_parent = &omap3_noncore_dpll_set_parent, + .set_rate_and_parent = &omap3_dpll4_set_rate_and_parent, + .determine_rate = &omap3_noncore_dpll_determine_rate, .round_rate = &omap2_dpll_round_rate, }; #endif |
