diff options
author | Rhyland Klein <rklein@nvidia.com> | 2015-06-18 17:28:32 -0400 |
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committer | Thierry Reding <treding@nvidia.com> | 2015-12-17 13:37:54 +0100 |
commit | 17e9273a9e00a1fc8a64d6de3c7bb9e5020b1b73 (patch) | |
tree | 89222073f3bc755fc0dcae9f8e127b6da574c19a /drivers/clk | |
parent | b985114e2f946de069b00002bd46a4efba5334eb (diff) | |
download | blackbird-op-linux-17e9273a9e00a1fc8a64d6de3c7bb9e5020b1b73.tar.gz blackbird-op-linux-17e9273a9e00a1fc8a64d6de3c7bb9e5020b1b73.zip |
clk: tegra: pll: Add dyn_ramp callback
Add a callback to the pll_params for custom dynamic ramping
functions which can be specified per PLL.
Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk')
-rw-r--r-- | drivers/clk/tegra/clk-pll.c | 7 | ||||
-rw-r--r-- | drivers/clk/tegra/clk.h | 4 |
2 files changed, 11 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index 1decca98008f..8901004025e7 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -669,6 +669,13 @@ static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, _get_pll_mnp(pll, &old_cfg); + if (state && pll->params->defaults_set && pll->params->dyn_ramp && + (cfg->m == old_cfg.m) && (cfg->p == old_cfg.p)) { + ret = pll->params->dyn_ramp(pll, cfg); + if (!ret) + return 0; + } + if (state) _clk_pll_disable(hw); diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index c78d9d088a6d..8dac213fa672 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -213,6 +213,8 @@ struct tegra_clk_pll; * is already enabled, it will be done the first * time the rate is changed while the PLL is * disabled. + * @dyn_ramp: Callback which can be used to define a custom + * dynamic ramp function for a given PLL. * * Flags: * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for @@ -284,6 +286,8 @@ struct tegra_clk_pll_params { unsigned long (*adjust_vco)(struct tegra_clk_pll_params *pll_params, unsigned long parent_rate); void (*set_defaults)(struct tegra_clk_pll *pll); + int (*dyn_ramp)(struct tegra_clk_pll *pll, + struct tegra_clk_pll_freq_table *cfg); }; #define TEGRA_PLL_USE_LOCK BIT(0) |