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authorLinus Torvalds <torvalds@linux-foundation.org>2019-06-28 08:50:09 +0800
committerLinus Torvalds <torvalds@linux-foundation.org>2019-06-28 08:50:09 +0800
commit556e2f6020bf90f63c5dd65e9a2254be6db3185b (patch)
tree2f4e23a47c8f8619bfc1deff4e180a6b48ff14a7 /drivers/clk/ti
parent65ee21eb633c644501185502d51831c4dee22c7b (diff)
parent74684cce5ebd567b01e9bc0e9a1945c70a32f32f (diff)
downloadblackbird-op-linux-556e2f6020bf90f63c5dd65e9a2254be6db3185b.tar.gz
blackbird-op-linux-556e2f6020bf90f63c5dd65e9a2254be6db3185b.zip
Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd: "A handful of clk driver fixes and one core framework fix - Do a DT/firmware lookup in clk_core_get() even when the DT index is a nonsensical value - Fix some clk data typos in the Amlogic DT headers/code - Avoid returning junk in the TI clk driver when an invalid clk is looked for - Fix dividers for the emac clks on Stratix10 SoCs - Fix default HDA rates on Tegra210 to correct distorted audio" * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: socfpga: stratix10: fix divider entry for the emac clocks clk: Do a DT parent lookup even when index < 0 clk: tegra210: Fix default rates for HDA clocks clk: ti: clkctrl: Fix returning uninitialized data clk: meson: meson8b: fix a typo in the VPU parent names array variable clk: meson: fix MPLL 50M binding id typo
Diffstat (limited to 'drivers/clk/ti')
-rw-r--r--drivers/clk/ti/clkctrl.c7
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/clk/ti/clkctrl.c b/drivers/clk/ti/clkctrl.c
index 8e834317c97d..975995eea15c 100644
--- a/drivers/clk/ti/clkctrl.c
+++ b/drivers/clk/ti/clkctrl.c
@@ -229,6 +229,7 @@ static struct clk_hw *_ti_omap4_clkctrl_xlate(struct of_phandle_args *clkspec,
{
struct omap_clkctrl_provider *provider = data;
struct omap_clkctrl_clk *entry;
+ bool found = false;
if (clkspec->args_count != 2)
return ERR_PTR(-EINVAL);
@@ -238,11 +239,13 @@ static struct clk_hw *_ti_omap4_clkctrl_xlate(struct of_phandle_args *clkspec,
list_for_each_entry(entry, &provider->clocks, node) {
if (entry->reg_offset == clkspec->args[0] &&
- entry->bit_offset == clkspec->args[1])
+ entry->bit_offset == clkspec->args[1]) {
+ found = true;
break;
+ }
}
- if (!entry)
+ if (!found)
return ERR_PTR(-EINVAL);
return entry->clk;
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